hilscher netX 50, netX 51, netX 52 Migration Manual

Migration Guide

netX 50 to netX 51/52

Hilscher Gesellschaft für Systemautomation mbH

www.hilscher.com

Introduction 2/56

Table of Contents

1 Introduction.............................................................................................................................................3

1.1 Migration from netX 50 to netX 51/52............................................................................................3

1.2 List of Revisions.............................................................................................................. ...............5

1.3 Terms, Abbreviations and Definitions............................................................................................5

1.3.1 netX Signal Description.....................................................................................................................6

1.4 Legal Notes..................................................................................................................................10

1.4.1 Copyright.........................................................................................................................................10

1.4.2 Important Notes...............................................................................................................................10

1.4.3 Exclusion of Liability........................................................................................................................ 11

1.4.4 Export..............................................................................................................................................11

2 Comparison netX 50 with netX 51/52 .................................................................................................12

2.1 Overview ......................................................................................................................................12

2.1.1 Block Diagrams...............................................................................................................................12

2.1.2 Key Features...................................................................................................................................13

2.1.3 Enhancements of netX 51/52 against netX 50 ................................................................................14

3 Package, Pinning, Pad Cells ...............................................................................................................15

3.1 netX 52.........................................................................................................................................15

3.1.1 netX 52 Package............................................................................................................................. 15

3.1.2 netX 52 Pinning............................................................................................................................... 16

3.2 Alternative Function at Host Interface..........................................................................................22

3.3 netX 51.........................................................................................................................................24

3.3.1 Differences in Pinning and Pad Cells .............................................................................................. 24

3.4 MMIO Signals...............................................................................................................................32

4 General Changing ................................................................................................................................34

4.1 CPUs............................................................................................................................................34

4.1.1 Core CPU........................................................................................................................................34

4.1.2 Additional CPU................................................................................................................................ 34

4.2 Memory ........................................................................................................................................35

4.2.1 Layout..............................................................................................................................................35

4.3 Peripherals...................................................................................................................................36

4.4 Improved Memory Access Performance......................................................................................38

4.5 Activating 256 KByte as Dual-Port Memory and Detection of netX 51 or netX 52 Mode............39

4.6 Host Interface Modes...................................................................................................................40

4.7 Miscellaneous ..............................................................................................................................41

4.7.1 Operating Conditions....................................................................................................................... 41

4.7.2 Effects to existing Software............................................................................................................. 41

4.7.3 Effects to existing Development Tools ............................................................................................ 41

5 Erratas...................................................................................................................................................42

5.1 Fixed Erratas of netX 50 ..............................................................................................................42

5.2 New Errata for netX 51 / 52..........................................................................................................43

5.2.1 SYS LED lights doesn’t light correctly during active Boot Loader.................................................... 43

5.2.2 Simultaneous Operation of SDRAM and parallel Flash Memory at the Memory Interface ..............44

6 Design Examples..................................................................................................................................45

6.1 Design Example netX 51..............................................................................................................45

6.2 Design Example netX 52..............................................................................................................50

7 Appendix...............................................................................................................................................55

7.1 List of Tables................................................................................................................................55

7.2 List of Figures...............................................................................................................................55

7.3 Contacts.......................................................................................................................................56

Introduction 3/56

1 Introduction

1.1 Migration from netX 50 to netX 51/52

This manual describes the differences between the netX 50 and netX 51/52 with the aim to support and lead you during the migration from netX 50 to netX 51/52.

Real-Time-Ethernet / Fieldbus

8x IO-Link

3x UART

Peripherals

SPI / QSPI

Memory

Controller

Memory*

MEM

CAN MAC USB

2x I2C

672 KB

SRAM

64kB ROM

Switch

EXT

PHY PHY

xC ALUs

Channel 1

xPIC RISC CPU

Data

netX 51 / 52

* netX 52: None external Memory Bus

DPM

100 MHz

ARM 966

100 MHz

SPM

MAC PIO

xC ALUs

Channel 2

CPUs

Host-Interface

Figure 1: Functionality and Price of netX 6/50/51/52

Within the netX network controller family the netX 50 support all Real-Time-Ethernet systems. After a few years in the market it was necessary to upgrade the communication functionality to support PROFINET in the version 2.3. Together with some other enhancement we are offering the pin compatible controller netX 51. This can be placed on already existing netX 50 PCBs without modifications. It also supports IO-Link version 1.1 and includes much more RAM and an additional 32-Bit Risc Controller, CAN controller and a MAC.

The same functionality is available as netX 52 without an external memory bus in a smaller package for a lower price.

The netX 6 with the same housing as the netX 52 is designed as network access controller. This means it needs additional a host CPU to run the protocol stack. It includes only the 32-Bit Risc controller and less memory to realize only the Real-Time-Switch functionality.

Introduction 4/56 With the netX 52 you can build up a very compact (30 x 30 mm) 2-Port Real-Time-Ethernet

Interfaces for a very low price. With the loadable firmware the whole interface works a black box with a configurable 8-/16-/32-Bit Dual-Port-Memory or a SPI slave interface.

The following block diagram gives you an overview. The detailed schematic you will find in the annex of this Migration Guide.

Host-DPM

Host-SPI

UART or

Synchronization

USB

3.3V

GND

RDY RUN

MMIO28 MMIO29 MMIO30 MMIO31

MMIO12 MMIO13

PHY0_TXP

PHY0_TXN

PHY0_RXP

PHY0_RXN

MMIO14 MMIO15

PHY1_TXP

PHY1_TXN PHY1_RXP

PHY1_RXN

3.3V

4 MB

SPI Flash

Power on

Reset

3.3V

1.5V

DPM / SPM / PIO

RXD / SYNC0 TXD / SYNC1

USB

netX 52

SPI

POR

XTI

25 MHz

XTO

VDDC

VDDIO VSS

Figure 2: Design Example with netX 51

3.3V SYS

COM0

COM1

LINK ACT

Ethernet Channel 0

LINK ACT

Ethernet Channel 1

GND

Component Description Manufacturer Price

netX 52 Network Controller Hilscher 10,00 € W25Q32VSSIG QSPI Flash Windbond 0,70 € MAX811SEUS-T Reset Generator Maxim 0,20 € EN5312Q DC/DC Converter 3,3 V/1,5 V Enpirion 1,20 € 25 MHz Crystal div. 0,30 € 3x LED Dual Color div. 0,30 € Dual RJ45 with Magnetics / LEDs div. 2,80 € Rs / Cs / Ls div. 0,50 €

Material Cost per Interface in quantities of 10.000 pcs. without PCB 16,00 €

Table 1: Material Costs

Introduction 5/56

1.2 List of Revisions

Rev Date Name Chapter Revision

0 2012-02-01 AO All Created. 1 2012-02-08 HJH All Reviewed. 2 2012-04-25 HJH Added some additional explanation. 3 2012-11-28 HH 1.3.1 Signal name for MII interface starts with MII (instead of ETH) in Table 4.

2.1.1 Figure 4: MAC (to PHY) mappable into Host Interface.

3.1.2 Corrections

3.2 Section Alternative Function at Host Interface added.

5.2.2

4 2013-03-26 HH

4.6 Section Host Interface Modes updated. Table 22 revised. 5 2013-08-26 HH 4.5 Correction: 10 Kbyte to 10 kOhm

Table 2: List of Revisions

2.1.1,

2.1.2

Section Simultaneous Operation of SDRAM and parallel Flash Memory at the Memory Interface ad

Correctio

n: 1x I2C for netX 50

ded

1.3 Terms, Abbreviations and Definitions

Term Description

DPM DFP FTS Fast-Track Switching HIF INTRAM PBGA XiP xMAC xPEC xPIC

Table 3: Terms, Abbreviations and Definitions

All variables, parameters, and data used in this manual have the LSB/MSB (“Intel”) data format. This corresponds to the convention of the Microsoft C Compiler.

All IP addresses in this document have host byte order.

Dual-Port Memory Dynamic Frame Packing

Host InterFace INTernal SRAM Plastic Ball Grid Array

EXecution in Place Flexible Media Access Controller Flexible Protocol Execution Controller Flexible Peripheral Interface Controller

Introduction 6/56

1.3.1 netX Signal Description

General

PORn Power on Reset RSTINn Reset Input RSTOUTn Reset Output RDYn RDY-LED / Boot option RUNn RUN-LED / Boot option CLKOUT Clock out WDGACT Watchdog active

Oscillator

OSC_XTI 25 MHz Crystal Input OSC_XTO 25 MHz Crystal Output OSC_VSS Oscillator Power Supply Ground OSC_VDDC Oscillator Power Supply Core 1.5V

JTAG

JT_TRSTn JTAG Test Reset JT_TMS JTAG Test Mode Select JT_TCLK JTAG Test Clock JT_TDI JTAG Test Data Input JT_TDO JTAG Test Data Output

SPI

SPI0_CLK SPI 0 Clock SPI0_CS0n SPI 0 Chip Select 0 SPI0_CS1n SPI 0 Chip Select 1 SPI0_MISO SPI 0 Master Input Slave Output Data SPI0_MOSI SPI 0 Master Output Slave Input Data QSPI_CLK XiP / QSPI Clock QSPI_CSn XiP / QSPI Chip Select QSPI_SIO0...3 XiP / QSPI Serial IO Data 0…3

I2C

I2C_SCL I2C Serial Clock Line I2C_SDA I2C Serial Data Line

USB

USB_DNEG USB D- Line USB_DPOS USB D+ Line USB_VDDC USB Power Supply Core 1.5 V USB_VDDIO USB Power Supply IO 3.3 V

Test

BSCAN_TRST Reset Boundary Scan Controller TEST Activate Test Mode (left open) TMC1 Test Mode 1 (left open) TMC2 Test Mode 2 (left open)

Introduction 7/56

TACT_TRST Reset Test Controller MEM_IF_OM Memory Interface Output Mode, Connect to GND for normal operating mode

MMIO

MMIO0...48 Multiplex Matrix IO 0...48

Fieldbus Interface

XM0_TX XMAC0 Transmit Data XM0_ECLK External Clock input for XM0_TX / output from XMAC0 XM0_TX_ECLK XMAC0 Transmit Data, clocked with external clock FB0_CLK Clock output of fb0_clk XM1_TX XMAC1 Transmit Data XM1_ECLK External Clock input for XM1_TX / output from XMAC1 XM1_TX_ECLK XMAC1 Transmit Data, clocked with external clock FB1_CLK Clock output of fb1_clk

Ethernet MAC MII Interface

MII_RXCLK Ethernet MAC Rx Clock MII_RXD0...3 Ethernet MAC Rx Data 0...3 MII_RXDV Ethernet MAC Rx Data Valid MII_RXER Ethernet MAC Rx Error MII_TXCLK Ethernet MAC Tx Clock MII_TXD0...3 Ethernet MAC Tx Data 0...3 MII_TXEN Ethernet MAC Tx Enable MII_TXER Ethernet MAC Tx Error MII_COL Ethernet MAC Collision MII_CRS Ethernet MAC Carrier Sense

Memory Interface

MEMSR_CS0...2n SRAM Chip Select 0...2 MEMSR_OEn SRAM Output Enable MEMSR_WEn SRAM Write Enable MEMDR_CSn SDRAM Chip Select MEMDR_WEn SDRAM Write Enable MEMDR_RASn SDRAM RAS MEMDR_CASn SDRAM CAS MEMDR_CKE SDRAM Clock Enable MEMDR_CLK SDRAM Clock MEM_DQM0 Memory Data Qualifier Mask D0-7 MEM_DQM1 Memory Data Qualifier Mask D8-15 MEM_DQM2 Memory Data Qualifier Mask D16-23 MEM_DQM3 Memory Data Qualifier Mask D24-31 MEM_D0...31 Memory Data 0-31 MEM_A0...23 Memory Addre ss 0-23

Host Interface

DPM_A00...15 Dual-Port Memory Address 0..15 DPM_BE1n Dual-Port Memory Byte High Enable

Introduction 8/56

DPM_BE3n Dual-Port Memory Byte Enable 3 DPM_CSn Dual-Port Memory Chip Select DPM_D0...31 Dual-Port Memory Data 0...31 DPM_DIRQn Dual-Port Memory Data Interrupt DPM_SIRQn Dual-Port Memory Sync Interrupt DPM_RDn Dual-Port Memory Read DPM_WAITn Dual-Port Memory Wait DPM_WRn Dual-Port Memory Write SPM_MISO Serial-Port Memory (SPI) Master Input Slave Output Data SPM_MOSI Serial-Port Memory (SPI) Master Output Slave Input Data SPM_CSN Serial-Port Memory (SPI) Chip Select SPM_CLK Serial-Port Memory (SPI) Clock SPM_DIRQ Serial-Port-Memory Interrupt Source 1 SPM_SIRQ Serial-Port-Memory Interrupt Source 2

PHY0, PHY1

PHY0_RXN PHY 0 Receive Input negative PHY0_RXP PHY 0 Receive Input positive PHY0_TXN PHY 0 Transmit Output negative PHY0_TXP PHY 0 Transmit Output positive FO0_RD Fiberoptic Ethernet channel 0, Receive Data FO0_TD Fiberoptic Ethernet channel 0, Transmit Data FO0_EN Fiberoptic Ethernet channel 0, Enable FO0_SD Fiberoptic Ethernet channe l 0, Signal Detect PHY0_VSSAT1 PHY 0 Analog Ground Supply PHY0_VSSAT2 PHY 0 Analog Ground Supply PHY0_VSSAR PHY 0 Analog Ground Supply PHY0_VDDCART PHY 0 Analog TX/RX Power Supply 1.5 V PHY1_RXN PHY 1 Receive Input negative PHY1_RXP PHY 1 Receive Input positive PHY1_TXN PHY 1 Transmit Output negative PHY1_TXP PHY 1 Transmit Output positive FO1_RD Fiberoptic Ethernet channel 1, Receive Data FO1_TD Fiberoptic Ethernet channel 1, Transmit Data FO1_EN Fiberoptic Ethernet channel 1, Enable FO1_SD Fiberoptic Ethernet channe l 1, Signal Detect PHY1_VSSAT1 PHY 1 Analog Ground Supply PHY1_VSSAT2 PHY 1 Analog Ground Supply PHY1_VSSAR PHY 1 Analog Ground Supply PHY1_VDDCART PHY 1 Analog TX/RX Power Supply 1.5 V PHY_EXTRES Reference Resistor 12.4 k / 1% PHY_ATP Leave open! PHY_VSSACP PHY Analog Central Ground Supply PHY_VDDCAP PHY Analog Central Power Supply 1.5 V

Introduction 9/56

PHY_VDDIOAC PHY Analog Central Power Supply 3.3 V PHY_VSSAT PHY Analog Test Ground Supply PHY_VDDIOAT PHY Analog Test Power Supply 3.3 V

Power

VSS Ground Supply (except PHY and Oscillator) VDDC Power Supply, Core 1.5 V (except PHY and Oscillator) VDDIO Power Supply, IO Buffer 3.3 V (except PHY and USB)

ETM

ETM_TCLK ETM Trace clock ETM_TSYNC ETM Trace synchronization ETM_DRQ ETM Debug request ETM_DACK ETM Debug acknowledge ETM_PSTAT0 ETM Pipe status 0 ETM_PSTAT1 ETM Pipe status 1 ETM_PSTAT2 ETM Pipe status 2 ETM_TPKT00 ETM Trace packet 0 ETM_TPKT01 ETM Trace packet 1 ETM_TPKT02 ETM Trace packet 2 ETM_TPKT03 ETM Trace packet 3 ETM_TPKT04 ETM Trace packet 4 ETM_TPKT05 ETM Trace packet 5 ETM_TPKT06 ETM Trace packet 6 ETM_TPKT07 ETM Trace packet 7 ETM_TPKT08 ETM Trace packet 8 ETM_TPKT09 ETM Trace packet 9 ETM_TPKT10 ETM Trace packet 10 ETM_TPKT11 ETM Trace packet 11 ETM_TPKT12 ETM Trace packet 12 ETM_TPKT13 ETM Trace packet 13 ETM_TPKT14 ETM Trace packet 14 ETM_TPKT15 ETM Trace packet 15

Table 4: Signal Description

Introduction 10/56

1.4 Legal Notes

1.4.1 Copyright

texts, documentation, etc.) are protected by German and international copyright law as well as international trade and protection provisions. You are not authorized to duplicate these in whole or in part using technical or mechanical methods (printing, photocopying or other methods), to manipulate or transfer using electronic systems without prior written consent. You are not permitted to make changes to copyright notices, markings, trademarks or ownership declarations. The included diagrams do not take the patent situation into account. The company names and product descriptions included in this document may be trademarks or brands of the respective owners and may be trademarked or patented. Any form of further use requires the explicit consent of the respective rights owner.

1.4.2 Important Notes

The user manual, accompanying texts and the documentation were created for the use of the products by qualified experts, however, errors cannot be ruled out. For this reason, no guarantee can be made and neither juristic responsibility for erroneous information nor any liability can be assumed. Descriptions, accompanying texts and documentation included in the user manual do not present a guarantee nor any information about proper use as stipulated in the contract or a warranted feature. It cannot be ruled out that the user manual, the accompanying texts and the documentation do not correspond exactly to the described features, standards or other data of the delivered product. No warranty or guarantee regarding the correctness or accuracy of the information is assumed.

We reserve the right to change our products and their specification as well as related user manuals, accompanying texts and documentation at all times and without advance notice, without obligation to report the change. Changes will be included in future manuals and do not constitute any obligations. There is no entitlement to revisions of delivered documents. The manual delivered with the product applies.

Hilscher Gesellschaft für Systemautomation mbH is not liable under any circumstances for direct, indirect, incidental or follow-on damage or loss of earnings resulting from the use of the information contained in this publication.

Introduction 11/56

1.4.3 Exclusion of Liability

The software was produced and tested with utmost care by Hilscher Gesellschaft für Systemautomation mbH and is made available as is. No warranty can be assumed for the performance and flawlessness of the software for all usage conditions and cases and for the results produced when utilized by the user. Liability for any damages that may result from the use of the hardware or software or related documents, is limited to cases of intent or grossly negligent violation of significant contractual obligations. Indemnity claims for the violation of significant contractual obligations are limited to damages that are foreseeable and typical for this type of contract.

It is strictly prohibited to use the software in the following areas:

 for military purposes or in weapon systems;  for the design, construction, maintenance or operation of nuclear facilities;  in air traffic control systems, air traffic or air traffic communication systems;  in life support systems;  in systems in which failures in the software could lead to personal injury or injuries leading to

death.

We inform you that the software was not developed for use in dangerous environments requiring fail-proof control mechanisms. Use of the software in such an environment occurs at your own risk. No liability is assumed for damages or losses due to unauthorized use.

1.4.4 Export

The delivered product (including the technical data) is subject to export or import laws as well as the associated regulations of different counters, in particular those of Germany and the USA. The software may not be exported to countries where this is prohibited by the United States Export Administration Act and its additional provisions. You are obligated to comply with the regulations at your personal responsibility. We wish to inform you that you may require permission from state authorities to export, re-export or import the product.

Comparison netX 50 with netX 51/52 12/56

2 Comparison netX 50 with netX 51/52

2.1 Overview

2.1.1 Block Diagrams

Block Diagram netX 50

Figure 3: Block Diagram of netX 50

Block Diagram netX 51/52

Figure 4: Block Diagram of netX 51/52

Comparison netX 50 with netX 51/52 13/56

2.1.2 Key Features

The netX 51 and netX 52 is an enhancement of the existing netX 50 to fulfil the increasing demands of performance and functionality of industrial networks. These controllers are supporting the PROFINET Specification 2.3 with the new option of Dynamic Frame Packaging and the IO-Link Version 1.1 with long telegrams.

We followed the successful strategy of the netX 10 controllers and implemented a second RISC CPU. This can be programmed by the user to work parallel with the ARM CPU handling very fast IO signals without interfering the communication tasks.

Further more we increased the application interface with a dedicated CAN Controller and an Ethernet MAC. Very often these communication lines were the reason to use the more expensive three channel controller netX 100.

To increase the over all performance of the netX 51 / 52 and to allow real single chip solutions the internal memory is dramatically enlarged from 96 KByte to 672 KByte.

netX 50 51 52

CPU ARM 966-200 MHz ARM 966-100 MHz Secondary CPU xPIC-100 MHz SRAM / ROM / ITCM / DTCM [kByte] 96 / 64 / 8 / 8 672 / 64 / - / Separate External Memory Bus X X DPM parallel [Data Width] 8 / 16 / 32 DPM serial - X Host Interface PIOs 54 58 Host Interface usable as

ExtMemBus / SDRAM / MAC Communication Channels 2

Internal PHYs 2 CAN Controller / Ethernet MAC - / - X / X IO-Link: Channels/Version 8 / V1.0 8 / V1.0, V1.1 USB Host / Device X / X - / X UARTs / I2C / SPI / QSPI 3 / 1 / 2 / - 3 / 2 / 1 / 1 IEEE 1588 System Time X IOs (without Host Interface PIOs) 32 40 24 Pins / Package 324 / PBGA 244 / PBGA Grid / size [mm] 1.0 mm / 19x19 0.8 mm / 15x15 Fieldbus / RTE (w/o PN IRT with DFP and FTS) X / X Support PROFINET IRT with DFP - X Support Fast Track Switching (FTS) - X

Table 5: Key Features

- / - / -

X / - / X

X / X / X

Comparison netX 50 with netX 51/52 14/56

2.1.3 Enhancements of netX 51/52 against netX 50

 Significant more internal memory available to accelerate tasks  High performance access to INTRAM blocks via TCM channels of ARM CPU  Reduced Power Consumption with higher Performance based on lower System Clock with

ARM CPU high speed Memory Access via two TCM channels

 Improved ARM performance on SDRAM  Performance of communication channel doubled to support high performance RTE-systems

as PROFINET IRT with Dynamic Frame Packing or Fast-Track-Switching

 xPIC as additional 100 MHz RISC CPU for time-critical tasks  Separate CAN Controller in addition to two communication channels  Separate Ethernet MAC in addition to two communication channels (Datalink layer done by

xPIC)

 New generation of Renesas’ internal PHYs for shortening cut-through delays  Dual-Port Memory: minimized access times, can run without Wait / Busy-line  Serial access to internal DPM via SPI/QSPI Slave interface without interfering of ARM CPU  Support IO-Link V1.1 specification  Dedicated Quad SPI Controller instead using internal communication controller for fast

loading of program code

 Support of XiP (Execution in Place). Execution of program code directly out of serial flash

Package, Pinning, Pad Cells 15/56

3 Package, Pinning, Pad Cells

The netX 51 comes in a 324 pin PBGA package and has the same pinning and size as the netX 50 has. It is designed to replace the netX 50 without changing the PCB (drop-in-replacement).

The netX 52 comes in a smaller 244 pin PBGA package with 0.8mm grid.

3.1 netX 52

3.1.1 netX 52 Package

Figure 5: Mechanical Dimensions of the netX 52

Symbol Min Type Max

A1 0.29 mm 0.35 mm 0.41 mm A2 1.11 mm b 0.40 mm 0.50 mm 0.55 mm E 14.90 mm 15.00 mm 15.10 mm e 0.80 mm D 14.90 mm 15.00 mm 15.10 mm

Table 6: Mechanical Dimensions of the netX 52

Package, Pinning, Pad Cells 16/56

3.1.2 netX 52 Pinning

Pin Pad

A03 IOU9 IO DPM_A0/BE0n DPM Dual-Port Memory Address 0 B06 IOU9 IO DPM_A1/BE2n DPM Dual-Port Memory Address 1 B12 IOU9 IO DPM_A10 DPM Dual-Port Memory Address 10 A14 IOU9 IO DPM_A11 DPM Dual-Port Memory Address 11 B13 IOU9 IO DPM_A12 DPM Dual-Port Memory Address 12 A13 IOU9 IO DPM_A13 DPM Dual-Port Memory Address 13 A12 IOU9 IO DPM_A14 DPM Dual-Port Memory Address 14 B11 IOU9 IO DPM_A15 DPM Dual-Port Memory Address 15 A17 IOU9 IO DPM_A16 DPM Dual-Port Memory Address 16 A18 IOU9 IO DPM_A17 DPM Dual-Port Memory Address 17 C06 IOU9 IO DPM_A2 DPM Dual-Port Memory Address 2 C07 IOU9 IO DPM_A3 DPM Dual-Port Memory Address 3 B08 IOU9 IO DPM_A4 DPM Dual-Port Memory Address 4 A07 IOU9 IO DPM_A5 DPM Dual-Port Memory Address 5 B09 IOU9 IO DPM_A6 DPM Dual-Port Memory Address 6 C09 IOU9 IO DPM_A7 DPM Dual-Port Memory Address 7 C13 IOU9 IO DPM_A8 DPM Dual-Port Memory Address 8 A10 IOU9 IO DPM_A9 DPM Dual-Port Memory Address 9 A16 IOU9 IO DPM_BHEn/BE1n DPM Dual-Port Memory Byte Enable 1 A15 IOU9 IO DPM_CSn DPM Dual-Port Memory Chip Select A01 IOU9 IO DPM_D0 DPM Dual-Port Memory Data 0 C02 IOU9 IO DPM_D1 DPM Dual-Port Memor y Data 1 D02 IOU9 IO DPM_D2 DPM Dual-Port Memor y Data 2 B03 IOU9 IO DPM_D3 DPM Dual-Port Memory Data 3 B04 IOU9 IO DPM_D4 DPM Dual-Port Memory Data 4 B02 IOU9 IO DPM_D5 DPM Dual-Port Memory Data 5 A05 IOU9 IO DPM_D6 DPM Dual-Port Memory Data 6 B05 IOU9 IO DPM_D7 DPM Dual-Port Memory Data 7 G18 IOU9 IO DPM_D8 DPM Dual-Port Memory Data 8 G16 IOU9 IO DPM_D9 DPM Dual-Port Memory Data 9 F17 IOU9 IO DPM_D10 DPM Dual-Port Memory Data 10 D18 IOU9 IO DPM_D11 DPM Dual-Port Memory Data 11 C18 IOU9 IO DPM_D12 DPM Dual-Port Memory Data 12 B18 IOU9 IO DPM_D13 DPM Dual-Port Memory Data 13 C17 IOU9 IO DPM_D14 DPM Dual-Port Memory Data 14 B17 IOU9 IO DPM_D15 DPM Dual-Port Memory Data 15 G17 IOU9 IO DPM_D16 DPM Dual-Port Memory Data 16 F18 IOU9 IO DPM_D17 DPM Dual-Port Memory Data 17 E18 IOU9 IO DPM_D18 DPM Dual-Port Memory Data 18 E17 IOU9 IO DPM_D19 DPM Dual-Port Memory Data 19 C12 IOU9 IO DPM_D20 DPM Dual-Port Memory Data 20 C11 IOU9 IO DPM_D21 DPM Dual-Port Memory Data 21 A11 IOU9 IO DPM_D22 DPM Dual-Port Memory Data 22 C10 IOU9 IO DPM_D23 DPM Dual-Port Memory Data 23

Signal Group Description

Out

Package, Pinning, Pad Cells 17/56

Pin Pad

A09 IOU9 IO DPM_D24 DPM Dual-Port Memory Data 24 A08 IOU9 IO DPM_D25 DPM Dual-Port Memory Data 25 A06 IOU9 IO DPM_D26 DPM Dual-Port Memory Data 26 B07 IOU9 IO DPM_D27 DPM Dual-Port Memory Data 27 A02 IOU9 IO DPM_D28 DPM Dual-Port Memory Data 28 A04 IOU9 IO DPM_D29 DPM Dual-Port Memory Data 29 D03 IOU9 IO DPM_D30 DPM Dual-Port Memory Data 30 H17 IOU9 IO DPM_D31 DPM Dual-Port Memory Data 31 D16 IOU9 IO DPM_DIRQn DPM Dual-Port Memory Data Interrupt B15 IOU9 IO DPM_RDn DPM Dual-Port Memory Read C15 IOU9 IO DPM_WAITn DPM Dual-Port Memory Wait C08 IOD9 IO DPM_SIRQn DPM Dual-Port Memory Sync Interrupt B16 IOU9 IO DPM_WRHn/BE3n DPM Dual-Port Memory Byte Enable 3 B14 IOU9 IO DPM_WRn/WRLn DPM Dual-Port Memory Write E03 IDS I BSCAN_TRST GENERAL Reset Boundary Scan Controller V07 PLL power supply I OSC_VDDC GENERAL Oscillator Power Supply Core 1.5V U07 PLL power supply I OSC_VSS GENERAL Oscillator Power Supply Ground U08 Ocsillator pad I OSC_XTI GENERAL 25 MHz Crystal Input V08 Ocsillator pad O OSC_XTO GENERAL 25 MHz Crystal Output C01 IUS I PORn GENERAL Power on Reset F01 IOD6 IO RDYn GENERAL RDY-LED / Boot start option D01 OZ6 O RSTOUTn GENERAL Reset Output F02 IOD6 IO RUNn GENERAL RUN-LED / Boot start option G02 IDS I TACT_TRST GENERAL Reset Test Controller B10 ID I TEST GENERAL Activate Test Mode (left open) F03 Internal Test pin, tmc1 I TMC1 GENERAL Test Mode 1 (left open) G03 Internal Test pin, tmc2 I TMC2 GENERAL Test Mode 2 (left open) H18 IOZUS9 (5K pull up) IO I2C_SCL I2C I2C Serial Clock Line H16 IOZUS9 (5K pull up) IO I2C_SDA I2C I2C Serial Data Line H01 IUS I JT_TCLK JTAG JTAG Test Clock J03 IUS I JT_TDI JT AG JTAG Test Data Input M03 OZ6 O JT_TDO JTAG JTAG Test Data Output K03 IUS I JT_TMS JTAG JTAG Test Mode Select H03 IDS I JT_TRSTn JTAG JTAG Test Reset T13 - - n. c. - Reserved T10 1,5V Core Power VDDC POWER Power Supply Core 1.5V T12 1,5V Core Power VDDC POWER Power Supply Core 1.5V T11 3,3V IO Power VDDIO POWER Power Supply IO 3.3V U14 3,3V IO Power VDDIO POWER Power Supply IO 3.3V U10 - - n. c. - Reserved V10 - - n. c. - Reserved U12 - - n. c. - Reserved V12 - - n. c. - Reserved U11 - - n. c. - Reserved V11 - - n. c. - Reserved U13 - I- n. c. - Reserved

Signal Group Description

Out

+ 39 hidden pages

hilscher netX 50, netX 51, netX 52 Migration Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Migration from netX 50 to netX 51/52

1.2 List of Revisions

1.3 Terms, Abbreviations and Definitions

1.3.1 netX Signal Description

1.4 Legal Notes

1.4.1 Copyright

1.4.2 Important Notes

1.4.3 Exclusion of Liability

1.4.4 Export

2 Comparison netX 50 with netX 51/52

2.1 Overview

2.1.1 Block Diagrams

2.1.2 Key Features

2.1.3 Enhancements of netX 51/52 against netX 50

3 Package, Pinning, Pad Cells

3.1 netX 52

3.1.1 netX 52 Package

3.1.2 netX 52 Pinning