Hifn 9155, 9150 User Manual
9150, 9155
Evaluation Card
User Guide
Hifn Confidential
UG-0210-00, 9150, 9155 Evaluation Card User Guide © April 15, 2010, Hi/fn
04/10
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 Hifn Security Processor Chip . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.3 Gigabit Ethernet Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.4 Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.5 DDR2 SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.6 RMII Fast Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.7 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.8 CPLD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.9 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.1.1 JP28: External Power Supply Connector. . . . . . . . . . . . . . . . . . . 18
3.1.2 P4: PCI Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Ethernet Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 U54, U56: SFP Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 U64, U65, U67: RJ45 Connectors . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 P1: JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Debug Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.1 JP6: SFP Control/Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.2 Amp MICTOR Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Jumpers, LEDs, and Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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4.1.1 JP34: Device ID Header (DEV-ID). . . . . . . . . . . . . . . . . . . . . . . 29
4.1.2 JP45: Secure Features Header (SEC) . . . . . . . . . . . . . . . . . . . . 29
4.1.3 JP49: System Configuration Header 1 (MISC-1) . . . . . . . . . . . . . 29
4.1.4 JP42: System Configuration Header 2 (MISC-2) . . . . . . . . . . . . . 30
4.1.5 JP43: SMI/I2C Interface Select Header . . . . . . . . . . . . . . . . . . . 31
4.1.6 JP41: Flash/RTC Interface Select Header . . . . . . . . . . . . . . . . . . 31
4.2 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.1 Communications Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.2 Card Status LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.3 915x Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3 Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 PHY Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.1 SFP Ports (Host-0 and Net-0) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.2 MDI Ports (Host-1 and Net-1) . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.3 MII Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.2 Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Addendum I Document Changes/Revisions . . . . . . . . . . . . . . . . . . 38
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List of Figures
Figure 1-1. Evaluation Card Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 2-1. Evaluation Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2-2. Evaluation Card Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3-1. 915x Evaluation Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3-2. SFP Connector Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 3-3. Debug Connector Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4-1. Jumpers, LEDs, and Switch Locations . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 4-2. JP34 Device ID Jumper Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 4-3. JP45 Secure Features Jumpers Diagram . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 4-4. JP49 System Configuration Header 1 Diagram . . . . . . . . . . . . . . . . . . .29
Figure 4-5. JP42 System Configuration Header 2 Diagram . . . . . . . . . . . . . . . . . . .30
Figure 4-6. JP43 SMI/I2C Select Header Diagram . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 4-7. JP41 Flash/RTC Select Header Diagram . . . . . . . . . . . . . . . . . . . . . . . .32
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List of Tables
Table 2-1. PHY Device Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 2-2. JTAG Chip and Revision IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 2-3. General Purpose I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3-1. External Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 3-2. PCI Power Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3-3. SFP Transceiver Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3-4. JTAG Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3-5. SFP Control/Status Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 3-6. J6: Net-0/Net-1Gigabit Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3-7. J5: Host-1 Gigabit Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 3-8. J7: Host-0 Gigabit Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 3-9. J1: System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 3-10. J2: DDR2 Addr/Ctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 3-11. J3: DDR2 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 3-12. JP48: 915x Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 4-1. Device ID Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 4-2. JP49 System Configuration Header 1 . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 4-3. JP42 System Configuration Header 2 . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 4-4. JP43 SMI/I2C Select Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 4-5. JP41 Flash/RTC Select Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 4-6. PHY-Driven Communications LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 4-7. 915x-Driven Communications LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 4-8. LEDs for RMII AC Access Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 4-9. Card Status LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 4-10. 915x Status LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 4-11. Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 6-1. Evaluation Card Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6-2. Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
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Preface
About this Document
Welcome to the User Guide for the Hifn 9150/9155 Evaluation Card. This document
provides details on configuration, connection and operation of the 9150/9155 Evaluation
Card.
The term “915x” will be used to denote either of the 9150 or 9155 devices. A single
evaluation card supports both the 9150 and 9155 devices and has the following part
number:
915xREF
Audience
This document assumes you are already familiar with the Hifn 9150 or 9155 security
processor devices. The intended audience is integrators and application developers
responsible for and familiar with software and hardware architecture of a target system.
Prerequisite
Before proceeding, you should generally understand:
• Software and hardware of the target system
• General networking concepts
Related Documents
• UG-0202, 9150, 9155 FlowThrough Application Programming Interface
Programming Guide
• UG-0204, 9150, 9155 Security Manager Application Programming Interface
Programming Guide
Document Organization
This document is organized as follows:
Chapter 1, “Introduction", describes the system application and basic connectivity.
Chapter 2, “Overview", provides brief description of each of the major components and
interfaces.
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Chapter 3, “Connectors", provides connectivity details for the power and signal interfaces.
Chapter 4, “Jumpers, LEDs, and Switches", defines the jumpers, LEDs and switch settings.
Chapter 5, “Operation", describes the high level evaluation card operation and PHY
configuration.
Chapter 6, “Specifications", lists the A/C, D/C and environmental specification for the
evaluation card.
Customer Support
For technical support about this product, please contact your local Hifn sales office,
representative, or distributor.
Web Site
For general information about Hifn and Hifn products refer to:
www.hifn.com
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1 Introduction
The Hifn 9150/9155 (915x) Evaluation Card is a standard PCI form-factor card that
connects as a “bump-in-the-wire” in Gigabit Ethernet links. It plugs into a standard 32-bit
PCI slot, however it only uses the PCI connector for power. An optional power connection
layout is provided to allow using the evaluation card on a bench top, rather than installed
in a PCI slot.
All communications with the card is done through its rear-panel Gigabit Ethernet
connections, or optionally via the 100 Mbps Fast Ethernet control port at the opposite edge
of the card. The primary ports are capable of operating at 10/100/1000 Mbps speeds (in
copper mode).
The Hifn 915x FlowThrough™ security processor chip is the heart of this card. Its two host
ports and two network ports interface through four separate single-port Gigabit PHY devices
to the rear panel Ethernet connectors. These four interfaces make up two distinct channels
through the 915x where each channel is composed of one host port and one network port.
The channel 0 ports utilize “SFP” pluggable modules, allowing either copper or fiber-optic
connections. The channel 1 ports are supported with RJ-45 copper-only connectors.
All of the bus interfaces to the 915x devices are instrumented with MICTOR test connectors
for interfacing with a Logic Analyzer or digital oscilloscope. A JTAG test connector is also
populated to allow boundary scan testing as well as for access to the on-chip processors.
1.1 Applications
The 915x Evaluation Card is a useful tool to allow design, development and debug of
software running on a target host system. The host port(s) of the 915x Evaluation Card are
connected to GigE ports on the host platform (i.e. HBA, TBA, NIC, Switch) and the network
port(s) are connected into a test network.
Refer to the sample system diagram in Figure 1-1.
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Figure 1-1. Evaluation Card Typical Application
The intent of the evaluation card is to simulate the actual software environment of the end
system to the greatest extent possible. This is easily achieved due to the FlowThrough
nature of the Hifn 915x devices. From the host perspective, software commands sent out
the Ethernet port will be intercepted and acted upon just as if the chip were installed on the
same PCB as the host GMAC/TOE/Network Processor. Given this, the evaluation card can be
used to test virtually all of the customer-developed software at both the driver and the
application layers. This includes: boot-load, initialization, port control & monitoring,
fragment reassembly, and security management.
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2 Overview
2.1 Card Layout
Figure 2-1 below identifies the significant functional components on the evaluation card
with the exception of the LEDs, jumpers, connectors, and switches, which are described
fully in a later chapter. The Hifn security processor chip is in the center of the card and
clearly labeled.
Figure 2-1. Evaluation Card Layout
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2.2 Functional Overview
2.2.1 Block Diagram
Figure 2-2. Evaluation Card Block Diagram
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