Electronics Industries Co., Ltd.
System IC Division
DESCRIPTION
HV7121B is a highly integrated single chip CMOS color image sensor using Hyundai 0.5um CMOS process
developed for image application to realize high efficiency R/G/B photo sensor. The sensor has 414X314 pixels
total, and 400X300 pixels effective. Each pixel is high photo sensitive, small size active pixel element that
converts photons to analog voltage signal. The sensor has three on-chip 8 bit Digital to Analog Convert (DAC)
and 414 comparators to digitize the pixel output. The three on-chip 8 bit DAC can be used for independent
R/G/B gain control. Hyundai proprietary on-chip CDS circuit can reduce Fixed Pattern Noise (FPN)
dramatically. The whole 8 bit digital color raw data is directly available on the package pins and just few
control signals are needed for whole chip control, so it is very ease to configure a system using the sensor.
FEATURES
l 400 x 300 pixels resolutionl Full function control through standard I2C bus
l 8um x 8um square pixelsl Built-in AGC
l High efficiency R/G/B color photo sensorsl 48Pin CLCC / 20Pin CDIP
l Integrated 8-bit ADC for direct digital outputl Bayer RGB color pattern
l Low power 3.3V operation (5V tolerant I/O)l Anti-blooming circuit
l Integrated pan control and window sizingl Flexible exposure time control
l Clock speed up to 15MHzl Integrated on-chip timing and drive control
l Programmable frame rate and synchronous
l 1/4" optical format
format
TECHNICAL SPECIFICATION FUNCTIONAL BLOCK DIAGRAM
Pixel resolution402x302
Pixel size8x8um
2
Fill factor30%
FormatCIF
SensitivityTBD
S/RTBD
Supply voltage for analog3.3V
Supply voltage for digital3.3V
Supply voltage for 5V tolerant input5.0V
Supply current
Operating temperature0~40 C
Technology0.5um 3metal CMOS
I2C
Control
Register
& Logic
Pixel
Array
Decoder/Pixel Driver
ADC Block
Line Buffer
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 1 1999 Hyundai System IC Division
HV7121B
CMOS IMAGE SENSOR
With 8-bit ADC
Electronics Industries Co., Ltd.
System IC Division
ELECTRICAL CHARACTERISTIC
Absolute Maximum Ratings
l Supply voltage(Analog, Digital):3.0 V~3.6 V
l Voltage on any input pins:0 V~5.0 V
l Operating Temperature :0¡É~40¡É
Note : Input pins are 5V tolerant. Stresses exceeding the absolute maximum ratings may induce failure.
DC Operating Conditions
SymbolParameterUnitsMin.Max.Load[pF]Notes
V
dd
V
ih
V
il
V
oh
V
ol
T
a
Internal operation supply voltageVolt3.03.6
Input voltage logic "1"Volt2.056.5
Input voltage logic "0"Volt00.86.5
Output voltage logic "1"Volt2.153.660
Output voltage logic "0"Volt0.40.460
Ambient operating temperatureCelsius040
AC Operating Conditions
SymbolParameterMax Operation FrequencyUnitsNotes
MCLKMain clock frequency20MHz1
SCKI2C clock frequency400kHz2
1. MCLK can be divided according to Clock Divide Register for internal clock.
2. SCK is driven by host processor. For the detail serial bus timing, refer to I
2
C Spec.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 2 1999 Hyundai System IC Division
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
With 8-bit ADC
System IC Division
ELECTRO-OPTICAL CHARACTERISTICS
ParameterUnitsMin.TypicalMax.Note
SensitivitymV / lux secTBDTBDTBD1)
HV7121B
Dark SignalmVTBD
Output Saturation SignalmVTBDTBDTBD3)
Blooming%TBD
Dynamic RangedBTBDTBD4)
ShadingTBD5)
Fixed Pattern Noise%TBD6)
Note:
1) Measured at 26 [1ux] illumination for exposure time 10 [msec]
2) Measured at zero illumination for exposure time 48 [msec] (Ta = 25 C)
3) Measured at Vdd =3.3V
4) 48dB is limited by 8-bit ADC
5) Variation in individual pixel response over entire sensor area
6) Measured at zero [lux] and 70 [lux] illumination for exposure time 10 [msec] Variation of average
pixel response from column(i) to column(i+2) and from row(i) to raw(i+2) due to Bayer Pattern RGB
sampling.
TBD
2)
Remarks : Master Clock = 15MHz
*All values are measured by raw image data from image sensor.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 3 1999 Hyundai System IC Division
HV7121B
CMOS IMAGE SENSOR
With 8-bit ADC
MCLK
Electronics Industries Co., Ltd.
System IC Division
INPUT / OUTPUT AC CHARACTERISTICS
l All output timing delays are measured with output load 60[pF].
l Output delay include the internal clock path delay[6ns] and output driving delay that changes in
respect to the output load, the operating environment, and a board design.
lDue to the variable valid time delay of the output, output signals may be latched in the negative
edge of MCLK for the stable data transfer between the image sensor and a host for less than
15MHz operation.
MCLK to HSYNC/VSYNC Timing
T1
MCLK
HSYNC/VSYNC
T2
T1
T1 : MCLK rising to HSYNC/VSYNC Valid maximum Time : 18ns [output load: 60pF]
T2 : HSYNC/VSYNC Valid Time : minimum 1Clock(subject to T1, T2 timing rule)
MCLK to DATA Timing
T3
DATA[7:0]
Valid DATA
T3
T3 : MCLK rising to DATA Valid maximum Time : 18ns [output load: 60pF]
Note) HSYNC signal is high when valid data is on the DATA bus.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 4 1999 Hyundai System IC Division
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
With 8-bit ADC
System IC Division
INPUT / OUTPUT AC CHARACTERISTICS (Continue)
ENB Timing
MCLK
ENB
HV7121B
T5T4
T4 : ENB Setup Time : 5ns
T5 : ENB Hold Time : 5ns
T6 : ENB Valid Time : minimum 2 Clock
RESET Timing
Must in Valid (active LOW) state at least 8MCLK periods
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 5 1999 Hyundai System IC Division
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
With 8-bit ADC
System IC Division
INPUT / OUTPUT AC CHARACTERISTICS CONTINUE
I2C Bus (Programming Serial Bus) Timing
HV7121B
stopstart
SDA
tbuf
SCK
thd;sta
tlow
I2C Bus Interface Timing
ParameterSymbolMin.Max.Unit
SCK clock frequency f
Time that I2C bus must be free before a new
transmission can start
tr
tf
thd;datthightsu;dattsu;statsu;sto
0400KHz
1.2us
t
sck
buf
thd;sta
stopstart
Hold time for a START thd;s
LOW period of SCK t
HIGH period of SCK t
Setup time for START tsu;s
Data hold time thd;d
Data setup time tsu;d
Rise time of both SDA and SCK t
Fall time of both SDA and SCK t
Setup time for STOP tsu;s
Capacitive load of each bus lines(SDA,SCK)C
ta
low
high
ta
at
at
r
f
to
b
1.0us
1.2us
1.0us
1.2us
1.3us
250ns
250ns
300ns
1.2us
pf
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 8 1999 Hyundai System IC Division
Electronics Industries Co., Ltd.
CMOS IMAGE SENSOR
With 8-bit ADC
System IC Division
PIN DESCRIPTION (48 Pin CLCC)
HV7121B
PINNAMEI/O
1SCKI I2C Clock ; I2C clock control from IIC master
2DGNDI Digital Ground
3ENBI Sensor Enable Signal ; 'H' enable normal operation
'L' disable sensor by stalling internal clock
4DGNDI Digital Ground
5MCLKI Master Clock (up to 15MHz)
; Global master clock for image sensor internal timing control
6VDD5I I/O bias voltage for 5V tolerant *1)
7AVDDI Analog Supply Voltage 3.3V
8AGNDI Analog Ground
9 ~ 16N.C No Connection
17AGNDI Analog Ground
18AVDDI Analog Supply Voltage 3.3V
19, 20Reserved Reserved
21DGNDI Digital Ground
22DATA7O Image Data bit 7
23DATA6O Image Data bit 6
24DATA5O Image Data bit 5
25DATA4O Image Data bit 4
26DGNDI Digital Ground
27DATA3O Image Data bit 3
28DATA2O Image Data bit 2
29DATA1O Image Data bit 1
30DATA0O Image Data bit 0
31DVDDI Digital Supply Voltage 3.3V
32DGNDI Digital Ground
33 ~ 41N.C No Connection
42DVDDI Digital Supply Voltage 3.3V
43RESETI Hardware Reset Signal, Active Low
44VSYNCO Vertical synchronization signal / Frame start output
; Signal pulse at start of image data frame with programmable
blanking duration
45HSYNCO Horizontal synchronization signal / Data valid output
/DVALID ; Data valid when 'H' with programmable blanking duration
46DGNDI Digital Ground
47SDAI/O I2C Data ; I2C standard data I/O port
48DGNDI Digital Ground
DESCRIPTION
*1) Tie to DVDD for 3.3V operation / Tie to 5V for 5V tolerant operation
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 9 1999 Hyundai System IC Division
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