HEI HL15703 Datasheet
H L 1 5 7 0 3
LCD Driver IC
HL15703
Preliminary
2Q. 1999
Hyundai Electronics Industries
System IC Division
1
P r e l i m i n a r y
Contents
1. General Description
2. Features
3. Block Diagram
4. Pin Diagram
5. Pin Description
6. Serial I/O Data Format
7. Registers
HL15703
8. Key Scan Function
9. LCD Function
10. Power On Reset
11. Power Down Mode
12. Oscillator Port
13. Electrical Characteristics
14. Application
2
P r e l i m i n a r y
HL15703
1. General Description
The HL15703 is 1/3 duty LCD display driver. It can drive directly maximum
171 segments. Also it has four general purpose output ports and a key scan
function that accepts input from up to 30 keys.
2. Features
• LCD display ..................................... 57 segments x 3 commons
1/3 duty - 1/2 bias
1/3 duty - 1/3 bias
• Key scan ............................................ Maximum 30 keys
Input 5 pins, Output 6 pins
• Power down mode ............................. Sleep mode and all segments off mode
• Port
Output .................................................. 4 pins
( Including the LCD segment port )
• Serial I/O .............................................. Data transfer and receive
• Power on reset ..................................... Supply voltage detection ( SVD )
• RC oscillator
• Package ............................................... 80QFP
Package Dimensions
80QFP
1.0
64
65
14.0
17.2
1.0
80
1.5
3.0 max
23.2
0.5
0.35
41
40
25
1 24
20.0
21.6
0.15
2.70
15.5
0.5
0.1
Unit : mm
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P r e l i m i n a r y
80QFP
14.0
12.0
61
1.25
0.5
1.25
60
1.25
0.20
14.0
12.0
0.5
1.25
41
HL15703
0.135
40
3. Block Diagram
VCL1
VCL2
VDD
VSS
RES
OSC
80
1
max
1.6
COM3
COM2
COM1
COMMOM
DRIVER
LCD
BIAS
SVD
CLOCK
GENERATOR
RESET
CLOCK
21
20
1.4
0.50.5
KS2 / SEG57
KS1 / SEG56
SEG55
SEGMENT
DRIVER
LCD
DISPLAY & CONTROL
REGISTER
SERIAL
I/O
0.1
Unit : mm
SEG5
SEG4 / P4
SEG1 / P1
SI
SO
SCK
CE
TEST
TEST
CONTROL
4
KS5
KS4
KS3
KS2
KEY
SCAN
KS1
KIN6
KIN5
KIN4
KIN3
KIN2
KIN1
P r e l i m i n a r y
4. Pin Diagram
KS6
KS5
KS4
KS3
KS2 / S57
KS1 / S56
COM3
COM2
COM1
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
HL15703
S41
KI1
KI2
KI3
KI4
KI5
VDD
VDD1
VDD2
VSS
TEST
OSC
RES
DD
CE
CL
DI
KS3
KS4
KS5
KS6
KI1
KI2
KI3
KI4
KI5
VDD
VDD1
VDD2
VSS
TEST
OSC
RES
DD
CE
CL
DI
80
65
70
64
1
P1 / S1
P2 / S2
P3 / S3
KS2 / S57
61
70
80
1
60
S5S6S7S8S9
P4 / S4
KS1 / S56
COM3
COM2
COM1
50
10 20
S10
S11
S12
S13
S14
S15
S16
S17
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
5060
10 20
S18
S45
S19
S44
S20
S43
41
S21
S42
40
30
21
S22
S41
41
40
30
25
24
S23
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
P1 / S1
P2 / S2
P3 / S3
S5S6S7S8S9
P4 / S4
S10
5
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
P r e l i m i n a r y
5. Pin Description
HL15703
PIN Name I/O
SEG[55:1] O
COM [3:1] O 3 LCD Common Pins
VCL[2:1] I 2 LCD Bias Pins
OSC I/O 1 Oscillator Input Pin
KS[6:1] O 6 Key Scan Output Pins
KIN[5:1] I 5 Key Scan Input Pins
CE I 1 Serial I/O Control Pin
SCK I 1 Serial I/O Clock Pin
SO O 1 Serial I/O Data Output Pin
SI I 1 Serial I/O Data Input Pin
TEST I 1 Test Pin. “1” Test mode , “0” Normal Mode
P[4:1] O 4 Output Port share SEG[4:1]
RES I 1 Reset Pin
VDD I
VSS
I
Pin Number
55
1
1 Ground Pin
LCD SEG Pins share P1,P2,P3 and P4
Power Supply Pin
Contents
6
P r e l i m i n a r y
6. Serial I/O Data Format
1) Writing Mode
i )SCK is stopped at the low level
CE
SCK
HL15703
SI
SO
CE
SCK
SI
SO
B0 B1 B2 B3 A0 A1 A2 A3
B0 B1 B2 B3 A0 A1 A2 A3
0 1 0 0 0 0 1 0 D1 D2 D3XX
Display data
D56
D57 0 0 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 0
0
Control data DD
D113
0 1 0 0 0 0 1 0 D58 D59 D60XX
Display data
D114
0 0 0 0 0 1
0 0 0 0 0 0
Fixed data DD
0 0 0
CE
SCK
SI
SO
XX
B0 B1 B2 B3 A0 A1 A2 A3
0 1 0 0 0 0 1 0 D115
D116 D117
Display data
D170
D171
0 0 0 0 1 0
0 0 0 0 0 0
Fixed data DD
7
0 0 0
P r e l i m i n a r y
ii )SCK is stopped at the high level
CE
SCK
HL15703
SI
SO
CE
SCK
SI
SO
CE
SCK
SI
SO
B0 B1 B2 B3 A0 A1 A2 A3
B0 B1 B2 B3 A0 A1 A2 A3
XX
B0 B1 B2 B3 A0 A1 A2 A3
1 0 0 0 0 1 0 0 D2 D3XX
1 0 0 0 0 1 0 0 D59 D60XX
1 0 0 0 0 1 0 0
D1
D58
D115
Display data
Display data
D116 D117
Display data
D56
D57 0 0 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 0
Control data DD
D113
D114
0 0 0 0 0
0 0 0 0
Fixed data DD
D170
D171
0 0 0 0 1
0 0 0 0
Fixed data DD
0 0 0 0
0 0 0 0
1
0
CCB address : 42H
D171~D1 : Display data
S0, S1 : Sleep control data
K0, K1 : Key scan output / Segment output selection data
P0, P1 : Segment output / general-purpose output port selection data
SC : Segment on / off control data
DR : 1/2 bias or 1/3 bias drive selection data
8
P r e l i m i n a r y
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