HEI GMS97L58, GMS97L56, GMS97C58, GMS97C56H, GMS97C56 Datasheet
...
DEC. 1998
Ver. 3.0
8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS90 Series
DATA SHEET
Version 3.0
Published by
MCU Application Team
1998 LG Semicon Co., Ltd. All right reserved.
Additional information of this manual may be served by LG Semicon offices in Korea or Distributo rs and Representatives listed at address directory.
LG Semicon reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct a nd reliable; however, LG Sem icon Co.,
Ltd. is in no way responsible for any viol ations of patents or oth er right s of the third party gene rated by the use
of this manual.
GMS90 Series
Device Naming Structure
GMS90X5X
LG Semicon MCU
Mask ROM version
GMS97X5X
- GBXXX XX XX
XXX
Frequency
Blank:
24:
40:
Package Type
Blank:
PL:
Q:
ROM Code serial No.
ROM size
1:
2:
4:
6:8:24k bytes
Operating Voltage
C:L:4.25~5.5V
12MHz
24MHz
40MHz
40PDIP
44PLCC
44MQFP
4k bytes
8k bytes
16k bytes
32k bytes
2.7~3.6V
OTP version
LG Semicon MCU
Dec. 1998 Ver 3.0
Package Type
Blank:
PL:
Q:
Frequency
Blank:H:12/24(5V),12MHz(3V)
ROM size
1:
2:
4:
6:8:24k bytes
Operating Voltage
C:L:4.25~5.5V
40PDIP
44PLCC
44MQFP
33MHz
4k bytes
8k bytes
16k bytes
32k bytes
2.7~3.6V
GMS90 Series
GMS90 Series Selection Guide
Operating
Voltage
(V)
4.25~5.5
2.7~3.6
ROM size
MASK OTP
4K
8K
16K
24K
32K
-
-
-
-
-
-
-
-
-
-
4K
8K
16K
24K
32K
(bytes)
ROM-less
-
-
-
-
4K
4K
8K
8K
16K
16K
24K
24K
32K
32K
ROM-less
-
-
-
-
-
RAM size
(bytes)
128
256
128
256
256
256
256
128
128
256
256
256
256
256
256
256
256
128
256
128
256
256
256
256
Device Name
GMS90C31
GMS90C32
GMS90C51
GMS90C52
GMS90C54
GMS90C56
GMS90C58
GMS97C51
GMS97C51H
GMS97C52
GMS97C52H
GMS97C54
GMS97C54H
GMS97C56
GMS97C56H
GMS97C58
GMS97C58H
GMS90L31
GMS90L32
GMS90L51
GMS90L52
GMS90L54
GMS90L56
GMS90L58
Operating
Frequency
12/24/40
12/24/40
12/24/40
12/24/40
12/24/40
12/24/40
12/24/40
12/24
33
12/24
33
12/24
33
12/24
33
12/24
33
12/16
12/16
12/16
12/16
12/16
12/16
12/16
(MHz)
-
-
-
-
-
4K
8K
16K
24K
32K
128
256
256
256
256
GMS97L51
GMS97L52
GMS97L54
GMS97L56
GMS97L58
12
12
12
12
12
Note: The ROM version products in this data book will be applied to new masking version. (From Dec., 1998)
In case that you have old p roducts, please refer to previ ous data book (prior to this).
Dec. 1998 Ver 3.0
GMS90 Series
GMS90C31/51, 97C51
GMS90L31/51, 97L51 (Low voltage versions)
• Fully compatible to standard MCS-51 microcontroller
• Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
•4K × 8 (EP)ROM
• 128 × 8 RAM
• 64K external program memory space
• 64K external data memory space
• Four 8-bit ports
• Two 16-bit Timers / Counters
• USART
• Five interrupt sources, two priority levels
• Power saving Idle and power down mode
• Quick pulse programming algorithm (in the OTP devices)
• 2-level program memory lock (in the OTP devices)
• 2.7Volt low voltage version available
• P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
128 × 8
T 0
T 1
ROM / EPROM
RAM
CPU
4K × 8
8-BIT
USART
PORT 0
PORT 1
PORT 2
PORT 3
I/O
I/O
I/O
I/O
Dec. 1998 Ver 3.0 1
GMS90 Series
GMS90C32/52, 97C52
GMS90L32/52, 97L52 (Low voltage versions)
• Fully compatible to standard MCS-51 microcontroller
• Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
•8K × 8 (EP)ROM
• 256 × 8 RAM
• 64K external program memory space
• 64K external data memory space
• Four 8-bit ports
• Three 16-bit Timers / Counters (Timer2 with up/down counter feature)
• USART
• Six interrupt sources, two priority levels
• Power saving Idle and power down mode
• Quick pulse programming algorithm (in the OTP devices)
• 2-level program memory lock (in the OTP devices)
• 2.7Volt low voltage version available
• P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
T 2
T 0
T 1
ROM / EPROM
RAM
256 × 8
CPU
8K × 8
8-BIT
USART
PORT 0
PORT 1
PORT 2
PORT 3
I/O
I/O
I/O
I/O
2 Dec. 1998 Ver 3.0
GMS90 Series
GMS90C54/56/58, 97C54/56/58
GMS90L54/56/58, 97L54/56/58 (Low voltage versions)
• Fully compatible to standard MCS-51 microcontroller
• Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
• 16K/24K/32K bytes (EP)ROM
• 256 × 8 RAM
• 64K external program memory space
• 64K external data memory space
• Four 8-bit ports
• Three 16-bit Timers / Counters (Timer2 with up/down counter feature)
• USART
• One clock output port
• Programmable ALE pin enable / disable
• Six interrupt sources, two priority levels
• Power saving Idle and power down mode
• Quick pulse programming algorithm (in the OTP devices)
• 2-level program memory lock (in the OTP devices)
• 2.7Volt low voltage version available
• P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
T 2
RAM
256 × 8
T 0
CPU
T 1
ROM / EPROM
GMS9XX54: 16K × 8
GMS9XX56: 24K × 8
GMS9XX58: 32K × 8
8-BIT
USART
PORT 0
PORT 1
PORT 2
PORT 3
I/O
I/O
I/O
I/O
Dec. 1998 Ver 3.0 3
PIN CONFIGURATION
44-PLCC Pin Configuration (top view)
GMS90 Series
N.C.: Do not connect.
INDEX
CORNER
RESET
RxD / P3.0
N.C.*
TxD / P3.1
/ P3.2
INT0
/ P3.3
INT1
T0 / P3.4
T1 / P3.5
P1.5
P1.6
P1.7
P1.4
P1.3
P1.2
P1.1 / T2EX
65432
7
8
9
10
11
12
13
14
15
16
17
1819202122232425262728
/ P3.7
XTAL2
XTAL1
RD
WR / P3.6
P1.0 / T2
N.C.*
1
SS
V
N.C.*
CC
V
4443424140
P2.0 / A8
P0.0 / AD0
P2.1 / A9
P0.1 / AD1
P0.2 / AD2
P0.3 / AD3
P0.4 / AD4
39
P0.5 / AD5
38
P0.6 / AD6
37
P0.7 / AD7
36
/ V
EA
35
34
33
32
31
30
29
P2.2 / A10
P2.4 / A12
P2.3 / A11
PP
N.C.*
ALE / PROG
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
4 Dec. 1998 Ver 3.0
GMS90 Series
40-PDIP Pin Configuration (top view)
T2 / P1.0
T2EX / P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RESET
RxD / P3.0
TxD / P3.1
/ P3.2
INT0
/ P3.3
INT1
T0 / P3.4
T1 / P3.5
/ P3.6
WR
/ P3.7
RD
XTAL2
XTAL1
V
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SS
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CC
P0.0 / AD0
P0.1 / AD1
P0.2 / AD2
P0.3 / AD3
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
/ V
EA
PP
ALE / PROG
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
Dec. 1998 Ver 3.0 5
44-MQFP Pin Configuration (top view)
P1.4
4443424140393837363534
P1.5
P1.6
P1.7
RESET
RxD / P3.0
N.C.*
TxD / P3.1
/ P3.2
INT0
/ P3.3
INT1
T0 / P3.4
T1 / P3.5
1
2
3
4
5
6
7
8
9
10
11
1213141516171819202122
GMS90 Series
CC
P0.0 / AD0
P0.1 / AD1
P0.2 / AD2
P1.3
P1.2
P1.1 / T2EX
P1.0 / T2
N.C.*
V
P0.3 / AD3
33
32
31
30
29
28
27
26
25
24
23
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
/ V
EA
PP
N.C.*
ALE / PROG
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
N.C.: Do not connect.
SS
V
/ P3.7
XTAL2
RD
WR / P3.6
N.C.*
XTAL1
P2.0 / A8
P2.1 / A9
P2.2 / A10
P2.4 / A12
P2.3 / A11
6 Dec. 1998 Ver 3.0
GMS90 Series
Logic Symbol
V
CCVSS
XTAL1
XTAL2
RESET
EA/V
PP
ALE/PROG
PSEN
Port 0
8-bit Digital I/O
Port 1
8-bit Digital I/O
Port 2
8-bit Digital I/O
Port 3
8-bit Digital I/O
Dec. 1998 Ver 3.0 7
PIN DEFINITIONS AND FUNCTIONS
GMS90 Series
Symbol
P1.0-P1.7 2-9
P3.0-P3.7 11,
PLCC-44PDIP-40MQFP-
2
3
2
13-19
Pin Number
44
1-8
1
2
1
10-17 5, 7-13 I/O
40-44,
1-3
40
41
40
Input/
Output
I/O
Function
Port1
Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 1 pins that have 1s written to them are
pulled high by the interna l pul l- up re si stor s a nd ca n b e
used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of
the pulls-ups (IIL, in the DC characteristics). Pins P1.0
and P1.1 also. Port1 also receives the low-order
address byte during program memory verification.
Port1 also serves alternate functions of Timer 2.
P1.0 / T2 : Timer/counter 2 external count input
P1.1 / T2EX : Timer/counter 2 trigger input
In GMS9XC54/56/58:
P1.0 / T2, Clock Out : Timer/counter 2 external count
input, Clock Out
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 3 pins that have 1s written to them are
pulled high by the interna l pul l- up re si stor s a nd ca n b e
used as inputs. As inputs, port 3 pins that are
externally pulled low will source current because of
the pulls-ups (IIL, in the DC characteristics). Port 3 also
serves the special features of the 80C51 family, as
listed below.
11
13
14
15
16
17
18
19
XTAL2 20 18 14 O
10
11
12
13
14
15
16
17
10
11
12
13
5
7
8
9
P3.0 / RxD
P3.1 / TxD
P3.2 /INT0
P 3 .3 / INT 1
P3.4 /T0
P3.5 /T1
P3.6 / WR
P3.7 /RD
XTAL2
Output of the inverting oscillator amplifier.
receiver data input (asynchronous) or
data input output(synch rono us) of serial
interface 0
transmitter data output (asynchronous)
or clock output (synchronous) of the
serial interface 0
interrupt 0 input/timer 0 gate control
interrupt 1 input/timer 1 gate control
counter 0 input
counter 1 input
the write control signal latches the data
byte from port 0 into the external data
memory
the read control signal enables the
external data memory to port 0
8 Dec. 1998 Ver 3.0
GMS90 Series
Pin Number
Symbol
XTAL1 21 19 15 I
P2.0-P2.7 24-31 21-28 18-25 I/O
PSEN 32 29 26 O
RESET 10 9 4 I
PLCC-44PDIP-40MQFP-
44
Input/
Output
Function
XTAL1
Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.To drive the
device from an external clock source, XTAL1 should
be driven, while XTA L2 is le ft un con nec ted . There are
no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking
circuitry is divided down by a divide-by-two flip-flop.
Minimum and maximum high an d low times as well as
rise fall times specified in the AC characteristics must
be observed.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 2 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 2 pins that are
externally pulled low will source current because of
the pulls-ups (IIL, in the DC characteristics).Port 2
emits the high-order addr ess by te d uring fetch es fro m
external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pull-ups when emitting 1s. During accesses to
external data memory that use 8-bit addresses
(MOVX @Ri), port 2 emits the contents of the P2
special function register.
The Program Store Enable
The read strobe to external program memory when
the device is executing code from the external
program memory. PSEN is activated twice each
machine cycle, except that two PSEN activations are
skipped during each access to external data memory.
PSEN is not activated during fetches from internal
program memory.
RESET
A high level on this pin for two machine cycles while
the oscillator is running resets the device. An inter nal
diffused resistor to VSS permits power-on reset us ing
only an external capaci tor to VCC.
Dec. 1998 Ver 3.0 9
GMS90 Series
Symbol
ALE /
PROG
EA / V
Pin Number
PLCC-44PDIP-40MQFP-
33 30 27 O
PP
35 31 29 I External Access Enable / Program Supply Voltage
44
Input/
Output
Function
The Address Latch Enable / Program pulse
Output pulse for latching the low byte of the address
during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external
timing or clocking. Note that one ALE pulse is skipped
during each access to external data memor y. This pin
is also the program pulse input (PROG) during
EPROM programming.
In GMS9XC54/56/58:
If desired, ALE operation can be disabled by setting
bit 0 of SFR locat ion 8EH. With this bit set, the pin is
weakly pulled high. The ALE disable feature will be
terminated by reset. Setting the ALE-disable bit has
no affect if the microcont roller is in ex ternal execut ion
mode.
EA must be external held low to enable the device to
fetch code from external program memory locations
0000H to FFFFH. If EA is held high, the device
executes from internal program memory unless the
program counter contai ns an address greater than its
internal memory size. This pin also receives the
12.75V programming supply voltage (VPP) during
EPROM programming.
Note; however, that if any of the Lock bits are
programmed, EA will be internally
latched on reset.
P0.0-P0.7 36-43 32-39 30-37 I/O
Port 0
Port 0 is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1s wri tten to them f loat and can
be used as high-impedan ce inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and
data memory. In this application it uses strong internal
pull-ups when emitting 1s. Port 0 also outputs the
code bytes during program verification in the
GMS97X5X. External pull-up resistors are required
during program verification.
V
SS
V
CC
N.C. 1,12
22 20 16 44 40 38 -
-6,17
23,34
28,39
Circuit ground potential
Supply terminal
-
No connection
for all operating modes
10 Dec. 1998 Ver 3.0
GMS90 Series
FUNCTIONAL DESCRIPTION
The GMS90 series is fully compatible to the standard 8051 microcontroller family.
It is compatible with the general 8051 family. While maintaining all architectural and operational characteristics
of the general 8051 family.
Figure 1 shows a block diagram of the GMS90 series
XTAL1
XTAL2
RESET
/V
EA
ALE/PROG
PSEN
PP
OSC & TIMING
CPU
Timer 0
Timer 1
Timer 2
Interrupt Unit
Serial Channel
Figure 1. Block Diagram of the GMS90 series
RAM
128/256×8
ROM/EPROM
4K/8K/16K
24K/32K
Port 0
Port 1
Port 2
Port 3
Port 0
8-bit Digit. I/O
Port 1
8-bit Digit. I/O
Port 2
8-bit Digit. I/O
Port 3
8-bit Digit. I/O
Dec. 1998 Ver 3.0 11
GMS90 Series
CPU
The GMS90 series is efficient both as a controller and as an arithmetic processor. It has extensive facilities for
binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results
from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12
MHz crystal, 58% of the instructions are executed in 1.0µs (40MHz: 300ns).
Special Function Register PSW
LSB
PSW
Bit No.
Addr. D0
MSB
76543210
H
CY AC F0 RS1 RS0 OV F1 P
Bit Function
Carry Flag
Auxiliary Carry Flag
(for BCD operations)
General Purpose Flag
Register Bank select control bits
Bank 0 selected, data address 00H - 07
Bank 1 selected, data address 08H - 0F
Bank 2 selected, data address 10H - 17
Bank 3 selected, data address 18H - 1F
H
H
H
H
Overflow Flag
General Purpose Flag
Parity Flag
Set/cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the accumulator, i.e. ev en parity.
RS1
0
0
1
1
CY
AC
F0
RS0
0
1
0
1
OV
F1
P
Reset value of PSW is 00H.
12 Dec. 1998 Ver 3.0
GMS90 Series
SPECIAL FUNCTION REGISTERS
All registers, except the progra m coun ter and th e four ge neral purp ose regi ster bank s, resi de in the s pecial fun ction register area.
The 28 special function registers (SFR) include pointers and registers that provide an interface between the CPU
and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area.
All SFRs are listed in Table 1, Table 1, and Table 3.
In Table 1 they are organized in nume ric order of their addr esses. In Tabl e 2 they are organ ized in groups wh ich
refer to the functional blocks of the GMS90 series. Table 3 illustrates the contents of the SFRs.
Table 1. Special Function Registers in Numeric Order of their Addresses
Address Register
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
3)
8EH
8FH
1) Bit-addressable Special Function Regis ter.
2) X means that the value is indeterminate and the location is reserved.
3) The GMS9XX54/56/58 have the AUXR0 reg iste r at ad dr ess 8EH.
1)
P0
SP
DPL
DPH
reserved
reserved
reserved
PCON
1)
TCON
TMOD
TL0
TL1
TH0
TH1
3)
☞
reserved
Contents after
Reset
FFH
07H
00H
00H
2)
XXH
2)
XXH
2)
XXH
0XX0000
2)
B
00H
00H
00H
00H
00H
00H
3)
☞
2)
XXH
Address Register
90H
91H
92H
93H
94H
95H
96H
97H
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
GMS9XX51/52 GMS9XX54/56/58
8E
H
reserved XXXXXXX0
XXXXXXXX
2)
B
8E
H
1)
P1
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SCON
SBUF
reserved
reserved
reserved
reserved
reserved
reserved
AUXR0
1)
Contents after
Reset
FF
00
XXH
XXH
XXH
XXH
XXH
XXH
00H
XXH
XXH
XXH
XXH
XXH
XXH
XXH
H
H
2)
2)
2)
2)
2)
2)
2)
2)
2)
2)
2)
2)
2)
2)
B
Dec. 1998 Ver 3.0 13
GMS90 Series
Table 1. Special Function Registers in Numeric Order of their Addresses
Address Register
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
1)
P2
reserved
reserved
reserved
reserved
reserved
reserved
reserved
1)
IE
reserved
reserved
reserved
reserved
reserved
reserved
reserved
1)
P3
reserved
reserved
reserved
reserved
reserved
reserved
reserved
1)
IP
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Contents after
Reset
FFH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
0X000000B
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
FFH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
XX000000B
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
XX
H
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
2)
Address Register
C8H
3)
C9H
CAH
CBH
CCH
CDH
CEH
CFH
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
(cont’d)
T2CON
T2MOD
RC2L
RC2H
TL2
TH2
reserved
reserved
PSW
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ACC
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
1)
1)
1)
Contents after
Reset
00H
3)
☞
00H
00H
00H
00H
2)
XXH
2)
XXH
00H
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
00H
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
14 Dec. 1998 Ver 3.0
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