Semiconductor Group of Hyundai Electronics Industrial Co., Ltd.
MicroElectronics
Version 1.04
Published by
MCU Application Team
1999 HYUNDAI Micro Electronics All right reserved.
Additional information of this manual may be served by HYUNDAI Micro Electronics offices in Korea or Distributors and
Representatives listed at address directory.
HYUNDAI Micro Electronics reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are co rrect and reliable; ho wever, HYUNDAI Micro Electronics is
in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
Instruction Set ....................................................x
D. MASK ORDER SHEET......................xvi
DEC. 1999 Ver 1.04
HYUNDAI MicroElectronicsGMS81508B/16B/24B
GMS81508B/16B/24B
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH A/D CONVERTER
1. OVERVIEW
1.1 Description
The GMS81508B/16B/24B are advanced CMOS 8-bi t microcon trollers with 8K/16K/24K byt es of ROM. The device is on e
of GMS800 family. This device using the GMS800 family CPU includes several peripheral functions such as Timer, A/D
converter, Programmable buzzer driver, Serial I/O communication, Pulse Width Mod ulation function, etc. The RAM, ROM,
and I/O are placed on the same memory map in addition to simple instruction set.
The GMS815xxB is functi onall y 10 0% com pati ble wit h earie r GMS81508/16 or GMS81508A/16A, h owever bet t er characteristics have such as strong EMS, wide operating voltage, temperature, frequency and fast programming time for the OTP.
• 448 Bytes of On-chip Data RAM
(Included stack memory)
• Minimum Instruction Execution Time
0.5
s at 8MHz
µµµµ
• One 8-bit Basic Interval Timer
• Four 8-bit Timer/Event counter
or Two 16-bit Timer/Event counter
• One 6-bit Watchdog timer
• Eight channel 8-bit A/D converter
• Two channel 8-bit PWM
• One 8-bit Serial Communication Interface
• Four External Interrupt input ports
• Buzzer Driving port
- 500Hz ~ 250kHz@8MHz
• 52 I/O Ports, 4 Input Ports
• Twelve Interrupt sources
- Basic Interval Timer: 1
- External input: 4
- Timer/Event counter: 4
- ADC: 1
- Serial Interface: 1
- WDT: 1
• Built in Noise Immunity Circuit
- Noise filter
- Power fail processor
• Power Down Mode
- STOP mode
• 2.2V to 5.5V Wide Operating Range
• 1~10MHz Wide Operating Frequency
• 64SDIP, 64MQFP, 64LQFP package types
• Available 16K, 24K bytes OTP version
DEC. 1999 Ver 1.041
GMS81508B/16B/24BHYUNDAI MicroElectronics
1.3 Development Tools
The GMS815xxB are supported by a full-featured macro
assembler, an in-circuit emulator CHOICE-Jr.
TM
and OTP
programmers. There are third different type programmers
such as emulator add-on board type, single type, gang
type. For mode detail, Refer to “22. OTP PROGRAMMING” on page 73. Macro assembler operates under the
MS-Windows 95/98
TM
.
Please contact sales part of Hyundai MicroElectronics.
1.4 Ordering Information
Device nameROM SizeRAM sizePackage
Mask version
OTP version
GMS81508B K
GMS81508B Q
GMS81508B LQ
GMS81516B K
GMS81516B Q
GMS81516B LQ
GMS81524B K
GMS81524B Q
GMS81524B LQ
GMS81516BT K
GMS81516BT Q
GMS81516BT LQ
GMS81524BT K
GMS81524BT Q
GMS81524BT LQ
Supply voltage.............................................-0.3 to +7.0 V
Storage Temperature ..................................-40 to +125 °C
Voltage on any pin with respect to Ground (V
................................ ..................................-0.3 to V
Maximum current out of V
Maximum current into V
Maximum current sunk by (I
Maximum output current sourced by (I
pin..........................150 mA
SS
pin ..............................80 mA
DD
per I/O Pin) ..........20 mA
OL
OH
)
SS
DD
per I/O Pin)
+0.3
...................................................................................8 mA
7.2 Recommended Operating Conditions
ParameterSymbolCondition
f
=1 ~ 10 MHz
XIN
f
Supply Voltage
Operating Frequency
V
f
DD
XIN
=1 ~ 8 MHz
XIN
f
=1 ~ 4 MHz
XIN
VDD=4.5~5.5V
VDD=2.7~5.5V
VDD=2.2~5.5V
Maximum current (ΣI
Maximum current (ΣI
)......................................100 mA
OL
)........................................50 mA
OH
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause per manent damage to the d evice. This is a stress ra ting only and functional ope r ati on of
the device at any oth er c ond iti ons ab ov e tho se ind ic ated in
the oper ati o na l se c ti ons of this s pecificatio n i s no t i mp l ie d .
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Specifications
Unit
Min.Max.
4.5
2.7
2.2
1
1
1
5.5
5.5
5.5
10
8
4
V
MHz
Operating Temperature
T
OPR
7.3 A/D Converter Characteristics
(TA=25°C, VSS=0V, VDD=5.12V@f
ParameterSymbol
Analog Input Voltage Range
Non-linearity Error
Differential Non-linearity Error
Zero Offset Error
Full Scale Error
Gain Error
Overall Accuracy
AV
Input CurrentI
DD
Conversion Time
=8MHz, VDD=3.072V@f
XIN
Normal Version
Temperature Extention Version
=4MHz)
XIN
Min.
V
N
N
N
N
N
N
T
CONV
AIN
NLE
DNLE
ZOE
FSE
GE
ACC
REF
V
SS
-
-
-
-
-
-
-0.51.01.0 mA
--4020
-20
-40
85
85
Specifications
1
Typ.
f
XIN
-
1.0±1.5±1.5LSB
±
1.0±1.5±1.5LSB
±
0.5±1.5±1.5LSB
±
0.35±0.5±0.5LSB
±
1.0±1.5±1.5LSB
±
1.0±1.5±1.5LSB
±
Max.
=4MHzf
AV
DD
XIN
AV
=8MHz
DD
C
°
Unit
V
s
µ
12DEC. 1999 Ver 1.04
HYUNDAI MicroElectronicsGMS81508B/16B/24B
Specifications
ParameterSymbol
Min.
Analog Power Supply Input Range
1. Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
AV
DD
0.9V
DD
Typ.
V
DD
1
f
XIN
Max.
=4MHzf
1.1V
XIN
DD
Unit
=8MHz
V
7.4 DC Electrical Characteristics
(TA=-20~85°C, VDD=2.7~5.5V, Ta= -20~85°C, f
=8MHz, VSS=0V)
XIN
ParameterSymbolCondition
, RESET,
X
IN
R4, R5, R6
R0, R1, R2, R3
, RESET,
X
IN
R4, R5, R6
R0, R1, R2, R3-
R0,R1,R2,R3,R4,R5
R6
R0,R1,R2,R3,R4,R5
R6
@ T
=25°C0.9V
A
All input pins-5.0-5.0
All input pins-5.0-5.0
RESET, EC0, EC2,
SIN, SCLK, INT0~INT3
SS
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Power Fail Detect
Voltage
Input High
Leakage Current
Input Low
Leakage Current
Hysteresis
V
IH1
V
IH2
V
IL1
V
IL2
V
OH
V
OL
V
PFD
I
IH1
I
IL
, V
V
T+
T-
I
DD1fXIN
VDD=4.5
VDD=2.7
VDD=4.5
V
=2.7
DD
VDD=4.5
VDD=2.7
I
=-2mA
OH1
VDD=4.5
VDD=2.7
I
=5mA
OL1
V
=3.0V
PFD
V
=2.4V
PFD
VIN=V
DD
VIN=V
SS
= 8 MHzA ll inp ut = V
C ry s ta l Oscilla tor ,
Power Current
1. Data in “Typ.” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Serial Input Clock Pulse
Serial Input Clock Pulse Width
Serial Input Clock Pulse Transition
Time
SIN Input Pulse Transition Time
SIN Input Setup Time (External SCLK)
SIN Input Setup Time (Internal SCLK)
SIN Input Hold Time
Serial Output Clock Cycle Time
Serial Output Clock Pulse Width
Serial Output Clock Pulse Transition
Time
Serial Output Delay Time
XIN
t
SCYC
t
SCKW
t
FSCK
t
RSCK
t
FSIN
t
RSIN
t
SUS
t
SUS
t
HS
t
SCYC
t
SCKW
t
FSCK
t
RSCK
s
OUT
=8MHz)
Specifications
Unit
Min.Typ.Max.
SCLK
SCLK
2t
SYS
+70
t
SYS
-8ns
-8ns
+200
SCLK--30ns
SIN--30n s
SIN100--ns
SIN200-ns
SIN
SCLK
SCLK
t
SYS
t
SYS
4t
SYS
-30
-ns
-
16t
SYS
ns
ns
+70
SCLK30ns
SOUT100ns
SCLK
SIN
SOUT
t
0.8V
0.2V
FSCK
t
SCYC
t
RSCK
SUS
DD
DD
t
SCKW
t
t
FSIN
t
DS
0.8V
DD
0.2V
DD
Figure 7-2 Serial I/O Timing Chart
t
SCKW
t
HS
0.8V
DD
0.2V
DD
t
RSIN
DEC. 1999 Ver 1.0415
GMS81508B/16B/24BHYUNDAI MicroElectronics
7.7 Typical Characteristic Curves
This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified
VDD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.
I
OH
(mA)
-12
-9
-6
-3
I
OH
VDD=4.5V
Ta=25°C
0
V
−
OH
0.30.6
R0~R6 pins
0.9 1.2
1.5
VDD-V
(V)
OH
I
OH
(mA)
-12
-9
-6
-3
I
0
V
−
OH
VDD=3.0V
Ta=25°C
0.3 0.6
OH
The data presented in this s ection is a statistical s ummary
of data collected on units from different lots over a period
of time. “Typical” represents the mean of the distribution
while “max” or “min” represents (mean + 3σ) and (mean
3σ) respectively where σ is standard deviation
R0~R6 pins
(V)
0.9 1.2
1.5
VDD-V
OH
−
V
I
OL
(mA)
20
15
10
IH1
(V)
0
I
5
0
V
4
3
2
1
V
−
OL
VDD=4.5V
Ta=25°C
0.2 0.4
V
−
DD
f
=8MHz
XIN
Ta=25°C
23
OL1
IH1
R0~R6 pins
0.6 0.8
XIN, RESET,
R4, R5, R6 pins
45
1.0
I
V
−
OL
VDD=3.0V
Ta=25°C
0.2 0.4
V
DD
f
=8MHz
XIN
Ta=25°C
1
OL2
V
−
IH2
23
I
OL
(mA)
20
15
10
5
V
OL
(V)
V
DD
(V)
6
0
V
IH2
(V)
4
3
2
1
0
R0~R6 pins
0.6 0.8
R0, R1, R2, R3 pins
45
1.0
6
V
V
(V)
(V)
OL
DD
16DEC. 1999 Ver 1.04
HYUNDAI MicroElectronicsGMS81508B/16B/24B
V
IL2
(V)
I
DD
(mA)
4
3
2
1
0
20
15
10
5
0
V
DD
f
XIN
Ta=25°C
I
−
DD
Ta=25°C
f
V
−
IL1
=8MHz
23
V
DD
= 8MHz
XIN
23
XIN, RESET
R4, R5, R6 pins
45
Normal Operation
4MHz
45
,
V
DD
(V)
6
V
DD
(V)
6
V
I
DD
(µA)
IL2
(V)
0.4
0.3
0.2
0.1
4
3
2
1
0
0
V
DD
f
XIN
Ta=25°C
1
I
STOP
V
−
IL2
=8MHz
23
V
−
DD
23
R0, R1, R2, R3 pins
45
Stop Mode
45
6
6
V
DD
(V)
85°C
25°C
-20°C
V
DD
(V)
Operating Area
f
XIN
(MHz)
Ta= -20~85°C
10
8
6
4
2
0
23
45
V
DD
(V)
6
DEC. 1999 Ver 1.0417
GMS81508B/16B/24BHYUNDAI MicroElectronics
SP
01
H
Stack Address (100H ~ 1FEH)
Bit 15Bit 087
Hardware fixed
00H~FE
H
8. MEMORY ORGANIZATION
The GMS81508B/16B/24B has separate address spaces
for Program memory and Data Memory. Pro gram memory
can only be read, not written to. It can be up to 24K bytes
8.1 Registers
This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
A
X
Y
SP
PCH
Figure 8-1 Configuration of Registers
Accumulator:
PCL
PSW
The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc.
The Accumulator can be used as a 16-bit register with Y
Register as shown below.
Y
A
Two 8-bit Registers can be used as a “YA” 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers
: In the addressing mode which uses these
index registers, the register conten ts a re added to the specified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables . The index regi sters also h ave increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators.
Stack Pointer
: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).
Generally, SP is au to mat ic ally upda t ed wh e n a s ubr outin e
ACCUMULATOR
X REGISTER
Y REGISTER
STACK POINTER
PROGRAM COUNTER
PROGRAM STATUS
WORD
YA
of Program memory. Data memory can be read and written
to up to 448 bytes including the stack area.
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.
The stack can be located at any position within 100
1FF
of the internal data memory. The SP is not initialized
H
to
H
by hardware, requiring to write the initial v alue (the lo cation with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “F E
” is
H
used.
Note: The Stack Pointer must be initialized by software because its value is undefined after RESET.
Example: To initialize the SP
LDX#0FEH
TXSP; SP ← FEH
Address 01FFH can not be used as stack. Don not use
1FFH, or malfunction would be occurred.
Program Counter
: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset routine address (PC
Program Status Word
:0FFH, PCL:0FEH).
H
: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3. It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.
[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.
18DEC. 1999 Ver 1.04
HYUNDAI MicroElectronicsGMS81508B/16B/24B
[Zero flag Z]
This flag is set when the result of an arithmetic operat ion
MSBLSB
N
V G B H I Z C
NEGATIVE FLAG
OVERFLOW FLAG
when G=1, page is selected to “page 1”
SELECT DIRECT PAGE
BRK FLAG
PSW
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
or data transfer is “0” and is cleared by any other result.
RESET VALUE: 00
CARRY FLAG RECEIVES
CARRY OUT
ZERO FLAG
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
H
This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00
addressing area is assigned 100
to 0FFH when this flag is "0". If it is set to "1",
H
to 1FFH. It is set by
H
SETG instruction and cleared by CLRG.
[Overflow flag V]
[Half carry flag H]
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector address.
[Direct page flag G]
This flag is set to “1” when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction exceeds +127(7F
) or -128(80H). The CLRV instruction
H
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
DEC. 1999 Ver 1.0419
GMS81508B/16B/24BHYUNDAI MicroElectronics
At execution of
a CALL/TCALL/PCALL
01FE
01FD
01FC
01FB
SP before
execution
SP after
execution
PCH
PCL
01FE
01FC
Push
down
SP before
execution
SP after
execution
01FE
01FD
01FC
01FB
At execution
of PUSH instruction
PUSH A (X,Y,PSW)
01FE
01FD
01FC
01FB
A
01FE
01FD
At acceptance
of interrupt
PCH
PCL
PSW
01FE
01FB
Push
down
Push
down
01FE
01FD
01FC
01FB
At execution
of RET instruction
01FE
01FD
01FC
01FB
At execution
of POP instruction
POP A (X,Y,PSW)
PCH
PCL
01FC
01FE
A
01FD
01FE
Pop
up
Pop
up
At execution
of RET instruction
01FE
01FD
01FC
01FB
0100H
01FEH
PCH
PCL
PSW
01FB
01FE
Stack
depth
Pop
up
Figure 8-4 Stack Operation
20DEC. 1999 Ver 1.04
HYUNDAI MicroElectronicsGMS81508B/16B/24B
0FFE0H
E2
AddressVector Area Memory
E4
E6
E8
EA
EC
EE
F0
F2
F4
F6
F8
FA
FC
FE
-
-
Serial Communication Interface
Basic Interval Timer
-
-
-
External Interrupt 2
Timer/Counter 1 Interrupt
External Interrupt 0
-
RESET Vector Area
External Interrupt 1
Watchdog Timer Interrupt
“-” means reserved area.
NOTE:
Timer/Counter 2 Interrupt
External Interrupt 3
Timer/Counter 0 Interrupt
Timer/Counter 3 Interrupt
A/D Converter
8.2 Program Memory
A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 2 4K bytes program memory
space only physically implemented. Accessing a location
above FFFF
will cause a wrap-around to 0000H.
H
Figure 8-5, shows a map of Pr ogram Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFE
and FFFFH as shown in Figure 8-6.
H
As shown in Figure 8-5, each area is assigned a fix ed location in Program Memory. Program Memory area contains
the user program.
A000
H
C000
H
E000
H
FEFF
H
FF00
FFC0
FFDF
FFE0
FFFF
H
H
H
H
H
TCALL area
Interrupt
Vector Area
PCALL area
GMS81508B, 8K ROM
GMS815024B, 24K ROM
GMS815016B, 16K ROM
it is more useful to save program byte length.
Table Call (TC ALL) causes the CP U to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0
for TCALL15, 0FFC2H for
H
TCALL14, etc., as shown in Figure 8-7.
Example: Usage of TCALL
The interrupt causes the CPU to jum p to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to location 0FFFA
interval: 0FFF8
0FFFA
Any area from 0FF00
. The interrupt service locations spaces 2-byte
H
and 0FFF9H for External Interru pt 1,
and 0FFFBH for External Interrupt 0, etc.
H
H
to 0FFFFH, if it is not going to be
H
used, its service location is available as general purpose
Program Memory.
Figure 8-5 Program Memory Map
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called,
DEC. 1999 Ver 1.0421
Figure 8-6 Interrupt Vector Area
GMS81508B/16B/24BHYUNDAI MicroElectronics
11111111 11010110
01001010
PC:
FH FH DH 6H
4A
~
~
~
~
25
0FFD6
H
0FF00
H
0FFFF
H
D1
NEXT
0FFD7
H
➊
➋
➌
0D125
H
Reverse
Address
0FF00
0FFFF
PCALL Area Memory
H
PCALL Area
(256 Bytes)
H
AddressP ro gra m Mem o r y
0FFC0
H
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
;ORG0C000H; 16K ROM Start address
;ORG0E000H; 8K ROM Start address
;*******************************************
; MAIN PROGRAM *
;*******************************************
;
RESET:DI;Disable All Interrupts
RAM_CLR: LDA#0;RAM Clear(!0000H->!00BFH)
;
;
ORG0A000H; 24K ROM Start address
CLRG
LDX#0
STA{X}+
CMPX#0C0H
BNERAM_CLR
LDX#0FEH;Stack Pointer Initialize
TXSP
LDMR0, #0;Normal Port 0
LDMR0DD,#82H;Normal Port Direction
:
:
:
LDMTDR0,#250;8us x 250 = 2000us
LDMTM0,#1FH;Start Timer0, 8us at 8MHz
LDMIRQH,#0
LDMIRQL,#0
LDMIENH,#0C8H ;Enable Timer0, INT0, INT1
LDMIENL,#0
LDMIEDS,#55H;Select falling edge detect on INT pin
LDMPMR4,#3H;Set external interrupt pin(INT0, INT1)
EI;Enable master interrupt
:
:
:
:
NOT_USED:NOP
:
RETI
DEC. 1999 Ver 1.0423
GMS81508B/16B/24BHYUNDAI MicroElectronics
8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided in to four groups, a user RAM,
control registers, Stack, and LCD memory.
0000
H
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
More detailed informations of each register are explained
in each peripheral section.
User Memory
00BF
00C0
00FF
0100
01FF
H
H
H
H
H
Control
Registers
User Memory
or Stack Area
PAGE0
PAGE1
When “G-flag=0”,
this page is selected
When “G-flag=1”
Figure 8-8 Data Memory Map
User Memory
The GMS815xxB has 448 × 8 bits for th e user me mory
(RAM).
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0
to 0FFH.
H
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction, for example “LDM”.
Example; To write at CKCTLR
LDMCLCTLR,#09H
;Divide ratio(÷32)
Stack Area
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
When returning from the processing routine, execu ting the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; ex ecuting the interrupt
return instruction [RETI] restores the contents of the program counter and flags.
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-4 on page 20.
24DEC. 1999 Ver 1.04
HYUNDAI MicroElectronicsGMS81508B/16B/24B
AddressRegister NameSymbolR/W
Initial Value
76543210
Page
00C0R0 port data registerR0R/WUndefinedpage 31
00C1R0 port I/O direction reg isterR0DDW0 0 0 0 0 0 0 0page 31
00C2R1 port data registerR1R/WUndefinedpage 31
00C3R1 port I/O direction reg isterR1DDW0 0 0 0 0 0 0 0page 31
00C4R2 port data registerR2R/WUndefinedpage 31
00C5R2 port I/O direction reg isterR2DDW0 0 0 0 0 0 0 0page 31
00C6R3 port data registerR3R/WUndefinedpage 32
00C7R3 port I/O direction reg isterR3DDW0 0 0 0 0 0 0 0page 32
00C8R4 port data registerR4R/WUndefinedpage 32
00C9R4 port I/O direction reg isterR4DDW0 0 0 0 0 0 0 0page 32
00CAR5 port data registerR5R/WUndefinedpage 33
00CBR5 port I/O direction registerR5DDW0 0 0 0 0 0 0 0page 33
00CCR 6 port data registerR6R/WUndefinedpage 33
00CDR6 port I/O direction registerR6DDW0 0 0 0 - - - -page 33
Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation
instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.
Registers are controlled by both bit and byte manipulation instruction.
26DEC. 1999 Ver 1.04
HYUNDAI MicroElectronicsGMS81508B/16B/24B
8.4 Addressing Mode
The GMS800 series MCU uses six addressing modes;
• Register addressing
• Immediate addressing
• Direct page addressing
• Absolute addressing
• Indexed addressing
• Register-indirect addressing
(1) Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
(2) Immediate Addressing
→
→
→ →
#imm
In this mode, second byte (operand) is accessed as a data
immediate ly.
Example:
0435ADC#35H
MEMORY
Example: G=1
E45535LDM35H,#55H
0135H
➊
0F100H
0F101H
0F102H
(3) Direct Page Addressing
data
~
~
~
~
data ¨ 55H
➋
E4
55
35
dp
→
→
→ →
In this mode, a address is specified within direct page.
Example; G=0
C535LDA35H;A ←RAM[35H]
04
35
A+35H+C → A
When G-flag is 1, then RAM address is defined by 16-bit
address which is composed of 8-bit RAM paging register
(RPR) and 8-bit immediate data.
35H
0E550H
0E551H
data
➋
~
~
C5
35
~
~
data → A
➊
DEC. 1999 Ver 1.0427
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