HEI GMS34120, GMS34140, GMS34004, GMS34112, GMS34012 Datasheet

APR. 1997 Rev. 2.0

4-BIT SINGLE CHIP MICROCOMPUTERS

GMS340 SERIES

USER`S MANUAL

• GMS34004

• GMS34012

• GMS34112

• GMS34120

• GMS34140

• GMS30000 EVA

We hereby introduce the manual for CMOS 4-bit microcomputer GMS340 Series. This manual is prepared for the users who should understand fully the functions and features of GMS340 Series so that you can utilize this product to its fullest capacity. A detailed explanations of the specifications and applications regarding the hardware is hereby provided.

INTRODUCTION

The contents of this user`s manual are subject to change for the reasons of later improvement of the features. The information, diagrams, and other data in this user`s manual are correct and reliable; however, Hyundai Electronics Indus tries Co., Ltd. is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual

Table of Cont en ts

Chapter 1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Outline of Characteristics . . . . . . . . . . . . . . . . . . . . . 1-1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Pin Assignment and Dimension . . . . . . . . . . . . . . . . . . . . 1-3

I/O circuit types and options . . . . . . . . . . . . . . . . . . . . . . . 1-7

Electrical Characteristics of GMS300 Series . . . . . . . . . . 1-10

Chapter 2

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . 2-1

Program Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . 2-1

ROM Address Register . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Data Me m o ry (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -3

X-Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Y-Register (Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Accumulator (Acc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

State Counter (SC) . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 2-5

Clock Ge nerato r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Initial Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Internal Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Watch Dog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Maske d Op tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Table of Contents

Chapter 3

Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Instruction format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Instruction Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Details of Instruction System . . . . . . . . . . . . . . . . . . . . 3-5

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . 3-6

Table of Contents

Chapter 4

Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Product Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Optional Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Caution of Operation . . . . . . . . . . . . . . . . . . . . . .. . . . . 4-6

Chapter 5

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Configuration of Assembler . . . . . . . . . . . . . . . . . . . . . . 5-1

Booting up Assembler . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Configuration of Simulator . . . . . . . . . . . . . . . . . . . . . . . 5-2

Booting up Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Simulator commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Description of commands . . . . . . . . . . . . . . . . . . . . . . . . 5-18

File typ es used in th e simulato r . . . . . . . . . . . . . . . . . . . 5-4 8

Error message and troubleshooting . . . . . . . . . . . . . . . . 5-49

Appendix

Mask option list

INTRODUCTION 1

ARCHITECTURE 2

INSTRUCTION 3

EVALUATION BOARD 4

SOFTWARE 5

APPENDIX 6

Chapter 1. Introduction

CHAPTER 1. Introduction

OUTLINE OF CHARACTERISTICS

The GMS340 series are remote contol transmitter which uses CMOS technology. This enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. The GMS340 sereis are suitable for remote control of TV, VCR, FANS, Airconditioners, Audio Equipments, Toys and Games etc.

Characteristics

¡Ü Program memory : 512 bytes for GMS34004/012

1024 bytes for GMS34112/120/140

¡Ü Data memory : 32 ¡Ü 43 types of instruction set ¡Ü 3 levels of subroutine nesting ¡Ü 1 bit output port for a large current (REMOUT signal) ¡Ü Operating frequency : 300~500KHz or 2.4~4MHz for 300~500KHz operation

(Masked option)

¡Ü Instruction cycle : f

¡Ü CMOS process (Single 3.0V power supply) ¡Ü Stop mode (Through internal instruction) ¡Ü Released stop mode by key input (Masked option) ¡Ü Built in capacitor for ceramic oscillation circuit (Masked option) ¡Ü Built in a watch dog timer (WDT) ¡Ü Low operating voltage : 2.0~4.0V (at 300~500KHz)

¡¿

4 bits

/6 (at 300~500KHz)

OSC

/48 (at 2.4~4MHz)

OSC

2.2~4.0V (at 2.4~4MHz)

Series

Program memory Data memory I/O ports

Input ports

Output ports

Package

GMS34004

512

32 ¡¿ 4

4 6

D0 ~ D5

16DIP/SOP

GMS34012

¡ç ¡ç

¡ç

D0 ~ D5

20DIP/SOP

GMS34112

1024

D0 ~ D5

Table 1-1 GMS340 series members

1 - 1

GMS34120

¡ç ¡ç ¡ç

¡ç

D0 ~ D7

24DIP/SOP

GMS34140

¡ç ¡ç ¡ç

¡ç

D0 ~ D9

¡ç

Chapter 1. Introduction

Block Diagram

RESET VDD GND

1 24

Reset

ROM

64word ¡¿

16page

¡¿

Instruction

Decoder

Control Signal

OSC

23 22 7 8 9 4 2110 3 5 6 11 12 13 14 15 16 17 18 19 20

OSC1 OSC2 K0 ~ K3 R0 ~ R3 D0 ~ D9 REMOUT

8bit

Program counter

MUX

X-Reg

Stack

MUX

RAM

16word x

2page x 4bit

R-Latch D-Latch

Word

Selector

4 10

Watchdog

timer

Y-Reg

ALU

ACC

Pluse

Generator

Fig 1-1 Block Diagram (In case of GMS34140)

1 - 2

Pin Assignment and terminals

Pin Assignment

Chapter 1. Introduction

1 16

RESET

2 15

GND

3 14

4 13

5 12

6 11

7 10

8 9

VDD OSC1

OSC2 REMOUT

D5 D4 D3 D2

1 20

2 19

3 18

4 17

5 16

6 15

7 14

8 13

9 12

10 11

R3 R2

R1 R0

GND RESET VDD OSC1 OSC2 REMOUT

Fig 1-2 GMS34004 Pin Assignment Fig 1-3 GMS34012/112 Pin Assignment

1 24

RESET

2 23

GND

3 22

4 21

5 20

6 19

7 18

8 17

9 16

10 15

11 14

12 13

VDD OSC1

OSC2 REMOUT

D7 D6 D5 D4 D3 D2 D1 NC

1 24

RESET

2 23

GND

3 22

4 21

5 20

6 19

7 18

8 17

9 16

10 15

11 14

12 13

VDD OSC1

OSC2 REMOUT

D7 D6 D5 D4 D3 D2 D1 D9

Fig 1-5 GMS34120 Pin Assignment

Fig 1-6 GMS34140 Pin Assignment

1 - 3

Pin Dimension

Chapter 1. Introduction

16 15 14 13 12 11 10 9

0.170MAX

0.0688MAX

1 2 3 4 5 6 7 8

0.785MAX

0.125MIN

0.135MAX

0.015MIN

0.040MAX

0.020MIN

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

0.0600MIN

0.745MIN

0.065MAX

0.050MIN

0.022MAX

0.015MIN

0.392MAX

0.386MIN

0.120MIN

0.140MAX

0.100BSC

Outline (Unit:Inch)

Fig 1-7 16PDIP Pin Dimension

¡æ ¡ç

0.244MAX

0.230MIN

0.157MAX

0.150MIN

0.300BSC

0.280MAX

0.240MIN

0.014MAX

0.008MIN

¡æ ¡ç

0~15¡Ç

Base Plane

Seating Plane

0.0040MIN

0.0098MAX

¡æ ¡ç

0.0200MAX

0.050BSC

¡Ç

0 ~ 8

Outline (Unit : Inch)

Fig 1-8 16SOP Pin Dimension (150Mil)

1 - 4

0.035MAX

0.016MIN

¡æ

¡ç

0.0098MAX

0.0075MIN

¡æ ¡ç

20 19 18 17 16 15 14 13 12 11

Chapter 1. Introduction

0.170MAX

0.104MAX

0.093MIN

1 2 3 4 5 6 7 8 9 10

0.984MAX

0.968MIN

0.065MAX

0.015MIN

0.055MIN

0.022MAX

0.015MIN

Outline (Unit : Inch)

Fig 1-10 20PDIP Pin Dimension

20 19 1 8 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10

0.5118MAX

0.4961MIN

0.1TYP

0.125MIN

0.135MAX

¡æ ¡ç

0.299MAX

0.292MIN

0.3TYP

0.270MAX

0.250MIN

0.012MAX

0.008MIN

0.419MAX

0.398MIN

¡æ ¡ç

0~15¡Ç

0.004MIN

0.0118MAX

0.020MAX

0.014MIN

¡æ ¡ç

0.05TYP

Outline (Unit : Inch)

0.125MAX

0.0091MIN

Fig 1-11 20SOP Pin Dimension

1 - 5

¡æ

0.042MAX

¡ç

0.016MIN

Chapter 1. Introduction

24 23 22 21 20 19 18 17 16 15 14

1 2 3 4 5 6 7 8 9 10 11

1.255MAX

1.245MIN

0.065MAX

0.055MIN

0.015MIN

0.170MAX

Outline (Unit : Inch)

Fig 1-12 24PDIP Pin Dimension

24 23 22 21 20 19 18 17 16 15 14

0.1TYP

0.022MAX

0.015MIN

0.125MIN

0.135MAX

¡æ ¡ç

0.3TYP

0.270MAX

0.250MIN

0.012MAX

0.008MIN

¡æ ¡ç

0~15¡Ç

0.104MAX

0.093MIN

0.018MAX

0.004MIN

1 2 3 4 5 6 7 8 9 10 11 12

0.618MAX

0.595MIN

0.05TYP

0.020MAX

0.014MIN

Outline (Unit : Inch)

Fig 1-13 24SOP Pin Dimension

1 - 6

¡æ ¡ç

0.125MAX

0.0091MIN

0.419MAX

0.396MIN

0.299MAX

0.292MIN

¡æ

0.042MAX

¡ç

0.016MIN

Chapter 1. Introduction

I/O circuit types and options

GMS340 series I/O port types

Pin Function

GND

RESET

K0~K3

D0~D9

R0~R3

REMOUT

OSC1

OSC2

I/O

Input

Output

I/O

Output

Input

Output

Connected to 2.0~4.0V power supply. Connected to 0V power supply. Used to input a manual reset. When the pin goes ¡ÈL¡È, the

D-output ports and REMOUT-output port are initialized to

¡ÈL¡È

, and ROM address is set to address 0 on page 0.

4-bit input port. Released STOP mode built in pull-up resistor by each pin as masked option. (It is released by ¡ÈL¡È input at STOP)

Each can be set and reset independently. The output is in the form of N-channel-open-drain.

4-bit I/O port. (Input mode is set only when each of them output ¡ÈH¡È.) In outputting, each can be set and reset independently(or at once.) The output is in the form of N-channel-open-drain. Pull-up resistor and STOP release mode can be respectively selected as masked option for each bit. (It is released by

¡ÈL¡È

input at STOP.)

High current output port. The output is in the form of C-MOS. The state of large current on is ¡ÈH¡È.

Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. Internal capacitors available as masked option. A feedback resistor is connected between this pin and OSC2

Connect a ceramic resonator between this pin and OSC1.

1 - 7

I/O circuit types and options

Chapter 1. Introduction

Pin I/O Note

Reset I

R0~R3 I/O

K0~K3 I

¡æ

I/O circuit

¡æ ¡ç

¡æ

¡æ ¡ç

Hysteresis Input Type Built in pull-upresistor Typical 400

(option) Built in pull-up resistor Typical 800

Open drain output

¡ÈH¡È

(Option) Built in MOS Tr for pull-up About 120

Built in MOS Tr for pull-up About 120

§Ú

output at reset

§Ú

D0~D9

REMOUT O

¡ç

¡æ ¡ç

1 - 8

Open drain output

¡ÈL¡È

output at reset

CMOS output

¡ÈL¡È

output at reset High current source output

Chapter 1. Introduction

Pin I/O Note

OSC2 O

OSC1 I

: Masked option

*. Recommendable circuit

OSC1

OSC2

OSCSTB

OSC1

I/O circuit

¡æ

¡è ¡è

¡ç

¡æ

¡ç

OSC2

Built in feedbackResister About 1

Built in dumping-Resister [No resistor in MHz operation]

(Option) Built in resonance Capacitor C1/C2 = 100pF N% [C1/C2 are not available for MHz operation]

§Û

¡¾

Frequency Resonator Maker Part Name Load Capacitor Operating Voltage

Murata CSB455E C1=C2=Open 2.0 ~ 4.0V

455KHz

480KHz

3.64MHz

3.84MHz

¡Ø

CST type is building in load capacitior

Kyocera KBR-455BKTL70 C1=C2=Open 2.0 ~ 4.0V

TDK FCR455K3 C1=C2=Open 2.0 ~ 4.0V

Murata

TDK FCR480K3 C1=C2=Open 2.0 ~ 4.0V Murata CSA3.64MG C1=C2=30pF 2.2 ~ 4.0V Murata CST3.64MGW C1=C2=Open 2.2 ~ 4.0V

TDK FCR3.64MC5 C1=C2=Open 2.2 ~ 4.0V Murata CSA3.84MG C1=C2=30pF 2.2 ~ 4.0V Murata CST3.84MGW C1=C2=Open 2.2 ~ 4.0V

TDK FCR3.84MC5 C1=C2=Open 2.2 ~ 4.0V

CSB480E C1=C2=Open 2.0 ~ 4.0V

1 - 9

Chapter 1. Introduction

Electrical Characteristics for GMS300 series

Absolute maximum ratings (Ta = 25¡É)

Parameter

Supply Voltage Power dissipation Storage temperature range

Input voltage Output voltage

* Thermal derating above 25¡É : 6mW per degree ¡É rise in temperature.

Recommended operation condition

Parameter

Supply Voltage

Operating temperature

Symbol

Topr

Symbol

Tstg

OUT

Condition

300 ~ 500KHz

2.4 ~ 4MHz

Max. rating

-0.3 ~ 5.0

¡É

700

-55 ~ 125

-0.3 ~ VDD+0.3

Rating

2.0 ~ 4.0

2.2 ~ 4.0

-20 ~ +70

Unit

¡É

V V

Unit

¡É

1 - 10

Electrical characteristics (Ta=25¡É, VDD=3V)

Chapter 1. Introduction

Parameter

Input H current

RESET input L current

K, R input L current

K, R input H voltage K, R input L voltage

RESET input H voltage RESET input L voltage

D. R output L voltage REMOUT output L

voltage REMOUT output H voltage

OSC2 output L voltage

OSC2 output H voltage D, R output leakage

current Current on STOP mode Operating supply current

1 Operating supply current 2 System clock frequency

OSC

/48 f

OSC

Symbol

IL2

IL1

IH1

IL1

IH2

IL2

OL2

OL1

OH1

OL3

OH3

STOP

DD1

DD2

OSC

Limits

Min. Typ. Max.

-16

-50

0.9

0.7

0.4

0.9

1.0

1.5

500

-2

-9

2.1

2.2 5

2.1

300

2.4

-7.5

-25

0.1

2.5

0.4

2.5

0.3

0.5

Unit Condition

VI=V

VI=GND VI=GND, Output

off, Pull-Up resistor provided.

IOL=1mA

IOL=100uA

IOH=8mA

IOL=70uA

IOH=70uA

V0=VDD, Output off

At STOP mode

=455KHz

OSC

=4MHz

OSC

KHz MHz

1 - 11

INTRODUCTION 1

ARCHITECTURE 2

INSTRUCTION 3

EVALUATION BOARD 4

SOFTWARE 5

APPENDIX 6

CHAPTER 2. Architecture

BLOCK DESCRIPTION

Characteristics

The GMS340 series can incorporate maximum 1024 words (64 words ¡¿ 16 pages ¡¿ 8bits) for program memory. Program counter PC (A0~A5) and page address register (A6~A9) are used to address the whole area of program memory having an instruction (8bits) to be next executed. The program memory consists of 64 words on each page, and thus each page can hold up to 64 steps of instructions. The program memory is composed as shown below.

Chapter 2. Architecture

Program capacity (pages)

Page 0 Page 1 Page 2 Page 15

A0~A5

Program counter (PC) Page address register (PA) Page buffer (PB)

0 1 2 15

6 4

Stack register

(Level ¡È1¡È)

(Level ¡È2¡È)

(Level ¡È3¡È)(PRS)(SR)

A6~A9

Fig 2-1 Configuration of Program Memory

2 - 1

Chapter 2. Architecture

ROM Address Register

The following registers are used to address the ROM.

• Page address register (PA) : Holds ROM`s page number (0~Fh) to be addressed.

• Page buffer register (PB) : Value of PB is loaded by an LPBI command when newly addressing a page. Then it is shifted into the PA when rightly executing a branch instruction (BR) and a subroutine call (CAL).

• Program counter (PC) : Available for addressing word on each page.

• Stack register (SR) : Stores returned-word address in the subroutine call mode.

(1) Page address register and page buffer register :

Address one of pages #0 to #15 in the ROM by the 4-bit binary counter. Unlike the program counter, the page address register is usually unchanged

so that the program will repeat on the same page unless a page changing command is issued. To change the page address, take two steps such as (1) writing in the page buffer what page to jump to (execution of LPBI) and (2) execution of BR or CAL, because and instruction code is of eight bits so that page and word cannot be specified at the same time. In case a return instruction (RTN) is executed within the subroutine that has been called in the other page, the page address will be changed at the same time.

(2) Program counter :

This 6-bit binary counter increments for each fetch to address a word in the currently addressed page having an instruction to be next executed. For easier programming, at turning on the power, the program counter is reset to the zero location. The PA is also set to ¡È0¡È. Then the program counter specifies the next ROM address in random sequence. When BR, CAL or RTN instructions are decoded, the switches on each step are turned off not to update the address. Then, for BR or CAL, address data are taken in from the instruction operands (a0 to a5), or for RTN, and address is fetched from stack register No. 1.

(3) Stack register :

This stack register provides two stages each for the program counter (6 bits) and the page address register (4bits) so that subroutine nesting can be mode on two levels.

2 - 2

Chapter 2. Architecture

Data memory (RAM)

Up to 32 nibbles (16 words ¡¿ 2pages ¡¿ 4bits) is incorporated for storing data. The whole data memory area is indirectly specified by a data pointer (X,Y). Page number is specified by zero bit of X register, and words in the page by 4 bits in Y-register. Data memory is composed in 16 nibbles/page. Figure 2.2 shows the configuration.

X-register (X)

D0 D9 R0 R3 REMOUT

Output port

Y-register (Y) X-register (X)

4 2

Fig 2-2 Composition of Data Memory

Data memory page (0~1)

Page 0 Page 1

0 14 A0~A3

X-register is consist of 2bit, X0 is a data pointer of page in the RAM, X1 is only used for selecting of D8~D9 with value of Y-register

X1=1X1=0

Y=0 Y=1 D1

Table 2-1 Mapping table between X and Y register

2 - 3

D8 D9

Chapter 2. Architecture

Y-register (Y)

Y-register has 4 bits. It operates as a data pointer or a general-purpose register. Y-register specifies and address (a0~a3) in a page of data memory, as well as it is used to specify an output port. Further it is used to specify a mode of carrier signal outputted from the REMOUT port. It can also be treated as a generalpurpose register on a program.

Accumulator (ACC)

The 4-bit register for holding data and calculation results.

Arithmetic and Logic Unit (ALU)

In this unit, 4bits of adder/comparator are connected in parallel as it`s main components and they are combined with status latch and status logic (flag.)

(1) Operation circuit (ALU) :

The adder/comparator serves fundamentally for full addition and data comparison. It executes subtraction by making a complement by processing an inversed output of ACC (ACC+1)

(2) Status logic :

This is to bring an ST, or flag to control the flow of a program. It occurs when a specified instruction is executed in two cases such as overflow in operation and two inputs unequal.

2 - 4

Chapter 2. Architecture

State Counter (SC)

A fundamental machine cycle timing chart is shown below. Every instruction is one byte length. Its execution time is the same. Execution of one instruction takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total). Virtually these two cycles proceed simultaneously, and thus it is apparently completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN instructions is normal execution time since they change an addressing sequencially. Therefore, the next instruction is prefetched so that its execution is completed within the fetch cycle.

T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6

Phase

Fetch cycle N

Execute cycle N-1

¥°

¥±

¥²

Machine

Cycle

Fig. 2-3 Fundamental timing chart

Execute cycle N

Fetch cycle N-1

Machine

Cycle

2 - 5

Chapter 2. Architecture

Clock Generator

The GMS340 series has an internal clock oscillator. The oscillator circuit is designed to operate with an external ceramic resonator. Internal capacitors are available as a masked option. Oscillator circuit is able to organize by connecting ceramic resonator to outside. (In order to built in capacitor for oscillation as masked option.) * It is necessary to connect capacitor to outside in order to change ceramic resonator, You must examine refer to a manufacturer`s

OSC1 OSC2

23 22

C1 C2

Operating Frequency

= 2.4 ~ 4MHz

OSC

= 300 ~ 500KHz

OSC

Internal capacitor option

No Internal capacitor option Circuit 1

OSC1 OSC2

23 22

Oscillation Circuit

Circuit 1 Circuit 2

2 - 6

Chapter 2. Architecture

Pulse generator

The following frequency and duty ratio are selected for carrier signal outputted from the REMOUT port depending on a PMR (Pulse Mode Register) value set in a program.

PMR

1 2 3 4 5 6 T=1/f

* Default value is ¡È0

T=1/f

= 12/f

PUL

T=1/f

= 12/f

PUL

T=1/f

= 8/f

PUL

OSC

T=1/f

= 8/f

PUL

OSC

T=1/f

= 11/f

PUL

No Pulse (same to D0~D9)

= 12/f

PUL

¡È

REMOUT signal

[96/f

OSC

[96/f

OSC

[64/f

], T1/T = 1/2

OSC

[64/f

], T1/T = 1/4

OSC

[88/f

OSC

[96/f

OSC

], T1/T = 1/20

], T1/T = 1/3

], T1/T = 4/11

], T1/T = 1/4

* [ ] means the value of ¡ÈT¡È, when Instruction cycle is f

Table 2-2 PMR selection table

OSC

/48

2 - 7

Chapter 2. Architecture

Initial Reset Circuit

RESET pin must be down to ¡ÈL¡È more than 4 machine cycle by outside capacitor or other for power on reset. The mean of 1 machine cycle is below. 1 machine cycle is 6/f operating voltage must be in recommended operating conditions, and clock oscillating stability. * It is required to adjust C value depending on rising time of power supply.

(Example shows the case of rising time shorter than 10ms.)

RESET

0.1uF

Watch Dog Timer (WDT)

Watch dog timer is organized binary of 14 steps. By the selected oscillation option, the signal of f

/6 cycle comes in the first step of WDT. If this counter

OSC

was overflowed, come out reset signal automatically, internal circuit is initialized. The overflow time is 6¡¿2 13/f

8¡¿6¡¿213/f

(108.026ms at f

OSC

(108.026ms at f

OSC

=455KHz.)

OSC

= 3.64MHz) Normally, the binary counter must be reset before the overflow by using reset instruction (WDTR) or / and REMOUT port (Y-reg=8, So instruction execution) at masked option.

, however,

OSC

* It is constantly reset in STOP mode. When STOP is released, counting is restarted. (Refer to 2-10 STOP function>)

Binary counter (14 steps)

Reset by instruction

REMOUT output

OSC

/6 or f

OSC

/48

RESET (edge-trigger)

Mask Option

2 - 8

CPU reset

Chapter 2. Architecture

STOP Function

Stop mode can be achieved by STOP instructions. In stop mode :

1. Oscillator is stopped, the operating current is low.

2. Watch dog timer is reset, D8~D9 output and REMOUT output are ¡ÈL¡È.

3. Part other than WDT, D8~D9 output and REMOUT output have a value before come into stop mode.

¡ÈBut, the state of D0~D7 output in stop mode is able to choose as masked option. ¡ÈL¡È output or same level before come into stop mode.

The function to release stop mode is able to choose each bit of K or R input. Stop mode is released when one of K or R input is going to ¡ÈL¡È.

1. State of D0~D7 output and REMOUT output is return to state of before stop mode is achieved.

2. After 1024¡¿8 enable clocks for stable oscillating. First instruction start to operate.

3. In return to normal operation, WDT is counted from zero again.

But, at executing stop instruction, if one of K or R input is chosen to ¡ÈL¡È, stop instruction is same to NOP instruction.

Masked options

The GMS340 series offer the following optional features. These options are masked.

1. Watch dog timer reset by REMOUT output signal.

2. Input terminals having STOP release mode : K0~K3, R0~R3.

3. I/O terminals having pull-up resistor : R0~R3

4. Ceramic oscillation circuit contained (or not contained). [This option is not available for MHz Ceramic oscillator]

5. Output form at stop mode

D0~D7 : ¡ÈL¡È or keep before stop mode

6. Instruction cycle selection: T=48/f

OSC

or T=6/f

OSC

2 - 9

INTRODUCTION 1

ARCHITECTURE 2

INSTRUCTION 3

EVALUATION BOARD 4

SOFTWARE 5

APPENDIX 6

CHAPTER 3. Instruction

INSTRUCTION FORMAT

All of the 43 instruction in GMS340 series is format in two fields of OP code and operand which consist of eight bits. The following formats are available with different types of operands.

Chapter 3. Instruction

Format

¥°

All eight bits are for OP code without operand.

¥±

Two bits are for operand and six bits for OP code. Two bits of operand are used for specifying bits of RAM and X-register (bit 1 and bit 7 are fixed at ¡È0¡È)

¥²

Four bits are for operand and the others are OP code. Four bits of operand are used for specifying a constant loaded in RAM or Yregister, a comparison value of compare command, or page addressing in ROM.

¥³

Six bits are for operand and the others are OP code. Six bits of operand are used for word addressing in the ROM.

3 - 1

Chapter 3. Instruction

INSTRUCTION TABLE

The GMS340 series provides the following 43 basic instructions.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17

HEI GMS34120, GMS34140, GMS34004, GMS34112, GMS34012 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Block Diagram

Pin Assignment