HEI GM6535 Datasheet
1
CLK
D in
AD in
CLK
D in
AD in
16DIP
16 SOP (150Mil)
GM6535
GM6535
60 MHz Universal Programmable
Dual PLL Frequency synthesizer
GENERAL DESCRIPTIONS
The GM6535 is a dual phase – locked loop
(PLL) frequency synthesizer especially designed for
CT-1 cordless phone applications worldwide. This
frequency synthesizer is also for any products with
frequency operation at 60 MHz or below.
The device features fully programmable
receive, transmit, reference, and auxiliary reference
counters accessed through an MCU serial interface,
this feature allows this device to operate in any CT1 cordless phone application.
The device consists of two independent phase
detectors for transmit and receive loops. A common
reference oscillator, driving two independent
reference frequency counters, provides independent
reference frequencies for transmit and receive loops.
The auxiliary reference counter allows the
user to select an additional reference frequency for
receive and transmit loops if required.
PIN CONFIGURATION
ENB
MCUCLK
Vss
OSC
OSC
out
i
Tx PD
fin-T
TxPS/f
VDD
RxPS/f
RxPD
fin-R
OUT
Tx
Rx
o
FEATURES
• Operating Voltage Range: 2.5 to 5.5 V
• Operating Temperature Range:-40 to +75¡É
• Operating Power Consumption:3.0mA@2.5V
• Maximum Operating Frequency:
60MHz@200mV
• 3 or 4 Pins Used for serial MCU Interface
• Power Saving Mode Controlled by MCU
• Lock Detect Signal
• On-Chip Reference Oscillator Supports External
Crystals to 16.0 MHz
• Reference Frequency Counter Division Range: 16 to
4095
• Auxiliary Reference Frequency Counter Division
Range: 16 to 16,383
• Transmit Counter Division Range:16 to 65,535
• Receive Counter Division Range: 16 to 65,53
ENB
MCUCLK
OSC
OSC
Vss
out
i
, VDD=2.5V
p-p
Tx PD
fin-T
TxPS/f
VDD
RxPS/f
RxPD
fin-R
OUT
Tx
Rx
o
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to v
)
ss
Symbol
Ranting Value Unit
VDD DC Supply Voltage -0.5 to +6.0 V
V
Iin , I
IDD , I
T
stg
in
Input Voltage, all Inputs -0.5 to V
DC Current Drain Per Pin 10 mA
out
DC Current Drain VDD or VSS Pins 30 mA
SS
+0.5 V
DD
Storage Temperature Range -65 to + 150
¡É
2
BLOCK DIAGRAM
12-Bit Shift
14-Bit Shift
MCU Interface Programming
16-Bit Tx Programmable
16-Bit Rx Programmable
Rx
Rx
TRANSMIT
RECEIVE
OSC
in
8
OSC
out
7
MCUCLK
5
AD
in
2
1
CLK
D
in
ENB
TX
RX
3
4
13
11
TxPS/f
PxPS/f
÷ 3 / ÷ 4
12-Bit Programmable
Reference Counter
14-Bit Programmable
Auxiliary Reference
Counter
Register
Mode control Register
16-Bit Shift Register
Register
÷ 4
÷ 25
A
B
C
D
f
R1
f
R2
SELECT
Phase
Detector
GM6535
TxPD
out
15
LD
16
f in
14
-T
Counter
16-Bit Shift Register
SELECT
Phase
Detector
RxPD
10
out
f in
9
-R
Counter
VDD = PIN 12
VSS = PIN 6
3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA =25 ¡É)
V
V
V
V
V
V
I
OL
I
IL
Power Supply Voltage - 2.5 5.5
DD
Output Voltage 0 Level
OL
OH
IL
IH
OH
(I
= 0)
out
(V
or 0) 1 Level
in =VDD
Input Voltage 0 Level
(V
0.5 V or V
out
1 Level
Output Current (V
Input Current OSC
(Vin = 0)
ADin , CLK , Din , ENB
Characteristic V
– 0.5V)
DD
= 2.2V) Source
out
(V
= 5.0V)
out
(V
= 0.3V) Sink
out
(V
= 0.5V)
out
, f
in
in-T
, f
in-R
Symbol
(Vin = VDD –0.5)
IIH
I
OZ
C
in
C
out
IDD
(standby)
I
DD
OSC
ADin
Three-Stats Leakage Current (V
, CLK , Din , ENB
= 0 V or 5.5 V)
out
Input Capacitance - - 8.0 pF
Output Capacitance - - 8.0 pF
Standby Current
(All Counters are in Power-Down Mode with Oscillator On)
Operating Current (200mV
input at f
p-p
in-T
=60MHz, OSC = 10.24MHz)
, f
, f
in
in-T
in-R
= 60MHz, and f
in-R
Guaranteed Limit
DD
Min Max
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
5.5
2.5
5.5
2.5
5.5
-
-
2.45
5.45
-
-
1.75
3.85
-0.18
-0.55
0.18
0.55
-
-
-
-
-
-
-
-
- ¡¾100 nA
-
-
-
-
GM6535
0.1
0.1
-
-
0.75
1.65
-
-
-
-
-
-
-30
-66
-1.0
-1.0
30
61
5.0
5.0
0.3
1.5
3.0
10
Unit
V
V
V
mA
¥ìA
¥ìA
mA
mA
4
tTLH
tTHL
ANY
OUTPUT
in
f
in-T, f in-R
SWITCHING CHARACTERISTICS (TA = 25
t
TLH
t
THL
tT, t
t
f
max
Output Rise Time
Output Fall Time
Input Rise and Fall Time, OSC
f
Input Pulse Width, CLK and ENB
W
Input frequency OSCin
(Input = Sine Wave @ ≥ 200mV
Characteristic Figure # V
Symbol
t
t
Setup Time Data to CLK
t
su
Hold Time, CLK to Data
t
h
Recovery Time, ENB to CLK
rec
Setup Time, ENB to CLK 4 2.5-5.5 80
sul
t
Hold Time, CLK to ENB 4 2.5-5.5 600 - ns
hl
in
p-p
¡É, CL = 50 pF)
f
ENB to CLK
in-T
f
in-R
1
1
2
3
5
5
5
DD
2.5
5.5 - -
2.5
5.5 - -
2.5
5.5 - -
2.5
5.5
2.5-5.5
2.5-5.5
2.5-5.5
2.5-5.5
5.5-5.5
2.5
5.5
2.5
5.5
GM6535
Min Max Unit
200
100
200
100
5.0
4.0
80
60
-
-
100
200
80
40
80
40
ns
ns
µs
ns
-
16
MHz
60
60
ns
-
ns
-
ns
-
- ns
SWITCHING WAVERORMS
90%
10%
CLK, OSC
90%
10%
t
r
ENB, CLK
50%
Figure 1.
Figure 2.
t
W
Figure 3.
t
f
V
DD
V
SS
V
DD
V
SS
5
LAST
FIRST
AD in,
FIRST
LAST
PREVIOUS
CLK
CLK
t
hl
ENB
CLK
t
sul
Figure 4.ENB High During Serial Transfer
D in
CLK
50%
t
su
50%
t
su
CLK
t
h
CLK
t
rec
GM6535
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
ENB
50%
DATA LATCHED
V
DD
V
SS
Figure 5. ENB Low During Serial Transfer
6
PIN DESCRIPTIONS
D C
B A
OSC
in
OSC
out f R1
f
R2
Figure 6. Reference Frequencies for Cordless Phone
OSCin/OSC
out
Reference Oscillator Input/Output (Pins8, 7)
These pins form a reference oscillator when
connected to an external parallel-resonant crystal
frequencies and reference frequencies for cordless
phone applications in various countries. OSCin may
also serve as input for an externally generated
reference signal which is typically ac coupled.
ADin, Din, CLK, ENB
Auxiliary Data In, Data In, Clock, Enable (Pins2, 3,
1, 4)
These four pins provide an MCU serial interface for
programming the reference counter, the transmitchannel counter, and the receive-channel counter. They
also provide various controls of the PLL including the
power saving mode and the programming format.
TxPS/fTx,RxPS/f
Rx
Transmit Power Save, Receive Power Save (Pins 13,
11)
For a normal application, these output pins provide
the status of the internal power saving mode operation.
If the transmit channels counter circuitry is in power
down mode, TxPS/fTx outputs a high state. If the
receive-channels counter circuitry is in power down
mode, RxPS/fRx is set high. These output can be
applied for controlling the external power switch for
the transmitter and the receiver to save MCU control
pins. In the Tx/Rx channel counter test mode, the
TxPS/fTx and RxPS/fRx pins output the divided value of
the transmit channel counter (fTx) and the receive
channel counter (fRx), respectively. This test mode
operation is controlled by the control register. Details
of the counter test mode are in the Tx/Rx Channel
Counter Test section of this data sheet.
÷ N (12 bits)
÷ M ( 14bits )
Crystal ¡ÀN Value f
11.150 MHz 446 6.25 MHz 1.0 MHz
11.150 MHz 223 12.5 MHz
10.240 MHz 512 5.0 MHz
12.000 MHz 600 5.0 MHz
Applications of Various Countries
GM6535
f
Transmit/Receive Counter Inputs (Pins14, 9)
receive counters, respectively. These signals are
typically driven from the loop VCO and ac-coupled.
The minimum input signal level is 200mV
60.0MHz.
TxPD
Transmit/Receive Phase detector Outputs (Pins15,
10)
receive phase detectors for use as loop error signals
(see Figure7 for phase detector output waveforms).
Frequency fV > fR or fV leading: output=negative pulse.
Frequency fV < fR or fV lagging: output = positive pulse.
Frequency fV = fR and phase coincidence: output = high
impedance state.
phase detector input and fV is the divided-down VCO
frequency at the phase detector input.
LD Lock Detect (Pin16)
loop. The output at a high level indicates an out-oflock condition (see Figure 7 for the LD output
waveform).
VDD Positive Power Supply (Pin 12)
ranging from 2.5 to 5.5V with respect to VSS.
VSS Negative Power Supply (Pin 6)
usually connected to ground.
in-T/fin-R
f
in-T
and f
out
are inputs to the transmit and the
in-R
/RxPD
out
p-p
These are three-state outputs of the transmit and
fR is the divided-down reference frequency at the
The lock detect signal is associated with the transmit
VDD is the most positive power supply potential
VSS is the most negative supply potential and is
÷4
÷25
¡æ B f
R1
¡æ C
R2
@
7
f R ,REFERENCE
REFERENCE COUNTER)
f v ,FEEDBACK
Tx COUNTER OR
Rx COUNTER)
TxPD
(OSC
÷
in
(F
÷
in - T
f
÷
in -_R
RxPD
OR
out
out
LD
V H = High voltage level
V L = Low voltage level
*At this point, when both fR and fv are in phase, the output is forced to near mid supply.
NOTE: The TxPD
When locked in phase and frequency, the output is high impedance and the voltage at that pin is determined
By the low-pass filter capacitor
and PxPDout generates error pulses during out-of-lock conditions.
out
Figure 7. Phase Detector/Lock Detector Output Waveforms
MCU PROGRAMMING SCHEME
The MCU programming scheme is defined in
two formats controlled by the ENB input. If the
enable signal is high during the serial data transfer,
control register/reference frequency programming is
selected. If the ENB is low, programming of the
transmit and receive counters is selected. During
programming of the transmit and receive counters,
both AD in and D in pins can input the data to the
transmit and receive counters. Both counters data is
clocked into the PLL internal shift register at the
leading edge of the CLK signal. It is not necessary
to reprogram the reference frequency
counter/control register when using the enable
signal to program the transmit/receive channels.
In programming the control register/reference
frequency scheme, the most significant bit (MSB) of
the programming word identifies whether the input
data is the control word. If the MSB is 1, the input
data is the control word (Figure 8). Also see figure
NO TAG and Table 1 for control register and bit
function. If the MSB is 0, the input data is the
reference frequency (Figure 9).
The reference frequency data word is 32-bit word
containing the 12-bit reference frequency data, the
14-bit auxiliary reference frequency counter
information, the reference frequency selection plus,
the auxiliary reference frequency counter enable
bit(Figure 9).
If the AUX REF ENB bit is high, the 14-bit
auxiliary reference frequency counter provides an
additional phase reference frequency output for the
loops. If AUX REF ENB bit is low, the auxiliary
reference frequency counter is forced into powerdown modes for current saving. (other power down
modes are also provided through the control register
per Table 2 and Figure 8). At the falling edge of the
ENB signal, the data is stored in the registers.
There are two interfacing schemes for the
universal channel mode: the three-pin and four-pin
interfacing schemes. The three-pin interfacing
scheme is suited for use with the MCU SPI (serial
peripheral interface) (Figure 10), while the four-pin
interfacing scheme is commonly used for general
I/O port connection (Figure 11).
For the three-pin interfacing scheme, the
auxiliary data select bit is set to 0. All 32 bits of data,
which define both the 16-bit transmit counter and
the 16-bit receive counter, latch into the PLL
internal register though the data in pins at the
leading edge of CLK. See Figure 12 and 13.
For the four-pin interfacing scheme, the auxiliary
data select bit is set to 1. In this scheme, the 16-bit
transmit counter’s data enters into the ADin pin at
the same time as the 16-bit receive. This
simultaneous entry of the transmit and receive
counters causes the programming period of the fourpin scheme to be half that of the three-pin scheme
(see Figures 14 and 15).
While programming Tx/Rx Channel Counter,
the ENB pin must be pulsed to provide falling edge
to latch the shifted data after the rising edge of the
last clock. Maximum data transfer rate is 500 kbps.
V
H
V
L
V
H
V
L
V
H
HIGH IMPEDANCE
GM6535
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