DISSEMINATION OR USE OF THIS INFORMATION IS NOT PERMITTED WITHOUT THE
WRITTEN PERMISSION OF ROCKWELL INTERNATIONAL.
Order No. 1129
Rev. 1, August 19, 1997
RCV56HCF PCI/CardBus Modem Designer’s Guide
NOTICE
Information furnished by Rockwell International Corporation is believed to be accurate and reliable. However, no
responsibility is assumed by Rockwell International for its use, nor any infringement of patents or other rights of third parties
which may result from its use. No license is granted by implication or otherwise under any patent rights of Rockwell
International other than for circuitry embodied in Rockwell products. Rockwell International reserves the right to change
circuitry at any time without notice. This document is subject to change without notice.
K56flex is a trademark of Lucent Technologies and Rockwell International.
MNP 10EC and DigiTalk are trademarks of Rockwell International.
MNP is a trademark of Microcom Systems, Inc.
VoiceView is a registered trademark of Radish Communications, Inc.
Hayes is a trademark of Hayes Microcomputer Products, Inc.
2.2 DATA MODE..............................................................................................................................................2-1
2.6.4 Tone Detectors................................................................................................................................. 2-3
3.3 INTERFACE TIMING AND WAVEFORMS................................................................................................3-22
3.3.1 PCI Bus Timing...............................................................................................................................3-22
3.3.2 Serial EEPROM Timing...................................................................................................................3-22
3.3.3 External Device Bus Timing ............................................................................................................3-23
4.1 PC BOARD LAYOUT GUIDELINES............................................................................................................4-1
4.1.1 General Principles.............................................................................................................................4-1
4.1.3 Signal Routing ..................................................................................................................................4-2
5.1.1 Vendor ID Field.................................................................................................................................5-1
5.1.2 Device ID Field ................................................................................................................................ .5-1
5.1.4 Status Register................................................................................................................................. 5-2
5.1.5 Revision ID Field...............................................................................................................................5-3
5.1.6 Class Code Field...............................................................................................................................5-3
5.1.8 Header Type Field ............................................................................................................................5-3
Figure 1-1. RCV56HCF System Overview..........................................................................................................................1-4
Table 3-1. Bus Interface 176-Pin TQFP Pin Signals...........................................................................................................3-5
Table 3-2. Bus Interface Pin Signal Definitions...................................................................................................................3-7
Table 3-4. MDP Pin Signal Definitions..............................................................................................................................3-15
Table 3-5. Current and Power Requirements ...................................................................................................................3-18
Table 3-6. Maximum Ratings........................................................................................................................................... 3-18
Table 3-7. PCI Bus DC Specifications for 3.3V Signaling..................................................................................................3-19
Table 3-8. PCI Bus AC Specifications for 3.3V Signaling..................................................................................................3-19
Table 3-9. MDP Digital Electrical Characteristics..............................................................................................................3-20
Table 3-10. Analog Electrical Characteristics ...................................................................................................................3-21
Table 3-11. Timing - Serial EEPROM Interface................................................................................................................3-22
Table 3-12. Timing - External Device Bus Interface............................................................................. .............................3-23
Table 5-3. Status Register.................................................................................................................................................5-2
Table 6-1. Command Set Summary - Functional Use Sort .................................................................................................6-1
Table 6-2. Command Set Summary - Alphanumeric Sort...................................................................................................6-4
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1. INTRODUCTION
1.1 SUMMARY
The Rockwell RCV56HCF-PCI Host-Controlled Modem Device Family supports high speed analog data, high speed fax,
ISDN, DSVD, AudioSpan, speakerphone, audio/voice, and VoiceView operation. It operates with PSTN or ISDN telephone
lines in the U.S. and world-wide and is offered in several device models (see Table 1-1).
The modem device set consists of PC PCI bus interface (BIF) and modem data pump (MDP) hardware available in two thin
quad flat packs (TQFPs). Host-controlled modem software is also provided.
Operating with +3.3V power, this device set supports 32-bit host applications in such designs as embedded motherboards,
PCI half cards, and CardBus cards.
Figure 1-1 illustrates the general structure of the RCV56HCF software and the interface to the RCV56HCF hardware. Figure
1-2 illustrates the major hardware interfaces supported by each model.
The RCV56HCF employs a downloadable architecture so that the user can update MDP executable code.
Using K56flex technology, the RCV56HCF can receive data at speeds up to 56 kbps from a digitally connected K56flex-
compatible central site modem, such as a Rockwell RC56CSM modem. K56flex modems take advantage of the PSTN which
is primarily digital except for the client modem to central office local loop and are ideal for applications such as remote
access to an Internet service provider (ISP), on-line service, or corporate site. The RCV56HCF can send data at speeds up
to V.34 rates.
In V.34 data mode, the modem operates at line speeds up to 33600 bps. Error correction (V.42/MNP 2-4) and data
compression (V.42 bis/MNP 5) maximize data transfer integrity and boost average data throughput. Non-error-correcting
mode is also supported.
AudioSpan (analog simultaneous audio/voice and data) operation supports a data rate with audio of 4.8 kbps.
SP models support position independent, full-duplex speakerphone (FDSP), as well as digital simultaneous voice and data
(DSVD) with speech coding per ITU-T G.729 Annex A with interoperable G.729 Annex B, and SIG DigiTalk DSVD.
The modem supports fax Group 3 send and receive rates up to 28800 bps and T.30 protocol.
V.80 and Rockwell Video Ready compatible synchronous access modes support host-controlled communication protocols, e.
g., H.324 video conferencing.
In voice/audio mode, PCM coding and decoding at 8000 Hz sample rate allows efficient digital storage of voice/audio. This
mode supports digital telephone answering machine, voice annotation, and audio recording/playback applications.
AccelerATor kits and reference designs are available to minimize application design time and costs.
This designer's guide describes the modem hardware capabilities and identifies the supporting commands. Commands and
parameters are defined in the RCVHCF Command Reference Manual (Order No. 1118).
1.2 FEATURES
•
Data modem
−
K56flex, 33.6 kbps, 31.2 kbps, V.34, V.32 bis, V.32, V.22 bis, V.22A/B, V.23, and V.21; Bell 212A and 103
The RCV56HCF Device Set provides the processing core for a complete system design featuring data/fax modem, DSVD,
AudioSpan, speakerphone, voice/audio, and VoiceView depending on specific model (Table 1-1). Note: RCV56HCF Device
Set refers to the family of single device modem models listed in Table 1-1.
The modem is the full-featured, self-contained data modem/fax modem/DSVD/voice/audio/speakerphone solution. Dialing,
call progress, telephone line interface, AudioSpan, DSVD, speakerphone, voice/audio, and VoiceView functions are
supported and controlled through the command set.
The modem hardware connects to the host PC via a PCI bus interface. The OEM adds a crystal circuit, telephone line
interface, telephone interface (optional), audio interface (optional), and ISDN interface (optional) to complete the system.
1.3.2 Operating Modes
Data/Fax Modes
In K56flex mode, the modem can receive data from a digital source using a K56flex -compatible central site modem (e.
g., Rockwell RC56CSM) over the digital telephone network portion of the PSTN at line speeds up to 56 kbps. Asymmetrical
data transmission supports sending data at V.34 rates. This mode can fall back to full-duplex V.34 mode, and to slower rates
as supported by line conditions.
In V.34 data modem mode, the modem can also operate in 2-wire, full-duplex, asynchronous modes at line rates up to
33600 bps. Data modem modes perform complete handshake and data rate negotiations. Using V.34 modulation to optimize
modem configuration for line conditions, the modem can connect at the highest data rate that the channel can support from
33600 bps to 2400 bps with automatic fallback. Automode operation in V.34 is provided in accordance with PN3320 and in
V.32 bis in accordance with PN2330. All tone and pattern detection functions required by the applicable ITU or Bell standard
are supported.
In fax modem modes, the modem fully supports Group 3 facsimile send and receive speeds of 28800, 14400, 12000, 9600,
7200, 4800, or 2400 bps. Fax modes support Group 3 fax requirements. Fax data transmission and reception performed by
the modem are controlled and monitored through the fax EIA-578 Class 1 command interface. Full HDLC formatting, zero
insertion/deletion, and CRC generation/checking are provided.
Both transmit and receive fax data are buffered within the modem. Data transfer to and from the DTE is flow controlled by
XON/XOFF and RTS/CTS.
AudioSpan Modes
AudioSpan provides full-duplex analog simultaneous audio/voice and data over a single telephone line at a data rate with
audio of 4800 bps using V.61 modulation. AudioSpan can send any type of audio waveform, including music. Data can be
sent with or without error correction. The audio/voice interface can be in the form of a headset, handset, or microphone and
speaker (half-duplex speakerphone). Handset echo cancellation is provided.
Host-Controlled DSVD Mode (ISDN and SP Models)
ISDN and SP models support host-controlled DSVD. A microphone and a speaker are required.
ITU-T interoperable G.729 and G.729 Annex A with interoperable G.729 Annex B Operation.
supports speech coding at an average bit rate significantly lower than 8.0 kbps.
SIG DigiTalk.
Voice/Audio Mode (V Models)
Voice/Audio Mode features include 8-bit linear and 8-bit µ-Law coding/decoding, tone detection/generation and call
discrimination, concurrent DTMF detection, and 8-bit monophonic audio data encoding at 11.025 kHz or 8000 Hz.
Voice/Audio Mode is supported by three submodes:
1. Online Voice Command Mode supports connection to the telephone line or a voice/audio I/O device (e.g., microphone,
speaker, or handset).
2. Voice Receive Mode supports recording voice or audio data input at the MIC_M pin, typically from a
microphone/handset or the telephone line.
3. Voice Transmit Mode supports playback of voice or audio data to the TXA1_L1/TXA2_L1 output, typically to a
speaker/handset or to the telephone line.
Speech coding is performed at 8.5 kbps.
Voice activity detection
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RCV56HCF PCI/CardBus Modem Designer’s Guide
Speakerphone Mode (ISDN and SP Models)
The speakerphone mode features an advanced proprietary speakerphone algorithm which supports full-duplex voice
conversation with both acoustic and line echo cancellation. Parameters are constantly adjusted to maintain stability with
automatic fallback from full-duplex to pseudo-duplex operation. The speakerphone algorithm allows position independent
placement of microphone and speaker.
The speakerphone mode provides hands-free full-duplex telephone operation under host control. The host can separately
control volume, muting, and AGC in microphone and speaker channels.
Synchronous Access Mode (SAM)
V.80 and Rockwell Video Ready synchronous access modes between the modem and the host/DTE are provided for host-
controlled communication protocols, e.g., H.324 video conferencing applications.
Voice-call-first (VCF) before switching to a videophone call is also supported.
1.3.3 Host-Controlled Modem Software
Host-controlled modem software performs processing of general modem control, command sets, fax Class 1, AudioSpan,
DSVD, speakerphone, voice/audio/TAM, error correction, data compression, and operating system interface functions.
Configurations of the modem software are provided to support modem models listed in Table 1-1.
Binary executable modem software is provided for the OEM.
1.3.4 Downloadable Modem Data Pump Firmware
Binary executable code controlling MDP operation is downloaded as required during operation.
1.3.5 Hardware Interfaces
1.3.5.1 PCI Bus Host Interface
The Bus Interface conforms to the PCI Local Bus Specification, Production Version, Revision 2.1, June 1, 1995. It is a
memory slave (burst transactions) and a bus master for PC host memory accesses (burst transactions). Configuration is by
PCI configuration protocol.
Four Bus Command and Byte Enable (CBE [3:0]), bidirectional
−
Bidirectional Parity (PAR); bidirectional
•
Interface control
−
Cycle Frame (FRAME#); bidirectional
−
Initiator Ready (IRDY#); bidirectional
−
Target Ready (TRDY#); bidirectional
−
Stop (STOP#); bidirectional
−
Initialization Device Select (IDSEL); input
−
Device Select (DEVSEL#); bidirectional
•
Arbitration
−
Request (REQ#); output
−
Grant (GRANT#); input
•
Error reporting
−
Parity Error ((PERR#); bidirectional
−
System Error ; bidirectional
•
Interrupt
−
Interrupt A (INTA#); output
•
System
−
Clock (PCICLK); input
−
Reset (PCIRST#); input
−
Clock Running (CLKRUN#); input
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1.3.5.2 Serial EEPROM Interface
A serial EEPROM is required to store the Maximum Latency, Minimum Grant, Device ID, Vendor ID, Subsystem ID, and
Subsystem Vendor ID parameters for the PCI Configuration Space Header.
Microchip 93LC66B, Atmel AT93C66,
line from the EEPROM (SROMIN), a serial data output line to the EEPROM (SROMOUT), Clock to the EEPROM
(SROMCLK), and chip select to the EEPROM (SROMCS).
1.3.5.3 Audio Interface
One Speaker output (SPKROUT_M) is provided for an optional OEM-supplied speaker circuit. Two microphone inputs are
supported: one for Voice Microphone input (MIC_V) and one for Music Microphone input (MIC_M), e.g., music-on-hold.
The MIC_V and SPKROUT_M lines connect to the handset and speaker to support functions such as AudioSpan headset
and speakerphone modes, FDSP, telephone emulation, microphone voice record, speaker voice playback, and call progress
monitor.
The MIC_M input can accept an external audio signal to support the music-on-hold function and routes it to the telephone
line. If music-on-hold function is not required, the microphone signal can be connected to the MIC_M input to support
telephone emulation mode.
The Speaker output (SPKROUT_M) carries the normal speakerphone audio or reflects the received analog signals in the
modem.
1.3.5.4 Telephone Line/Telephone/Audio Interface
The Telephone Line/Telephone/Audio Signal Interface can support a 3-relay telephone line interface (Figure 1-3). Signal
routing for Voice mode is shown in Table 1-2. Relay positions for VoiceView are shown in Table 1-3.
The following signals are supported:
•
A single-ended Receive Analog input (RXA_L1) and a differential Transmit Analog output (TXA1_L1 and TXA2_L1) to the
telephone line.
•
Off-hook (OH_L1#), Caller ID (CID_L1#), and Voice (VOICE_L1#) relay control outputs.
•
A Ring Indicate (IRING_L1) input.
•
A Loop Current Sense (LCS) input.
•
An input from the telephone microphone (TELIN_L1) and an output to the telephone speaker (TELOUT_L1 ) are supported
in AudioSpan modes. These lines connect voice record/playback and AudioSpan audio to the local handset.
or equivalent 256 x 16 serial EEPROM. The interface signals are: a serial data input
The EEPROM is programmable by the PC via the BIF.
The serial EEPROM interface connects to an
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RCV56HCF PCI/CardBus Modem Designer’s Guide
LCS_L1#
IRING_L1#
VOICE#
OH_L1#
CID_L1#
VC_L1
RCV56HCF
MODEM
DEVICE
TXA1_L1
TXA2_L1
RXA_L1
TELOUT_L1
TELIN_L1
MIC_M
MIC_V
SPKROUT_M
HYBRD
&
XFRMR
CALLID
RELAY
TELEPHONE LINE/TELEPHONE HANDSET
SSI
&
BRDGE
OH
RELAY
HANDSET
HYBRID
VOICE
RELAY
CUR
SRC
INTERFACE CIRCUIT
BIAS
SOUNDUCER
(OPTIONAL)
AUDIO/HEADPHONE
INTERFACE CIRCUIT
Figure 1-3. Typical Audio Signal Interface (U.S.)
AMP/
SURG
PROT
RNG
DET
TEL LINE
TEL HANDSET
LCS
MICROPHONE
HEADPHONE
1123F1-3 AIF 3R-US
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Table 1-2. Typical Signal Routing - Voice Mode
+VLS=
Command
0Modem on hook. Phone connected to Line..NoNoYes
1Modem connected to Line.RXA_L1TXA1/2_L1YesYesNo
2Modem connected to HandsetTELIN_L1TELOUT_L1NoYesYes
3Modem connected to Line and HandsetRXA_L1TXAYesNoNo
4Modem connected to SpeakerSPKROUT_MNoNoYes
5Modem connected to Line and SpeakerRXA_L1TXA1/2_L1, SPKROUT_M YesYesNo
6Modem connected to MicrophoneMIC_V.NoNoYes
7Speaker and Mic. routed to Line via Modem RXA_L1, MIC_M TXA1/2_L1, SPKROUT_M YesYesNo
8Modem connected to Speaker.SPKROUT_MNoNoYes
9Modem connected to Line and SpeakerRXA_L1TXA1/2_L1, SPKROUT_M YesYesNo
10Speaker and Mic. routed to Line via Modem RXA_L1, MIC_M TXA1/2_L1, SPKROUT_M YesYesNo
11Modem connected to MicrophoneMIC_V.NoNoYes
12Speaker and Mic. routed to Line via Modem RXA_L1, MIC_M TXA1/2_L1, SPKROUT_M YesYesNo
13Speaker and Mic. routed to Line via Modem RXA_L1, MIC_M TXA1/2_L1, SPKROUT_M YesYesNo
14Modem connected to HeadsetMIC_VSPKROUT_MNoNoYes
15Speaker and Mic. routed to Line via Modem
DescriptionInput SelectedOutput SelectedOH_L1#
RXA_L1, MIC_M TXA1/2_L1, SPKROUT_M
Output
Activated
YesYesNo
VOICE#
Output
Activated
CID_L1#
Output
Activated
Table 1-3. Relay Positions - VoiceView Mode
2-Relay DAA
Off-Hook Relay (OH_L1)
Activated
StageFunction
1On-hookNoNo
2aDetected tone - on-hookNoNo
2bDetected tone - off-hook for handset and speakerphoneYesNo
3Off-hookYesYes
Voice Relay (VOICE#)
Activated
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2. TECHNICAL SPECIFICATIONS
2.1 ESTABLISHING DATA MODEM CONNECTIONS
Dialing
DTMF Dialing.
complies with Bell Publication 47001.
Pulse Dialing.
Blind Dialing.
Modem Handshaking Protocol
If a tone is not detected within the time specified in the S7 register after the last digit is dialed, the modem aborts the call
attempt.
Call Progress Tone Detection
Ringback, equipment busy, and progress tones can be detected in accordance with the applicable standard.
Answer Tone Detection
Answer tone can be detected over the frequency range of 2100 ± 40 Hz in ITU-T modes and 2225 ± 40 Hz in Bell modes.
Ring Detection
A ring signal can be detected from a TTL-compatible square wave input (frequency is country-dependent).
DTMF dialing using DTMF tone pairs is supported in accordance with ITU-T Q.23. The transmit tone level
Pulse dialing is supported in accordance with EIA/TIA-496-A.
The modem can blind dial in the absence of a dial tone if enabled by the X0, X1, or X3 command.
Billing Protection
When the modem goes off-hook to answer an incoming call, both transmission and reception of data are prevented for a
period of time determined by country requirement to allow transmission of the billing signal.
Connection Speeds
Data modem line connection can be selected using the +MS command in accordance with V.25 ter. The +MS command
selects modulation, enables/disables automode, and selects transmit and receive minimum and maximum line speeds.
Automode
Automode detection can be enabled by the +MS command to allow the modem to connect to a remote modem in
accordance with V.25 ter.
2.2 DATA MODE
Data mode exists when a telephone line connection has been established between modems and all handshaking has been
completed.
Speed Buffering (Normal Mode)
Speed buffering allows a DTE to send data to, and receive data from, a modem at a speed different than the line speed. The
modem supports speed buffering at all line speeds.
DTE-to-Modem Flow Control
If the modem-to-line speed is less than the DTE-to-modem speed, the modem supports XOFF/XON or RTS/CTS flow control
with the DTE to ensure data integrity.
Escape Sequence Detection
The “+++” escape sequence can be used to return control to the command mode from the data mode. Escape sequence
detection is disabled by an S2 Register value greater than 127.
GSTN Cleardown (K56flex, V.34, V.32 bis, V.32)
Upon receiving GSTN Cleardown from the remote modem in a non-error correcting mode, the modem cleanly terminates the
call.
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Fall Forward/Fallback (K56flex, V.34/V.32 bis/V.32)
During initial handshake, the modem will fallback to the optimal line connection within K56flex/V.34/V.32 bis/V.32 mode
depending upon signal quality if automode is enabled by the +MS command.
When connected in K56flex/V.34/V.32 bis/V.32 mode, the modem will fall forward or fallback to the optimal line speed within
the current modulation depending upon signal quality if fall forward/fallback is enabled by the %E1 command.
Retrain
The modem may lose synchronization with the received line signal under poor line conditions. If this occurs, retraining may
be initiated to attempt recovery depending on the type of connection.
The modem initiates a retrain if line quality becomes unacceptable if enabled by the %E command. The modem continues to
retrain until an acceptable connection is achieved, or until 30 seconds elapse resulting in line disconnect.
2.3 ERROR CORRECTION AND DATA COMPRESSION
V.42 Error Correction
V.42 supports two methods of error correction: LAPM and, as a fallback, MNP 4. The modem provides a detection and
negotiation technique for determining and establishing the best method of error correction between two modems.
MNP 2-4 Error Correction
MNP 2-4 is a data link protocol that uses error correction algorithms to ensure data integrity. Supporting stream mode, the
modem sends data frames in varying lengths depending on the amount of time between characters coming from the DTE.
V.42 bis Data Compression
V.42 bis data compression mode operates when a LAPM or MNP connection is established.
The V.42 bis data compression employs a “string learning” algorithm in which a string of characters from the DTE is encoded
as a fixed length codeword. Two dictionaries, dynamically updated during normal operation, are used to store the strings.
MNP 5 Data Compression
MNP 5 data compression mode operates during an MNP connection.
In MNP 5, the modem increases its throughput by compressing data into tokens before transmitting it to the remote modem,
and by decompressing encoded received data before sending it to the DTE.
2.4 MNP 10EC™ ENHANCED CELLULAR CONNECTION
A traditional landline modem, when used for high-speed cellular data transmission, typically encounters frequent signal
interference and degradation in the connection due to the characteristics of the analog cellular network. In this case, cellularspecific network impairments, such as non-linear distortion, fading, hand-offs, and high signal-to-noise ratio, contribute to an
unreliable connection and lower data transfer performance. Implementations relying solely on protocol layer methods, such
as MNP 10, generally cannot compensate for the landline modem's degraded cellular channel performance.
The modem achieves higher cellular performance by implementing enhanced cellular connection techniques at both the
physical and protocol layers, depending on modem model. The modem enhances the physical layer within the modulation by
optimizing its responses to sudden changes in the cellular connection. The MNP 10EC protocol layer implemented in the
modem software improves data error identification/correction and maximizes data throughput by dynamically adjusting speed
and packet size based on signal quality and data error performance.
2.5 FAX CLASS 1 OPERATION
Facsimile functions operate in response to fax class 1 commands when +FCLASS=1.
In the fax mode, the on-line behavior of the modem is different from the data (non-fax) mode. After dialing, modem operation
is controlled by fax commands. Some AT commands are still valid but may operate differently than in data modem mode.
Calling tone is generated in accordance with T.30.
2.6 VOICE/AUDIO MODE
Voice and audio functions are supported by the Voice Mode. Voice Mode includes three submodes: Online Voice Command
Mode, Voice Receive Mode, and Voice Transmit Mode.
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2.6.1 Online Voice Command Mode
This mode results from the connection to the telephone line or a voice/audio I/O device (e.g., microphone, speaker, or
handset) through the use of the +FCLASS=8 and +VLS commands. After mode entry, AT commands can be entered without
aborting the connection.
2.6.2 Voice Receive Mode
This mode is entered when the +VRX command is active in order to record voice or audio data input at the RXA_L1 pin,
typically from a microphone/handset or the telephone line.
Received analog voice samples are converted to digital form and compressed for reading by the host. AT commands control
the codec bits-per-sample rate.
Received analog mono audio samples are converted to digital form and formatted into 8-bit unsigned linear or µ-Law PCM
format for reading by the host. AT commands control the bit length and sampling rate. Concurrent DTMF/tone detection is
available.
2.6.3 Voice Transmit Mode
This mode is entered when the +VTX command is active in order to playback voice or audio data to the TXA1_L1 output,
typically to a speaker/handset or to the telephone line. Digitized audio data is converted to analog form then output to the
TXA1_L1 output.
2.6.4 Tone Detectors
The tone detector signal path is separate from the main received signal path thus enabling tone detection to be independent
of the configuration status. In Tone Mode, all three tone detectors are operational.
2.6.5 Speakerphone Modes
Speakerphone modes are selected in voice mode with the following commands:
Speakerphone ON/OFF (+VSP).
Microphone Gain (+VGM)=<gain>.
unsigned octet where values greater than 128 indicate a gain larger than nominal and values smaller than 128 indicate a
gain smaller than nominal.
Speaker Gain (+VGS=<gain>).
octet where values greater than 128 indicate a gain larger than nominal and values smaller than 128 indicate a gain smaller
than normal.
This command turns the Speakerphone function ON (+VSP = 1) or OFF (+VSP = 0).
This command sets the microphone gain of the Speakerphone function. <gain> is an
This command sets the speaker gain of the Speakerphone function. <gain> is an unsigned
2.7 SIMULTANEOUS AUDIO/VOICE AND DATA (AudioSpan)
The modem can operate in AudioSpan Mode if the remote modem is also configured for AudioSpan Mode operation.
AT commands are used to select the AudioSpan Mode, to enable automatic AudioSpan modulation selection or select a
specific AudioSpan modulation, and to enable AudioSpan data burst operation.
V.61 modulation supports 4800 bps data speed with audio, and a data-only speed of 4800 bps.
The AudioSpan audio interface defaults to the local handset connected to the modem and can be configured to interface
through the modem microphone and speaker pins to support use of a headset or a speakerphone.
2.8 HOST-BASED DSVD MODE
Host-based DSVD operation is enabled by the -SSE or -SMS command. In Host-based DSVD Mode, the modem supports
the transfer of data and voice occurs simultaneously during a data connection.
2.9 FULL-DUPLEX SPEAKERPHONE (FDSP) MODE
The modem operates in FDSP mode when +FCLASS=8 and +VSP=1 (see 2.6.5).
In FDSP Mode, speech from a microphone or handset is converted to digital form, shaped, and output to the telephone line
through the line interface circuit. Speech received from the telephone line is shaped, converted to analog form, and output to
the speaker or handset. Shaping includes both acoustic and line echo cancellation.
2.10 VOICEVIEW
Voice and data can be alternately sent and received in a time-multiplexed fashion over the telephone line whenever the
+FCLASS=80 command is active. This command and other VoiceView commands embedded in host communications
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RCV56HCF PCI/CardBus Modem Designer’s Guide
software control modem operation. Most VoiceView commands use an extended syntax starting with the characters "-S",
which signifies the capability to switch between voice and data.
2.11 CALLER ID
Caller ID can be enabled/disabled using the +VCID command. When enabled, caller ID information (date, time, caller code,
and name) can be passed to the DTE in formatted or unformatted form. Inquiry support allows the current caller ID mode
and mode capabilities of the modem to be retrieved from the modem.
2.12 WORLD CLASS COUNTRY SUPPORT
The W-class models include functions which support modem operation in multiple countries. The following capabilities are
provided in addition to the data modem functions previously described. Country dependent parameters are included in the
.INF file for customization by the OEM.
2.12.1 Programmable Parameters
The following parameters are programmable:
•
Dial tone detection levels and frequency ranges.
•
DTMF dialing transmit output level, DTMF signal duration, and DTMF interdigit interval parameters.
•
Pulse dialing parameters such as make/break times, set/clear times, and dial codes.
•
Ring detection frequency range.
•
Blind dialing disable/enable.
•
The maximum, minimum, and default carrier transmit level values.
•
Calling tone, generated in accordance with V.25, may also be disabled.
•
Call progress frequency and tone cadence for busy, ringback, congested, dial tone 1, and dial tone 2.
•
Answer tone detection period.
•
On-hook/off-hook, make/break, and set/clear relay control parameters.
2.12.2 Blacklist Parameters
The modem can operate in accordance with requirements of individual countries to prevent misuse of the network by limiting
repeated calls to the same number when previous call attempts have failed. Call failure can be detected for reasons such as
no dial tone, number busy, no answer, no ringback detected, voice (rather than modem) detected, and key abort (dial
attempt aborted by user). Actions resulting from such failures can include specification of minimum inter-call delay, extended
delay between calls, and maximum numbers of retries before the number is permanently forbidden ("blacklisted"). Up to 20
such numbers may be tabulated. The blacklist parameters are programmable.
2.13 DIAGNOSTICS
2.13.1 Commanded Tests
Diagnostics are performed in response to &T commands per V.54.
Analog Loopback (&T1 Command).
DTE.
Analog Loopback with Self Test (&T8 Command).
is sent to the modem. An error detector within the modem checks for errors in the string of reversals.
Remote Digital Loopback (RDL) (&T6 Command).
data back to the local DTE.
Remote Digital Loopback with Self Test (&T7 Command).
to the remote modem, which loops the data back to the local modem.
Local Digital Loopback (&T3 Command).
in the local modem. Data from the local DTE is looped back to the local DTE (path 1) and data received from the remote
modem is looped back to the remote modem (path 2).
Data from the local DTE is sent to the modem, which loops the data back to the local
An internally generated test pattern of alternating 1s and 0s (reversals)
Data from the local DTE is sent to the remote modem which loops the
An internally generated pattern is sent from the local modem
When local digital loop is requested by the local DTE, two data paths are set up
2.13.2 Power On Reset Tests
Upon power on, an MDP test is performed. If the MDP is not operational, an error indication is generated.
2.14 LOW POWER SLEEP MODE
When not being used, the MDP is placed in a low power state.
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3. HARDWARE INTERFACE
3.1 HARDWARE SIGNAL PINS AND DEFINITIONS
The RCV56HCF (PCI) functional interface signals are shown in Figure 3-1.
The Bus Interface hardware interface signals are shown by major interface in Figure 3-2.
The Bus Interface pin assignments for the 176-pin TQFP are shown Figure 3-3 and are listed Table 3-1.
The Bus Interface hardware interface signals are defined in Table 3-2.
The MDP hardware interface signals are shown by major interface in Figure 3-4.
The MDP pin assignments for the 144-pin TQFP are shown in Figure 3-5 and are listed in Table 3-3.
The MDP hardware interface signals are defined in Table 3-4.
65GNDGGNDGround153RESERVEDI/OIt/Ot12To 3.3V through 47K
66DEVSEL#I/OI/OpstsPCI Bus: DEVSEL#154I/O4I/OIt/Ot12DAA: Reserved
67STOP#I/OI/OpstsPCI Bus: STOP#155I/O3I/OIt/Ot12DAA: Reserved
68PERR#I/OI/OstsPCI Bus: PERR#156I/O2I/OIt/Ot12DAA: Reserved
69SERR#I/OI/OpodPCI Bus: SERR#157I/O1I/OIt/Ot12DAA: Reserved
70VDDPPWRTo 3.3V158I/O0I/OIt/Ot12DAA: Reserved
71GNDGGNDGround159GNDGGNDGround
72PARI/OI/OptsPCI Bus: PAR160RESERVEDI/OIt/Ot12To 3.3V through 47K
73CBE1#I/OI/OptsPCI Bus: CBE1#161RH_L1#OOt12HS: RH
74AD15I/OI/OptsPCI Bus: AD15162ORING_H2OOt12
75AD14I/OI/OptsPCI Bus: AD14163ORING_H1OOt12Ring Output Handset
76VDDPPWRTo 3.3V164MUTE_L1#OOt12DAA: Mute Relay
77GNDGGNDGround165VOICE#OOt12DAA: Voice Relay
78AD13I/OI/OptsPCI Bus: AD13166CID_L1#OOt12DAA: Caller ID Relay
79AD12I/OI/OptsPCI Bus: AD12167OH_L1#OOt12DAA: Off-Hook Relay
80AD11I/OI/OptsPCI Bus: AD11168VDDPPWRTo 3.3V
81AD10I/OI/OptsPCI Bus: AD10169GNDGGNDGround
82GNDGGNDGround170IRING_L1#IItDAA: Ring Indicate
83VDDPPWRTo 3.3V171LCS_L1#IItDAA: Line Current Sense
84AD9I/OI/OptsPCI Bus: AD9172LCS_H1#IItHS: Line Current Sense
85AD8I/OI/OptsPCI Bus: AD8173USED_L1IIt
86CBE0#I/OI/OptsPCI Bus: CBE0#174LCS_H2#IItDAA: Line Current Sense
87GNDGGNDGround175RESERVEDIItTo 3.3V through 47K
88VDDPPWRTo 3.3V176GNDGGNDGround
Notes:
1. I/O types:
I/OpodInput/Output, PCI, open drain (PCI type =o/d)
I/OpstsInput/Output, PCI, sustained tristate (PCI type = s/t/s)
I/OptsInput/Output, PCI, tristate (PCI type = t/s)
IpInput, PCI, totem pole (PCI type = in)
IptsInput, PCI (PCI type = t/s)
ItInput, TTL
It2Input, TTL, 2 mA
ItpdInput, TTL, internal pull-down
It/OtInput, TTL/Output, TTL
It/Ot12Input, TTL/Output, TTL, 12 mA
OpodOutput, PCI, open drain (PCI type =o/d)
OptsOutput, PCI, tristate (PCI type = t/s)
OtOutput, TTL
Ot2Output, TTL, 2 mA
Ot4Output, TTL, 4 mA
Ot12Output, TTL, 12 mA
2. NC = No external connection allowed (may have internal connection).
3. Interface Legend:
MDP = Modem Data Pump
I/O Type
1
InterfacePinSignal LabelI/O
I/O Type
1
Interface
Handset
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Table 3-2. Bus Interface Pin Signal Definitions
LabelI/O TypeSignal Name/Description
SYSTEM
XIN,
XOUT
VDDPWR
GNDGND
CARDBUS#It
VGG1PWR
VIOPWR
PCICLKIp
CLKRUN#Ip,
PCIRST#Ip
AD[31:0]I/Opts
CBE[3:0]#I/Opts
PARI/Opts
FRAME#I/Opsts
IRDY#I/Opsts
TRDY#I/Opsts
STOP#I/Opsts
IDSELIp
DEVSEL#I/Opsts
TRDY#I/Opts
GNT#I/Opts
It
Ot2
(in)
(in, o/d,
s/t/s)
(in)
(t/s)
(t/s)
(t/s)
(s/t/s)
(s/t/s)
(s/t/s)
(s/t/s)
(in)
(s/t/s)
(t/s)
(t/s)
Crystal In and Crystal Out.
Digital Supply Voltage.
Digital Ground.
CardBus Interface Select.
VCC through 1K ohm.
I/O Voltage Tolerance Reference.
I/O Signaling Voltage Source.
PCI Bus Clock.
Clock Running.
to request starting or speeding up CLK. Connect to GND through 1KΩ for PCI designs.
PCI Bus Reset.
signals to a consistent state.
Multiplexed Address and Data.
Bus Command and Bus Enable.
During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase,
C/BE[3:0]# are used as Byte Enables.
Parity.
write data phases; the Bus Interface drives PAR for read data phases.
Cycle Frame.
Initiator Ready.
data phase of the transaction. IRDY# is used in conjunction with TRDY#.
Target Ready.
the transaction. TRDY# is used in conjunction with IRDY#.
STOP# is asserted to indicate the Bus Interface is requesting the master to stop the current
Stop.
transaction.
Initialization Device.
Device Select.
target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been
selected.
Reques
GNT# is used to indicate to the agent that access to the bus has been granted.
Grant.
Connect to digital ground.
The PCICLK (PCI Bus CLK signal) input provides timing for all transactions on PCI.
CLKRUN# is an input used to determine the status of CLK and an open drain output used
PCIRST# (PCI Bus RST# signal) is used to bring PCI-specific registers, sequencers, and
Parity is even parity across AD[31::00] and C/BE[3::0]#. The master drives PAR for address and
FRAME# is driven by the current master to indicate the beginning and duration of an access.
IRDY# is used to indicate the initiating agent’s (bus master’s) ability to complete the current
TRDY# is used to indicate s the Bus Interface’s ability to complete the current data phase of
When actively driven, DEVSEL# indicates the driving device has decoded its address as the
t. TRDY# is used to indicate to the arbiter that this agent desires use of the bus.
Connect XIN and XOUT to a 28.224 MHz external crystal circuit.
Connect to 3.3V.
Selects CardBus (low) or PCI Bus (high) drive strength. For PCI Bus, connect to
Connect to VCC.
Connect to 3.3V.
PCI BUS INTERFACE
Address and Data are multiplexed on the same PCI pins.
Bus Command and Byte Enables are multiplexed on the same PCI pins.
IDSEL input is used as a chip select during configuration read and write transactions.
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Table 3-2. Bus Interface Pin Signal Definitions (Cont’d)
the Special Cycle command, or any other system error where the result will be catastrophic.
Interrupt A.
SERIAL EEPROM INTERFACE (NMC93C56 OR EQUIVALENT)
Serial ROM Shift Clock.
Serial ROM Chip Select.
Serial ROM Instruction, Address, and Data In.
Serial ROM Device Status and Data Out.
Off-Hook Relay Control.
polarity of this output is configurable.
Caller ID Relay Control.
polarity of this output is configurable.
Voice Relay Control.
output is configurable.
Mute Relay Control.
of this output is configurable.
Ring Indicate.
output of an optoisolator or equivalent. The idle state (no ringing) output of the ring detect circuit should be
low.
Line Current Sense.
Remote Hangup.
remote modem/telephone has released the line (gone on-hook).
Extension Offhook.
extension phone.
Line Current Sense Handset 1.
Ring Output Handset 1.
Line Current Sense Handset 2.
Ring Output Handset 2.
Reserved.
PERR# is used for the reporting of data parity errors.
SERR# is an open drain output asserted to report address parity errors, data parity errors on
INTA# is an open drain output asserted to request an interrupt.
Connect to SROM SK input.
Connect to SROM CS input.
Connect to SROM DO output.
Connect to SROM DI input.
DAA INTERFACE
Output (typically active low) used to control the normally open off-hook relay. The
Output (typically active low) used to control the normally open Caller ID relay. The
Output (typically active low) used to control the normally open. The polarity of this
Output (typically active low) used to control the normally open mute relay. The polarity
A high-going edge used to initiate presence of a ring frequency. Typically connected to the
Active low input used to indicate handset off-hook status.
Active low input used to indicate hangup of the remote modem or telephone, i.e. the
Active high input used to indicate the telephone line is in use by the local handset or an
Active low input used to indicate off-hook status from handset 1.
Active high output used to indicate ring signal to handset 1.
Active low input used to indicate off-hook status from handset 2.
Active high output used to indicate ring signal to handset 2.
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Table 3-2. Bus Interface Pin Signal Definitions (Cont’d)
Device Bus Address Lines 0-4.
Device Bus Data Line 0-7.
Device Bus Read Enable.
Device Bus Write Enable.
External Device Active Low Reset.
Wakeup Reset.
MDP Data Pump Chip Select.
MDP Interrupt Request.
MDP IRQ pin.
Modem Clock.
Modem Transmit Clock.
Modem Transmit Data.
Modem Receive Clock.
Modem Receive Data.
SI Frame.
SI Clock.
SI Data Downstream.
SI Data Upstream.
Active low wake input. Connect to the MDP WKRES# pin.
1.I/O types:
IA, IB = Digital input; OA, OB = Digital output (see Table 3-9).
I(DA) = Analog input; O(DD), O(DF) = Analog output (see Table 3-10).
DI = Device interconnect.
2.NC = No external connection allowed (may have internal connection).
3.Interface Legend:
MDP = Modem Data Pump
BIF = Bus Interface Device
ISDN = ISDN U or S/T interface device.
1.536 MHz clock. Connect to BIF SI_CLK pin.
Connect to BIF SI_DD pin.
Connect to BIF SI_DU pin.
MDP TO SIEMENS PSB2186 S/T INTERFACE
8 kHz frame sync; rising edge starts frame. The start of the B1
1.536 MHz clock. Connect to the ISDN device DCL pin.
IOM data input synchronous to IOM_CLK. Connect to the ISDN device DOUT pin.
IOM data output synchronous to IOM_CLK. Connect to the ISDN device DIN pin.
MDP TO SIEMENS PSB21910 U INTERFACE
8 kHz frame sync; rising edge starts frame. The start of the B1
1.536 MHz clock. Connect to the ISDN device DCL pin.
IOM data input synchronous to IOM_CLK. Connect to the ISDN device DOUT pin.
IOM data output synchronous to IOM_CLK. Connect to the ISDN device DIN pin.
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Table 3-4. MDP Signal Definitions (Cont'd)
LabelI/O TypeSignal Name/Description
TELEPHONE LINE/TELEPHONE/AUDIO INTERFACE SIGNALS AND REFERENCE VOLTAGE
TXA1_L1
TXA2_L1
RXA_L1I(DA)
TELOUT_L1O(DF)
TELIN_L1I(DA)
MIC_MI(DA)
MIC_VI(DA)
SPKROUT_MO(DF)
VREFREF
VC_L1REF
PLLVDDPLL
PLLGNDPLL
MK4, MK5IA
SPKMDOA
O(DF)
Transmit Analog 1 and 2.
phase with each other. Each output can drive a 300 Ω load.
Receive Analog.
external hybrid circuit. The input impedance is > 70k Ω.
Telephone Handset Analog Output.
speaker interface circuit. TELOUT_L1 can drive a 300 Ω load.
Telephone Handset Analog Input.
microphone interface circuit. The input impedance is > 70k Ω.
Modem Microphone Input.
Voice Microphone Input.
Modem Speaker Analog Output.
The SPKROUT_M on/off and three levels of attenuation are controlled by bits in DSP RAM. When the speaker
is turned off, the SPKROUT_M output is clamped to the voltage at the VC_L1 pin. The SPKROUT_M output
can drive an impedance as low as 300 ohms. In a typical application, the SPKROUT_M output is an input to
an external LM386 audio power amplifier.
The current and power requirements are listed in Table 3-5.
The absolute maximum ratings are listed in Table 3-6.
Table 3-5. Current and Power Requirements
CurrentPower
Mode
Bus Interface (11229)fIN = 28.224 MHz
Operating
Modem Data Pump (R6776)fIN = 28.224 MHz
Operating5868191245
Sleep1.8—5.9—
Total
MDP Operating
MDP Sleep
Notes:
Operating voltage: VDD = 3.3V ± 0.3V.
Test conditions: VDD = 3.3 VDC for typical values; VDD = 3.6 VDC for maximum values.
Typical
Current (mA)
145186479670
203254670915
147—485—
Maximum
Current (mA)
Typical
Power (mW)
Maximum
Power (mW)Notes
Table 3-6. Maximum Ratings
ParameterSymbolLimitsUnits
Supply VoltageV
Input VoltageV
Operating Temperature RangeT
Storage Temperature RangeT
Analog InputsV
Voltage Applied to Outputs in High Impedance (Off) StateV
DC Input Clamp CurrentI
DC Output Clamp CurrentI
Static Discharge Voltage (25°C)V
Latch-up Current (25°C)I
TRIG
DD
IN
A
STG
IN
HZ
IK
OK
ESD
-0.5 to +4.6V
-0.5 to (VCC +0.5)V
-0 to +70°C
-55 to +125°C
-0.3 to (VAA+ 0.3)V
-0.5 to (VCC + 0.5)V
±20mA
±20mA
±2500V
±400mA
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3.2.2 PCI Bus
Table 3-7 summarizes the PCI DC specifications for 3.3V signaling.
Table 3-8 summarizes the PCI AC specifications for 3.3V signaling.
Table 3-7. PCI Bus DC Specifications for 3.3V Signaling
Equation C: Ioh = (0.98/Vcc) * (Vout - Vcc) * (Vout + 0.4Vcc) for Vcc > Vout > 0.7Vcc.
Equation D: Iol = (256/Vcc) * Vout * (Vcc - Vout) for 0V < Vout < 0.18Vcc.
See PCI Bus Specification for complete details.
A
µ
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3.2.3 MDP
The MDP digital electrical characteristics for the hardware interface signals are listed in Table 3-9.
The MDP analog electrical characteristics for the hardware interface signals are listed in Table 3-10.
Table 3-9. MDP Digital Electrical Characteristics
ParameterSymbolMin.Typ.Max.Units
Input High VoltageV
Type IA2.0–VCC + 0.3
Type IE–4.0–Note 2.
Input High CurrentI
Type IB––40
Input Low VoltageV
Type IA–0.3–0.8
Type IE–1.0–Note 2.
Input Low CurrentI
Input Leakage CurrentI
Output High VoltageV
Type OA2.4––I
Type OB2.4––I
Output Low VoltageV
Type OA––0.4I
Type OB––0.4I
Three-State (Off) CurrentI
Capacitive LoadC
Types IA and ID–10
Type IB–20
Capacitive DriveC
Types OA and OB–10
Circuit Type
Type IATTL
Type IBTTL with pull-up
Type ID~RES
Types OA and OBTTL with 3-state
Notes:
1. Test Conditions:VCC = 3.3V ±0.3V, TA = 0°C to 70°C, (unless otherwise stated).
Output loads: Data bus (D0-D7), address bus (A0-A15), chip selects,
2. Type IE inputs are centered approximately 2.5 V and swing 1.5 V
3. Type OE outputs provide oscillator feedback when operating with an external crystal.
IH
IH
IL
IL
IN
OH
OL
TSI
L
D
DRD#, and DWR# loads = 70 pF + one TTL load.
Other = 50 pF + one TTL load.
––-40µA
PEAK
±2.5µADCVIN = 0 to 3.3V, VCC = 3.6 V
±10µADCVIN = 0 V to VCC
in each direction.
VDC
µAVIN= 3.6 V, VCC = 3.6 V
VDC
VDC
LOAD
LOAD
VDC
LOAD
LOAD
pF
pF
Test Conditions
= – 100 µA
= 0 mA
= 1.6 mA
= 0.8 mA
1
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Table 3-10. Analog Electrical Characteristics
NameTypeCharacteristicValue
RXA_L1,I (DA)Input Impedance> 70K
TELIN_L1AC Input Voltage Range1.1 VP-P**
DC Offset Voltage± 20 mV
* Reference Voltage provided internal to the device.
** Corresponds to 2.2 VP-P at Tip and Ring.
Ω
Ω
Ω
Ω
Ω
Ω
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3.3 INTERFACE TIMING AND WAVEFORMS
3.3.1 PCI Bus Timing
The PCI interface timing conforms to the PCI Local Bus Specification, Production Version, Revision 2.1, June 1, 1995.
3.3.2 Serial EEPROM Timing
The serial EEPROM interface timing is listed in Table 3-11 and is shown in Figure 3-6.
Table 3-11. Timing - Serial EEPROM Interface
SymbolParameterMinTyp.MaxUnitsTest Condition
t
CSS
t
CSH
t
DOS
t
DOH
t
PD0
t
PD1
t
DF
t
SV
t
SKH
t
SKL
Chip select setup400500–ns
Chip select hold400500–ns
Data output setup400500–ns
Data output hold400500–ns
Data input delay––400ns
Data input delay––400ns
Data input disable time––100ns
Status valid––100ns
Clock high500––ns
Clock low500––ns
SROMCS (CS)
SROMCLK (SK)
SROMOUT (DI)
SROMIN (DO) (READ)
SROMIN (DO) (PROGRAM)
t
CSS
t
SKL
t
PD1
t
DOS
t
SV
t
DOH
t
PD0
t
SKH
Figure 3-6. Waveforms - Serial EEPROM Interface
t
CSH
t
DF
t
DF
1123F3-7 EEPROM
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3.3.3 External Device Bus Timing
The external Device Bus timing is listed in Table 3-12 and illustrated in Figure 3-7.
Table 3-12. Timing - External Device Bus Interface
SymbolDescriptionMin.Typ.Max.UnitsTest Conditions
Read
t
AS
t
AH
t
CSS
t
CSH
t
RW
t
RDA
t
RDH
t
AS
t
AH
t
CSS
t
CSH
t
WW
t
WDS
t
RDH
Address setup
Address hold
Chip select setup
Chip select hold
Read pulse width
Read data access
Read data hold
Address setup
Address hold
Chip select setup
Chip select hold
Write pulse width
Write data setup
Write data hold
40
10
40
108–144ns
150––ns
––36ns
0––ns
40
10
40
108–144ns
150––ns
36––ns
36–72ns
––
––
––
Write
––
––
––
ns
ns
ns
ns
ns
ns
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DA0 - DA4
ISDN_CS#
DRD#
DD0-DD7
t
AS
t
CSS
t
AS
t
RDA
t
RW
Read data valid
a. Read
t
AH
t
t
RDH
t
AH
CSH
DA0 - DA4
ISDN_CS#
DWR#
DD0-DD7
t
CSS
t
WW
t
WDS
t
t
WDH
CSH
Write data valid
a. Write
Figure 3-7. Waveforms - External Device Bus Interface
1123F3-8 EB
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3.3.4 IOM-2 Interface
The interface timing is listed in Table 3-13 and shown in Figure 3-8.
Table 3-13. Timing - IOM-2 Interface
SymbolParameterMinTyp.MaxUnitsTest Condition
t
r, tf
t
DCL
t
wH, twL
t
sD
t
hD
t
dF
t
hF
t
dDC
t
dDF
Notes:
1. 768 bps.
Data clock (DCL) and frame
sync (FSC) rise/fall
––30nsC
= 25 pF
L
Data clock period (note 1)565651735nsCL = 25 pF
Data clock pulse width high/low
200310420ns
(note 1)
Data setup32––ns
Data hold32––ns
Frame advance065130nsCL = 25 pF
Frame hold20––nsCL = 25 pF
Data delay clock–20100nsCL = 150 pF
Data delay frame––150nsCL = 150 pF
IOM_CLK (DCL)
IOM_FRAME (FSC)
IOM_DD (DD)
IOM_DU (DU)
IOM_CLK (DCL)
IOM_FRAME (FSC)
IOM_DU (DU)
IOM_DD (DD)
t
dF
t
dDC
Bit NBit 0
t
DCL
t
r
t
wH
t
dDF
t
f
Detail a
t
wL
t
hF
Bit 0
Bit 1Bit 2
t
sD
t
hD
1129
Detail a
Figure 3-8. Waveforms - IOM-2 Interface
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4. DESIGN CONSIDERATIONS
Good engineering practices must be followed when designing a printed circuit board (PCB) containing the modem device.
This is especially important considering the high data bit rate, high fax rate, record/play of analog speech and music audio,
and full-duplex speakerphone operation. Suppression of noise is essential to the proper operation and performance of the
modem and interfacing audio and DAA circuits.
Two aspects of noise in an OEM board design containing the modem device set must be considered: on-board/off-board
generated noise that can affect analog signal levels and analog-to-digital conversion (ADC)/digital-to-analog conversion
(DAC), and on-board generated noise that can radiate off-board. Both on-board and off-board generated noise that is
coupled on-board can affect interfacing signal levels and quality, especially in low level analog signals. Of particular concern
is noise in frequency ranges affecting modem and audio circuit performance.
On-board generated electromagnetic interference (EMI) noise that can be radiated or conducted off-board is a separate, but
equally important, concern. This noise can affect the operation of surrounding equipment. Most local governing agencies
have stringent certification requirements that must be met for use in specific environments. In order to minimize the
contribution of the circuit design and PCB layout to EMI, the designer must understand the major sources of EMI and how to
reduce them to acceptable levels.
Proper PC board layout (component placement and orientation, signal routing, trace thickness and geometry, etc.),
component selection (composition, value, and tolerance), interface connections, and shielding are required for the board
design to achieve desired modem performance and to attain EMI certification. In addition, design layout should meet
requirements stated in the PCI Bus Specification, Section 4.4, Expansion Board Specification, as well as other applicable
sections.
All the aspects of proper engineering practices are beyond the scope of this designer's guide. The designer should consult
noise suppression techniques described in technical publications and journals, electronics and electrical engineering text
books, and component supplier application notes. Seminars addressing noise suppression techniques are often offered by
technical and professional associations as well as component suppliers.
The following guidelines are offered to specifically help achieve stated modem performance, minimize audible noise for audio
circuit use, and to minimize EMI generation.
4.1 PC BOARD LAYOUT GUIDELINES
4.1.1 General Principles
1. Provide separate digital, analog, and DAA sections on the board.
2. Keep digital and analog components and their corresponding traces as separate as possible and confined to defined
sections.
3. Keep high speed digital traces as short as possible.
4. Keep sensitive analog traces as short as possible.
5. Provide proper power supply distribution, grounding, and decoupling.
6. Provide separate digital ground, analog ground, and chassis ground (if appropriate) planes.
7. Provide wide traces for power and critical signals.
8. Position digital circuits near the host bus connection and position the DAA circuits near the telephone line connections.
4.1.2 Component Placement
1. From the system circuit schematic,
a) Identify the digital, analog, and DAA circuits and their components, as well as external signal and power
connections.
b) Identify the digital, analog, mixed digital/analog components within their respective circuits.
c) Note the location of power and signals pins for each device (IC).
2. Roughly position digital, analog, and DAA circuits on separate sections of the board. Keep the digital and analog
components and their corresponding traces as separate as possible and confined to their respective sections on the
board. Typically, the digital circuits will cover one-half of the board, analog circuits will cover one-fourth of the board, and
the DAA will cover one-fourth of the board.
and status signals routed through it. A DAA section is also governed by local government regulations covering subjects
such as component spacing, high voltage suppression, and current limiting.
NOTE:
While the DAA is primarily analog in nature, it also has many control
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3. Once sections have been roughly defined, place the components starting with the connectors and jacks.
a) Allow sufficient clearance around connectors and jacks for mating connectors and plugs.
b) Allow sufficient clearance around components for power and ground traces.
c) Allow sufficient clearance around sockets to allow the use of component extractors.
4. First, place the mixed analog/digital components (e.g., modem device, A/D converter, and D/A converter).
a) Orient the components so pins carrying digital signals extend onto the digital section and pins carrying analog
signals extend onto the analog section as much as possible.
b) Position the components to straddle the border between analog and digital sections.
5. Place all analog components.
a) Place the analog circuitry, including the DAA, on the same area of the PCB.
b) Place the analog components close to and on the side of board containing the TXA1_L1, TXA2_L1, RXA_L1,
VC_L1, and VREF signals.
c) Avoid placing noisy components and traces near TXA1_L1, TXA2_L1, RXA_L1, VC_L1, and VREF lines.
6. Place active digital components/circuits and decoupling capacitors.
a) Place digital components close together in order to minimize signal trace length.
b) Place 0.1 µF decoupling (bypass) capacitors close to the pins (usually power and ground) of the IC they are
decoupling. Make the smallest loop area possible between the capacitor and power/ground pins to reduce EMI.
c) Place host bus interface components close to the edge connector in accordance with the applicable bus interface
standard, e.g., the PCI Bus Specification.
d) Place crystal circuits as close as possible to the devices they drive.
7. Provide a “connector” component, usually a zero ohm resistor or a ferrite bead at one or more points on the PCB to
connect one section’s ground to another.
4.1.3 Signal Routing
1. Route the modem signals to provide maximum isolation between noise sources and noise sensitive inputs. When layout
requirements necessitate routing these signals together, they should be separated by neutral signals. The noise source,
neutral, and noise sensitive pins are listed in Table 4-1.
2. Keep digital signals within the digital section and analog signals within the analog section. (Previous placement of
isolation traces should prevent these traces from straying outside their respective sections.) Route the digital traces
perpendicular to the analog traces to minimize signal cross coupling.
3. Provide isolation traces (usually ground traces) to ensure that analog signals are confined to the analog section and
digital traces remain out of the analog section. A trace may have to be narrowed to route it though a mixed analog/digital
IC, but try to keep the trace continuous.
a) Route an analog isolation ground trace, at least 50 mil to 100 mil wide, around the border of the analog section; put
on both sides of the PCB.
b) Route a digital isolation ground trace, at least 50 mil to 100 mil wide, and 200 mil wide on one side of the PCB
edge, around the border of the digital section.
4. Keep host interface signals (e.g., AEN, IOR#, IOW#, HRESET) traces at least 10 mil thick (preferably 12 - 15 mil).
5. Keep analog signal (e.g., the TXA1_L1, TXA2_L1, RXA_L1, TELIN_L1, TELOUT_L1 , MIC_M, MIC_V, and
SPKROUT_M) traces at least 10 mil thick (preferably 12 - 15 mil).
6. Keep all other signal traces as wide as possible, at least 5 mil (preferably 10 mil).Route the signals between
components by the shortest possible path (the components should have been previously placed to allow this).
7. Route the traces between bypass capacitors to IC pins, at least 25 mil wide; avoid vias if possible.
8. Gather signals that pass between sections (typically low speed control and status signals) together and route them
between sections through a path in the isolation ground traces at one (preferred) or two points only. If the path is made
on one side only, then the isolation trace can be kept contiguous by briefly passing it to the other side of the PCB to
jump over the signal traces.
9. Avoid right angle (90 degree) turns on high frequency traces. Use smoothed radiuses or 45 degree corners.
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10. Minimize the number of through-hole connections (feedthroughs/vias) on traces carrying high frequency signals.
11. Keep all signal traces away from crystal circuits.
12. Distribute high frequency signals continuously on a single trace rather than several traces radiating from one point.
13. Provide adequate clearance (e.g., 60 mil minimum) around feedthroughs in any internal planes in the DAA circuit.
14. Eliminate ground loops, which are unexpected current return paths to the power source.
4.1.4 Power
1. Identify digital power (VDD) and analog power (AVDD) supply connections.
2. Place a 10 µF electrolytic or tantalum capacitor in parallel with a ceramic 0.1 µF capacitor between power and ground at
one or more points in the digital section. Place one set nearest to where power enters the PCB (edge connector or
power connector) and place another set at the furthest distance from where power enters the PCB. These capacitors
help to supply current surge demands by the digital circuits and prevent those surges from generating noise on the
power lines that may affect other circuits.
3. For 2-layer boards, route a 200-mil wide power trace on two edges of the same side of the PCB around the border of
the circuits using the power. (Note that a digital ground trace should likewise be routed on the other side of the board.)
4. Generally, route all power traces before signal traces.
1. In a 2-layer design, provide digital and analog ground plane areas in all unused space around and under digital and
analog circuit components (exclusive of the DAA), respective, on both sides of the board, and connect them such a
manner as to avoid small islands. Connect each ground plane area to like ground plane areas on the same side at
several points and to like ground plane areas on the opposite side through the board at several points. Connect all
modem DGND pins to the digital ground plane area and AGND pins to the analog ground plane area. Typically,
separate the collective digital ground plane area from the collective analog ground plane area by a fairly straight gap.
There should be no inroads of digital ground plane area extending into the analog ground plane area or visa versa.
2. In a 4-layer design, provide separate digital and analog ground planes covering the corresponding digital and analog
circuits (exclusive of the DAA), respectively. Connect all modem DGND pins to the digital ground plane and AGND pins
to the analog ground plane. Typically, separate the digital ground plane from the analog ground plane by a fairly straight
gap.
3. In a design which needs EMI filtering, define an additional “chassis” section adjacent to the bracket end of a plug-in
card. Most EMI components (usually ferrite beads/capacitor combinations) can be positioned in this section. Fill the
unused space with a chassis ground plane, and connect it to the metal card bracket and any connector shields/grounds.
4. Keep the current paths of separate board functions isolated, thereby reducing the current's travel distance. Separate
board functions are: host interface, display, digital (SRAM, EPROM, modem), and DAA. Power and ground for each of
these functions should be separate islands connected together at the power and ground source points only.
5. Connect grounds together at only one point, if possible, using a ferrite bead. Allow other points for grounds to be
connected together if necessary for EMI suppression.
6. Keep all ground traces as wide as possible, at least 25 mil to 50 mil.
7. Keep the traces connecting all decoupling capacitors to power and ground at their respective ICs as short and as direct
(i.e., not going through vias) as possible.
4.1.6 Crystal Circuit
1. Keep all traces and component leads connected to crystal input and output pins (i.e., XTLI and XTLO) short in order to
reduce induced noise levels and minimize any stray capacitance that could affect the crystal oscillator. Keep the XTLO
trace extremely short with no bends greater than 45 degrees and containing no vias since the XTLO pin is connected to
a fast rise time, high current driver.
2. Where a ground plane is not available, such as in a 2-layer design, tie the crystal capacitors ground paths using
separate short traces (as wide as possible) with minimum angles and vias directly to the corresponding device digital
ground pin nearest the crystal pins.
3. Connect crystal cases(s) to ground (if applicable).
4. Place a 100-ohm (typical) resistor between the XTLO pin and the crystal/capacitor node.
5. Connect crystal capacitor ground connections directly to GND pin on the modem device. Do not use common ground
plane or ground trace to route the capacitor GND pin to the corresponding modem GND pin.
4.1.7 VC_L1 and VREF Circuit
1. Provide extremely short, independent paths for VC_L1 and VREF capacitor connections.
a) Route the connection from the plus terminal of the 10 µF VC_L1 capacitor and one terminal of the 0.1 µF VC_L1
capacitor to the modem device VC_L1 pin (pin 24) using a single trace isolated from the trace to the VC_L1 pin
from the VREF capacitors (see step d).
b) Route the connection from the negative terminal of the 10 µF VC_L1 capacitor and the other terminal of a the 0.1
µ
F VC_L1 capacitor to a ferrite bead. The bead should typically have characteristics such as: impedance = 70 Ω at
a frequency of 100 MHz , rated current = 200 mA, and maximum resistance = 0.5 Ω. Connect the other bead
terminal to the AGND pin (pin 34) with a single trace.
c) Route the connection from the plus terminal of the 10 µF VREF capacitor and one terminal of the 0.1 µF VREF
capacitor to the modem device VREF pin (pin 25) with a single trace.
d) Route the connection from the negative terminal of 10 µF VREF capacitor and the other terminal of the 0.1 µF
VREF capacitor to the modem device VC_L1 pin (pin 24) with a single trace isolated from the trace to the VC_L1
pin from the VC_L1 capacitors (see step a).
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4.1.8 Telephone and Local Handset Interface
1. Place common mode chokes in series with Tip and Ring for each connector.
2. Decouple the telephone line cables at the telephone line jacks. Typically, use a combination of series inductors, common
mode chokes, and shunt capacitors. Methods to decouple telephone lines are similar to decoupling power lines,
however, telephone line decoupling may be more difficult and deserves additional attention. A commonly used design
aid is to place footprints for these components and populate as necessary during performance/EMI testing and
certification.
3. Place high voltage filter capacitors (.001 µF @1KV) from Tip and Ring to digital ground.
4.1.9 Optional Configurations
Because fixed requirements of a design may alter EMI performance, guidelines that work in one case may deliver little or no
performance enhancement in another. Initial board design should, therefore, include flexibility to allow evaluation of optional
configurations. These optional configurations may include:
1. Chokes in Tip and Ring lines replaced with jumper wires as a cost reduction if the design has sufficient EMI margin.
2. Various grounding areas connected by tie points (these tie points can be short jumper wires, solder bridges between
close traces, etc.).
3. Develop two designs in parallel; one based on a 2-layer board and the other based on a 4-layer board. During the
evaluation phase, better performance of one design over another may result in quicker time to market.
4.1.10 MDP Specific
1. Locate the MDP device and all supporting analog circuitry, including the data access arrangement, on the same area of
the PCB.
2. Locate the analog components close to and on the side of board containing the TXA1_L1, TXA2_L1, RXA_L1,
TELIN_L1, TELOUT_L1 , MIC_M, MIC_V, and SPKROUT_M signals.
3. Avoid placing noisy components and traces near the TXA1_L1, TXA2_L1, RXA_L1, TELIN_L1, TELOUT_L1 , MIC_M,
MIC_V, and SPKROUT_M lines.
4. Route MDP modem interconnect signals by the shortest possible route avoiding all analog components.
5. Provide an RC network on the AVAA supply in the immediate proximity of the AVAA pin to filter out high frequency noise
above 115 kHz. A tantalum capacitor is recommended (especially in a 2-layer board design) for improved noise
immunity with a current limiting series resistor or inductor to the VCC supply which meets the RC filter frequency
requirements.
6. Provide a 0.1 µF ceramic decoupling capacitor to ground between the high frequency filter and the VAA pin.
7. Provide a 0.1 µF ceramic decoupling capacitor to ground between the VCC supply and the AVDD pin.
4.2 CRYSTAL/OSCILLATOR SPECIFICATIONS
Recommended surface-mount crystal specifications are listed in Table 4-2.
Recommended through-hole crystal specifications are listed in Table 4-3.
4.3 OTHER CONSIDERATIONS
The DAA design described in this designer's guide is a wet DAA, i.e., it requires line current to be present to pass the signal.
Therefore, if the modem is to be connected back-to-back by cable directly to another modem, the modems will not be able to
connect. The DAAs must be modified to operate dry, i.e., without line current, when used in this environment.
A complete schematic is available for the RCV56HCF Data/Fax Modem PCI Half Card Reference Design (TR04-D380).
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Table 4-2. Crystal Specifications - Surface Mount
CharacteristicValue
Rockwell Part No.5333R02-020
Electrical
Frequency28.224 MHz nom.
Frequency Tolerance±50 ppm (CL = 16.5 and 19.5 pF)
Frequency Stability
vs. Temperature±35 ppm (0°C to 70°C)
vs. Aging±15 ppm/4 years
Oscillation ModeFundamental
Calibration ModeParallel resonant
Load Capacitance, C
Shunt Capacitance, C
Series Resistance, R
Drive Level100µW correlation; 300µW max.
Operating Temperature0°C to 70°C
Storage Temperature–40°C to 85°C
Mechanical
Dimensions (L x W x H)7.5 x 5.2 x 1.3 mm max.
MountingSMT
Holder TypeNone
18 pF nom.
L
7 pF max.
O
60 Ω max. @20 nW drive level
1
Suggested Suppliers
KDS America
ILSI America
Vectron Technologies, Inc.
Notes
1. Characteristics @ 25°C unless otherwise noted.
2. Supplier Information:
KDS America
Fountain Valley, CA 92626
(714) 557-7833
ILSI America
Kirkland, WA 98033
(206) 828 - 4886
Vectron Technologies, Inc.
Lowell, NH 03051
(603) 598-0074
Toyocom U.S.A., Inc.
Costa Mesa, CA
(714) 668-9081
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Table 4-3. Crystal Specifications - Through Hole
CharacteristicValue
Rockwell Part No.333R44-011
Electrical
Frequency28.224 MHz nom.
Frequency Tolerance±50 ppm (CL = 16.5 and 19.5 pF)
Frequency Stability
vs. Temperature±30 ppm (0°C to 70°C)
vs. Aging±20 ppm/5 years
Oscillation ModeFundamental
Calibration ModeParallel resonant
Load Capacitance, C
Shunt Capacitance, C
Series Resistance, R
Drive Level100µW correlation; 500µW max.
Operating Temperature0°C to 70°C
Storage Temperature–40°C to 85°C
Mechanical
Dimensions (L x W x H)11.05 x 4.65 x 13.46 mm max.
MountingThrough Hole
Holder TypeHC-49/U
L
1
18 pF nom.
7 pF max.
O
35 Ω max. @20 nW drive level
Suggested Suppliers
KDS America
ILSI America
Vectron Technologies, Inc.
Notes
1. Characteristics @ 25°C unless otherwise noted.
2. Supplier Information:
KDS America
Fountain Valley, CA 92626
(714) 557-7833
ILSI America
Kirkland, WA 98033
(206) 828 - 4886
Vectron Technologies, Inc.
Lowell, NH 03051
(603) 598-0074
Toyocom U.S.A., Inc.
Costa Mesa, CA
(714) 668-9081
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4.4 PACKAGE DIMENSIONS
The package dimensions are shown in Figure 4-1 (144-pin TQFP) and Figure 4-2 (176-pin TQFP) .
D
D1
D2
PIN 1
REF
D
D1
D2
e
b
D1
DETAIL A
0.15
0.75
0.27
0.17
Inches*
Min.
0.0630 MAX
0.0020
0.0059
0.0551 REF
0.8563
0.8760
0.7874 REF
0.6890 REF
0.0197
0.0295
0.0394 REF
0.0197 BSC
0.0067
0.0106
0.0043
0.0067
0.0031 MAX
Max.
Millimeters
Min.
1.6 MAX
0.05
1.4 REF
21.75
20.0 REF
17.5 REF
0.5
1.0 REF
0.50 BSC
0.17
0.11
0.08 MAX
Max.
22.25
Dim.
A
D1
A2
A
c
A1
L
A1
A2
D
D1
D2
L
L1
e
b
c
Coplanarity
Ref: 144-PIN TQFP (GP00-D252)
* Metric values (millimeters) should be used for
PCB layout. English values (inches) are
converted from metric values and may include
round-off errors.
L1
DETAIL A
PD-TQFP-144 (040395)
4-8
Figure 4-1. Package Dimensions - 144-Pin TQFP
ROCKWELL PROPRIETARY INFORMATION
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Figure 4-2. Package Dimensions - 176-Pin TQFP
ROCKWELL PROPRIETARY INFORMATION
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5. SOFTWARE INTERFACE
5.1 PCI Configuration Registers
The PCI Configuration registers are located in the BIF. Table 5-1 identifies the configuration register contents that are
supported in the BIF device:
Table 5-1. PCI Configuration Registers
Bit
Offset
(Hex)
0Device IDVendor ID
4StatusCommand
8Class CodeRevision ID
CNot ImplementedHeader TypeLatency TimerNot Implemented
10Base Address 0 - Memory (BIF)
14Unused Base Address Register
18Unused Base Address Register
1CUnused Base Address Register
20Unused Base Address Register
24Unused Base Address Register
28CIS Pointer
2CSubsystem IDSubsystem Vendor ID
30Not Implemented
34Reserved
38Reserved
3CMax LatencyMin GrantInterrupt PinInterrupt Line
31:2423:1615:87:0
5.1.1 Vendor ID Field
This field is read-only and is loaded from the serial EEPROM after reset events. The default value for the Vendor ID is 127a.
5.1.2 Device ID Field
This field is read-only and is loaded from the serial EEPROM after reset events.
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5.1.3 Command Register
The Command Register bits are described in Table 5-2.
Table 5-2. Command Register
BitDescription
0Controls a device’s response to I/O Space accesses. A value of 0 disables the device response. A value of
1 allows the device to respond to I/O Space accesses. State after RST# is 0.
1Controls a device’s response to Memory Space accesses. A value of 0 disables the device response. A
value of 1 allows the device to respond to Memory Space accesses. State after RST# is 0.
2Controls a device’s ability to act as a master on the PCI bus. A value of 0 disables the device from
generating PCI accesses. A value of 1 allows the device to behave as a bus master. State after RST# is 0.
3Not Implemented.
4Not Implemented.
5Not Implemented.
6This bit controls the device’s response to parity errors. When the bit is set, the device must take its normal
action when a parity error is detected. When the bit is 0, the device must ignore any parity errors that it
detects and continue normal operation. This bit’s state after RST# is 0.
7This bit is used to control whether or not a device does address/data stepping. This bit is read only from the
PCI interface. It is loaded from the serial EEPROM after RST#.
8This bit is an enable bit for the SERR# driver. A value of 0 disables the SERR# driver. A value of 1 enables
the SERR# driver. This bit’s state after RST# is 0.
9This bit controls whether or not a master can do fast back-to-back transactions to different devices. A value
of 1 means the master is allowed to generate fast back-to-back transactions to different agents as described
in Section 3.4.2 of the PCI 2.1 specification. A value of 0 means fast back-to-back transactions are only
allowed to the same agent. This bit’s state after RST# is 0.
10-15Reserved
5.1.4 Status Register
The Status Register bits are described in Table 5-3.
Status register bits may be cleared by writing a ‘1’ in the bit position corresponding to the bit position to be cleared. It is not
possible to set a status register bit by writing from the PCI Bus. Writing a ‘0’ has no effect in any bit position.
Table 5-3. Status Register
BitDescription
0-4Reserved
5Not Implemented.
6Not Implemented.
7Not Implemented.
8This bit is only implemented by bus masters. It is set when three conditions are met: 1) the bus agent
asserted PERR# itself or observed PERR# asserted; 2) the agent setting the bit acted as the bus master for
the operation in which the error occurred; and 3) the Parity Error Response bit (Command Register) is set.
9-10These bits encode the timing of DEVSEL#. These are encoded as 00 for fast, 01 for medium, and 10 for slow
(11 is reserved.) These bits are read-only and must indicate the slowest time that a device asserts DEVSEL#
for any bus command except Configuration Read and Configuration Write.
11Not Implemented.
12This bit must be set by a master device whenever its transaction is terminated with Target-Abort. All master
devices must implement this bit.
13This bit must be set by a master device whenever its transaction (except for Special Cycle) is terminated with
Master-Abort. All master devices must implement this bit.
14This bit must be set whenever the device asserts SERR#. Devices which will never assert SERR# do not
need to implement this bit.
15This bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled
(as controlled by bit 6 in the Command register).
5-2
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5.1.5 Revision ID Field
Initial part hardwired to 00.
5.1.6 Class Code Field
Hardwired to 0x078000 to indicate communications controller.
5.1.7 Latency Timer Register
The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. This
register has 5 read/write bits (MSBs) plus 3 bits of hardwired zero (LSBs). The Latency Timer Register is loaded into the PCI
Latency counter each time FRAME# is asserted to determine how long the master is allowed to retain control of the PCI bus.
This register is loaded by system software. The default value for Latency Timer is 00.
5.1.8 Header Type Field
Hardwired to 00.
5.1.9 CIS Pointer Register
This register points to the CIS memory located in the BIF’s memory space.
5.1.10 Subsystem Vendor ID and Subsystem ID Registers
Subsystem Vendor ID and Subsystem ID are optional registers that are implemented in this design. Both registers are
loaded from the serial EEPROM after RST#.
5.1.11 Interrupt Line Register
The Interrupt Line register is an eight bit register that is read/write. POST software will write the value of this register as it
initializes and configures the system. The value in this register indicates which of the system interrupt controllers the device’s
interrupt pin is connected to.
5.1.12 Interrupt Pin Register
The Interrupt Pin register tells which interrupt pin the device uses. The value of this register will be 0x01, indicating that
INTA# will be used.
5.1.13 Min Grant and Max Latency Registers
The Min Grant and Max Latency registers are used to specify the devices desired settings for Latency Timer values. For
both registers, the value specifies a period of time in units of ¼ microsecond. Min Grant is used for specifying the desired
burst period assuming a 33 MHz clock. Min Latency specifies how often the device needs to gain access to the PCI bus.
These registers are loaded from the serial EEPROM after RST#.
5.2 BASE ADDRESS REGISTER
BIF provides a single Base Address Register. The Base Address Register is a 32 bit register that is used to access the BIF
register set. Bits 3:0 are hard-wired to 0 to indicate memory space. Bits 15-4 will be hard-wired to 0. The remaining bits (31 -
16) will be read/write. This specifies that this device requires a 64k byte address space. After reset, the Base Address
Register contains 0x00000000.
The 64k byte address space used by the BIF is divided into 4k byte regions. Each 4k byte region is used as Table 5-4.
Table 5-4. BIF Address Map
Address
[15:12]
0x00x0-0xfffBASIC2 RegistersBuffers, control, and status registers
0x10x0-0xfffCIS MemoryData loaded from Serial EEPROM for Card Bus applications
0x20x0-0xfffDSP Scratch PadAccess to DSP scratch page registers
0x30x0-0xfffReserved
0x40x0-0xfffReserved
0x5-0xf0x0-0xfffReserved.
Address
[11:0]
Region NameDescription
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5.3 SERIAL EEPROM INTERFACE
The serial EEPROM interface is used to load PCI configuration parameters and CIS information (required for Card Bus
operation) after a reset occurs. The PCI configuration information to be loaded requires 10 bytes of data. The CIS
information requires 384 bytes of data. The minimum serial EEPROM size is 512 bytes (4096 bits). After the PCI reset signal
is negated, the configuration data is read from the serial EEPROM and stored in the PCI configuration registers as required,
then the CIS information is read from the serial EEPROM and stored in the internal RAM of the BIF. While the serial
EEPROM data is being read and is being loaded in the configuration registers and the CIS RAM, any PCI access that occurs
will receive a RETRY signal from the BIF device. After completion of the serial EEPROM reads, the BIF device will accept
PCI transactions.
The data stored in the serial EEPROM is in 16 bit word format. The configuration data to be read from the serial EEPROM is
shown in Table 5-5.
Table 5-5. EEPROM Configuration Data
EEPROM AddressCopied to
0x0Configuration Register Device ID
0x1Configuration Register Vendor ID
0x2Configuration Register Subsystem Device ID
0x3Configuration Register Subsystem Vendor ID
0x4 (LSBs)Configuration Register Min Grant
0x4 (MSBs)Configuration Register Max Latency
Beyond 0x4CIS RAM
5-4
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6. COMMAND SET
The commands for the different models are listed by functional use in Table 6-1and alphanumerically in Table 6-2.
Table 6-1. Command Set Summary - Functional Use Sort
ZReset to Default ConfigurationXXXX
+FCLASSSelect Active Service ClassXXXX
&FSet to Factory-Defined ConfigurationXXXX
IRequest Identification InformationXXXX
+GMIRequest Manufacturer IdentificationXXXX
+GMMRequest Model IdentificationXXXX
+GMRRequest Revision IdentificationXXXX
+GSNRequest Product Serial Number IdentificationXXXX
+GOIRequest Global Object IdentificationXXXX
+GCAPRequest Complete Capabilities ListXXXX
+ESError Control and Synchronous Mode SelectionXXXX
+EBBreak Handling in Error Control operationXXXX
+ESRSelective RepeatXXXX
+EFCS32-bit Frame Check SequenceXXXX
+ERError Control ReportingXXXX
+ETBMCall Termination Buffer ManagementXXXX
1129
ROCKWELL PROPRIETARY INFORMATION
6-1
RCV56HCF PCI/CardBus Modem Designer’s Guide
Table 5-1. Command Set Summary - Functional Use Sort (Cont’d)
+DSData CompressionXXXX
+DRData Compression ReportingXXXX
%EEnable/Disable Line Quality Monitor and Auto-
Retrain
%LLine Signal LevelXXXX
%QLine Signal QualityXXXX
V.8 and V.8 bis
+A8EV.8 and V.8bis Operation ControlXXXX
+A8MSend V.8 Menu SignalsXXXX
+A8TSend V.8bis Signal and/or Message(s)XXXX
Synchronous Mode Access
+ESASynchronous Access Mode ConfigurationXXXX
+ITFTransmit Flow Control ThresholdsXXXX
World-Class
*BDisplay Blacklisted NumbersXXXX
*DDisplay Delayed NumbersXXXX
+GCICountry of InstallationXXXX
DSVD Control
-SSEEnable/Disable DSVDXXXX
Fax Commands
+FAEData/fax Auto AnswerXXXX
+FTSStop Transmission and PauseXXXX
+FRSWait for SilenceXXXX
+FTMTransmit Data with <MOD> CarrierXXXX
+FRMReceive Data with <MOD> CarrierXXXX
+FTHTransmit HDLC Data with <MOD> CarrierXXXX
+FRHReceive HDLC Data with <MOD> CarrierXXXX
+FARAdaptive Reception ControlXXXX
+FCLCarrier Loss TimeoutXXXX
+FDDDouble Escape Character Replacement
Control
+FITDTE Inactivity TimeoutXXXX
+FPRLocal DTE-Modem Serial Port Rate
+FMIManufacturer Identification-XXX
+FMMProduct Identification-XXX
+FMRVersion, Revision, etc.-XXX
+FLOFlow Control-XXX
Retrain
%LLine Signal LevelXXXX
%QLine Signal QualityXXXX
&CRLSD BehaviorXXXX
&DDTR BehaviorXXXX
&FSet to Factory-Defined ConfigurationXXXX
&GSelect Guard ToneXXXX
&PSelect Pulse Dial Make/Break RatioXXXX
&VDisplay Current ConfigurationXXXX
&WStore Current ConfigurationXXXX
*BDisplay Blacklisted NumbersXXXX
*DDisplay Delayed NumbersXXXX
+A8EV.8 and V.8bis Operation ControlXXXX
+A8MSend V.8 Menu SignalsXXXX
+A8TSend V.8bis Signal and/or Message(s)XXXX
+DRData Compression ReportingXXXX
+DSData CompressionXXXX
+EBBreak Handling in Error Control operationXXXX
+EFCS32-bit Frame Check SequenceXXXX
+ERError Control ReportingXXXX
+ESError Control and Synchronous Mode SelectionXXXX
+ESASynchronous Access Mode ConfigurationXXXX
+ESRSelective RepeatXXXX
+ETBMCall Termination Buffer ManagementXXXX
+FAEData/fax Auto AnswerXXXX
+FARAdaptive Reception ControlXXXX
+FCLCarrier Loss TimeoutXXXX
+FCLASSSelect Active Service ClassXXXX
+FDDDouble Escape Character Replacement
Control
+FITDTE Inactivity TimeoutXXXX
+FLOFlow Control-XXX
+FMIManufacturer Identification-XXX
+FMMProduct Identification-XXX
+FMRVersion, Revision, etc.-XXX
+FPRLocal DTE-Modem Serial Port RateXXXX
+FRHReceive HDLC data with <MOD> carrierXXXX
+FRMReceive Data with <MOD> carrierXXXX
+FRSWait for SilenceXXXX
+FTHTransmit HDLC data with <MOD> carrierXXXX
+FTMTransmit Data with <MOD> carrierXXXX
+FTSStop Transmission and PauseXXXX
+GCAPRequest Complete Capabilities ListXXXX
+GCICountry of InstallationXXXX
+GMIRequest Manufacturer IdentificationXXXX
+GMMRequest Model IdentificationXXXX
+GMRRequest Revision IdentificationXXXX
+GOIRequest Global Object IdentificationXXXX
+GSNRequest Product Serial Number IdentificationXXXX
+HEnable/Disable Video Ready ModeXXXX
XXXX
XXXX
Data/Fax/Voice/
Speakerphone/
ISDN
6-4
ROCKWELL PROPRIETARY INFORMATION
1129
RCV56HCF PCI/CardBus Modem Designer’s Guide
Table 5-2. Command Set Summary - Alphanumeric Sort (Cont’d)
Rockwell Semiconductor Systems
5000 Birch Street
Suite 400
Newport Beach, CA 92660
Phone: (714) 222-9119
Fax:(714) 222-0620
US Southwest Satellite Office
Rockwell Semiconductor Systems
1000 Business Center Circle
Suite 215
Thousand Oaks, CA 91320
Phone: (805) 376-0559
Fax:(805) 376-8180
US South Central Office
Rockwell Semiconductor Systems
2001 North Collins Blvd
Suite 103
Richardson, TX 75080
Phone: (214) 379-9310
Fax:(214) 479-9317
US Southeast Office
Rockwell Semiconductor Systems
900 Ashwood Parkway
Suite 400
Atlanta, GA 30338
Phone: (770) 393-1830
Fax:(770) 395-1419
US Southeast Satellite Office
Rockwell Semiconductor Systems
One Prestige Place
2600 McCormick Drive
Suite 350
Clearwater, FL 34619
Phone: (813) 799-8406
Fax:(813) 799-8306
US Northwest Office
Rockwell Semiconductor Systems
US Northwest Office
3600 Pruneridge Avenue
Suite 100
Santa Clara, CA 95051
Phone: (408) 249-9696
Fax:(408) 249-7113
US North Central Office
Rockwell Semiconductor Systems
Two Pierce Place
Chancellory Park
Suite 810
Itasca, IL 60143
Phone: (630) 773-3454
Fax:(630) 773-3907
US Northeast Office
Rockwell Semiconductor Systems
239 Littleton Road
Suite 4A
Westford, MA 01886
Phone: (508) 692-7660
Fax:(508) 692-8185
Australia
Rockwell Semiconductor Systems
Rockwell Australia Pty Limited
Suite 603, 51 Rawson Street
Epping, NSW 2121
Australia
Phone: (61-2) 9869 4088
Fax:(61-2) 9869 4077
Europe Mediterranean
Rockwell Semiconductor Systems
c/o Rockwell Automation S.r.l.
Via Di Vittorio, 1
20017 Mazzo Di Rho (MI)
Italy
Phone: (39 2) 93179911
Fax(39 2) 93179913
Rockwell Semiconductor Systems
S.A.R.L.
Tour GAN
Cedex 13
92082 Paris La Defense 2
France
Phone: (33-1) 49-06-3980
Fax:(33-1) 49-06-3990
Germany
Rockwell Semiconductor Systems
Rockwell Int'l GmbH Germany
Paul-Gerhardt-Allee 50 a
81245 Munchen
Germany
Phone: (49-89) 829-1320
Fax:(49-89) 834-2734
Hong Kong
Rockwell Int'l (Asia Pacific) Ltd.
13th Floor, Suites 8-10,
Harbour Centre
25 Harbour Road
Wanchai,
Hong Kong
Phone: (852) 2 827-0181
Fax:(852) 2 827-6488
Japan
Rockwell Int'l Japan Co., Ltd.
Shimomoto Bldg
1-46-3 Hatsudai, Shibuya-ku
Tokyo, 151
Japan
Phone: (81-3) 5371 1520
Fax:(81-3) 5371 1501
Korea
Rockwell-Collins Int'l, Inc.
Room No. 1508
Korea Textile Centre Building
944-31, Daechi-3dong
Kangnam P.O. Box 2037
Kangnam-ku
Seoul
Korea
Phone: (82-2) 565-2880
Fax:(82-2) 565-1440
Singapore
Rockwell Semiconductor Systems
Singapore Branch
1 Kim Seng Promenade
#09-01 Great World City East Tower
Singapore 237994
Phone: (65) 737-7355
Fax:(65) 737-9077