Harris Semiconductor IP82C55A-5, IP82C55A Datasheet

1

Semiconductor

June 1998

82C55A

CMOS Programmable

Peripheral Interface

Features

• Pin Compatible with NMOS 8255A

• 24 Programmable I/O Pins

• Fully TTL Compatible

• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88

• Direct Bit Set/Reset Capability

• Enhanced Control Word Read Capability

• L7 Process

• 2.5mA Drive Capability on All I/O Ports

• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA

Description

The Harris 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.

Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Harris advanced SAJI process results in performance equal
to or greaterthan existing functionally equivalent products at
a fraction of the power.

Ordering Information

P AR T NUMBERS

P ACKAGE

TEMPERA TURE

RANGE

PKG.

NO.5MHz 8MHz

CP82C55A-5 CP82C55A

40 Ld PDIP

0oC to 70oC E40.6

IP82C55A-5 IP82C55A -40

o

C to 85oC E40.6

CS82C55A-5 CS82C55A

44 Ld PLCC

0

o

C to 70oC N44.65

IS82C55A-5 IS82C55A -40

o

C to 85oC N44.65

CD82C55A-5 CD82C55A

40 Ld
CERDIP

0

o

C to 70oC F40.6

ID82C55A-5 ID82C55A -40

o

C to 85oC F40.6

MD82C55A-5/B MD82C55A/B -55

o

C to 125oC F40.6

8406601QA 8406602QA SMD# F40.6
MR82C55A-5/B MR82C55A/B

44 Pad
CLCC

-55

o

C to 125oC J44.A

8406601XA 8406602XA SMD# J44.A

Pinouts

82C55A (DIP)

TOP VIEW

82C55A (CLCC)

TOP VIEW

82C55A (PLCC)

TOP VIEW

PA3
PA2
PA1
PA0

RD
CS

GND

A1

A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2

PA4
PA5
PA6
PA7
WR
RESE

T

D0
D1
D2
D3
D4
D5
D6
D7
V

CC

PB7
PB6
PB5
PB4
PB3

13

1
2
3
4
5
6
7
8

9
10
11
12

14
15
16
17
18
19
20

28

40
39
38
37
36
35
34
33
32
31
30
29

27
26
25
24
23
22
21

4065 321444342414

9
10
11

8

7

12
13

17

16

15

14

39
38

37
36
35
34
33
32
31
30
29

18 19 20 21 22 23 24 25 26 27 28

GND

NC

A1

A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2

PC3

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

V

CC

NC

NC
RESET
D0
D1
D2
D3
D4
D5
D6
D7
NC

CS

RD

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

WR

CS

GND

A1
A0

PC7

PC6
PC5
PC4
PC0
PC1

PC3

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

NC

NC

RESET
D0
D1
D2
D3

D4
D5
D6
D7
V

CC

RD

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

WR

NC

PC2

NC

44 4342 41 40

39
38
37
36
35
34
33
32
31
30
29

2827

123456

262524232221201918

7
8
9
10
11
12
13
14
15
16
17

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

File Number 2969.2

2

Functional Diagram

Pin Description

SYMBOL

PIN

NUMBER TYPE DESCRIPTION

V

CC

26 VCC: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is

recommended for decoupling.

GND 7 GROUND

D0-D7 27-34 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the

system data bus.

RESET 35 I RESET: A high on this input clears the control register and all ports (A, B, C) are set

to the input mode with the “Bus Hold” circuitry turned on.

CS 6 I CHIP SELECT: Chip selectis an activelowinput used toenable the 82C55Aonto the

Data Bus for CPU communications.

RD 5 I READ: Read is an active low input control signal used by the CPU to read status

information or data via the data bus.

WR 36 I WRITE: Write is an active low input control signal used by the CPU to load control

words and data into the 82C55A.

A0-A1 8, 9 I ADDRESS: These input signals, in conjunction with the RD and WR inputs, control

the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.

PA0-PA7 1-4, 37-40 I/O PORT A: 8-bit inputandoutput port. Bothbushold high and bushold low circuitry are

present on this port.
PB0-PB7 18-25 I/O PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PC0-PC7 10-17 I/O PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.

GROUP A

PORT A

(8)

GROUP A

PORT C

UPPER

(4)

GROUP B

PORT C
LOWER

(4)

GROUP B

PORT B

(8)

GROUP B

CONTROL

GROUP A

CONTROL

DATA BUS

BUFFER

READ

WRITE

CONTROL

LOGIC

RD

WR

A1
A0

RESET

CS

D7-D0

POWER

SUPPLIES

+5V
GND

BI-DIRECTIONAL

DATA BUS

I/O

PA7-PA0

I/O

PC7-PC4

I/O

PC3-PC0

I/O

PB7-PB0

8-BIT

INTERNAL

DATA BUS

82C55A

3

Functional Description

Data Bus Buffer

This three-state bi-directional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status informa­tion are also transferred through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of theControl Groups.

(CS) Chip Select. A “low” on this input pin enables the
communcation between the 82C55A and the CPU.

(RD) Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.

(WR) Write. A “low” on this input pin enables the CPU to
write data or control words into the 82C55A.

(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).

(RESET) Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the 82C55A will hold
the I/O port inputs to a logic “1” state with a maximum hold
current of 400µA.

Group A and Group B Controls

The functional configuration of each port is programmed by
the systems software. In essence, the CPU “outputs” a con­trol word to the 82C55A. The control word contains
information such as “mode”, “bitset”, “bit reset”, etc., that ini­tializes the functional configuration of the 82C55A.

Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.

Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as

shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
“1”, as this implies control word mode information.

82C55A BASIC OPERATION

A1 A0 RD WR CS

INPUT OPERATION

(READ)

00010Port A → Data Bus

01010Port B → Data Bus

10010Port C → Data Bus

11010Control Word → Data Bus

OUTPUT OPERATION

(WRITE)

00100Data Bus → Port A

01100Data Bus → Port B

10100Data Bus → Port C

11100Data Bus → Control

DISABLE FUNCTION

XXXX1Data Bus → Three-State

X X 1 1 0 Data Bus → Three-State

FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUSBUFFER,

READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS

GROUP A

PORT A

(8)

GROUP A

PORT C

UPPER

(4)

GROUP B

PORT C
LOWER

(4)

GROUP B

PORT B

(8)

GROUP B

CONTROL

GROUP A

CONTROL

DAT A

READ

WRITE

CONTROL

LOGIC

RD

WR

A1
A0

RESET

CS

D7-D0

POWER

SUPPLIES

+5V
GND

BI-DIRECTIONAL

DATA BUS

I/O

PA7-

I/O

PC7-

I/O

PC3-

I/O

PB7-

BUFFER

BUS

PB0

PC0

PC4

PA0

8-BIT

INTERNAL

DATA BUS

82C55A

4

Ports A, B, and C

The 82C55A contains three 8-bit ports (A, B, and C). All can
be configured to a wide variety of functional characteristics
by the system software but each has itsown special features
or “personality” to further enhance the power and flexibility of
the 82C55A.

Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus-hold devices
are present on Port A. See Figure 2A.

Port B One 8-bit data input/output latch/buffer and one 8-bit
data input buffer. See Figure 2B.

Port C One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
two 4-bit ports under the mode control. Each 4-bit port con­tains a 4-bit latch and it can be used for the control signal
output and status signal inputs in conjunction with ports A
and B. See Figure 2B.

Operational Description

Mode Selection

There are three basic modes of operation than can be
selected by the system software:

Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-directional Bus

When the reset input goes “high”, all ports will be set to the
input mode with all 24 port lines held at a logic “one” level by
internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional ini­tialization required. This eliminates the need to pullup or pull­down resistors in all-CMOS designs. The control word

register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 82C55A to
service a variety of peripheraldevices with a simple software
maintenance routine. Any port programmed as an output
port is initialized to all zeros when thecontrol word is written.

FIGURE 2A. PORT A BUS-HOLD CONFIGURATION

FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION

FIGURE 2. BUS-HOLD CONFIGURATION

MASTER

RESET

OR MODE

CHANGE

INTERNAL

DATA IN

INTERNAL

DATA OUT

(LATCHED)

EXTERNAL
PORT A PIN

OUTPUT MODE

INPUT MODE

RESET

OR MODE

CHANGE

INTERNAL

DATA IN

INTERNAL

DATA OUT

(LATCHED)

EXTERNAL
PORT B, C

OUTPUT MODE

PIN

P

V

CC

FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE

DATA BUS

8 I/O

B

PB7-PB0

4 I/O

PC3-PC0

4 I/O

C

PC7-PC4

8 I/O

A

PA7-PA0

CONTROL BUS

ADDRESS BUS

RD, WR

82C55A

D7-D0 A0-A1

CS

MODE 0

8 I/O

B

PB7-PB0 CONTROL

C

8 I/O

A

PA7-PA0

MODE 1

OR I/O

CONTROL

OR I/O

8 I/O

B

PB7-PB0

C

BI-

A

PA7-PA0

MODE 2

CONTROL

DIRECTIONAL

FIGURE 4. MODE DEFINITION FORMAT

D7 D6 D5 D4 D3 D2 D1 D0

PORT C (LOWER)
1 = INPUT
0 = OUTPUT

PORT B
1 = INPUT
0 = OUTPUT

MODE SELECTION
0 = MODE 0
1 = MODE 1

GROUP B

PORT C (UPPER)
1 = INPUT
0 = OUTPUT

PORT A
1 = INPUT
0 = OUTPUT

MODE SELECTION
00 = MODE 0
01 = MODE 1

GROUP A

1X = MODE 2

MODE SET FLAG
1 = ACTIVE

CONTROL WORD

82C55A

5

The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display compu­tational results, Group A could be programmed in Mode 1 to
monitor a keyboard or tape reader on an interrupt-driven
basis.

The mode definitions and possible mode combinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal defi­nition vs. PC layout and complete functional flexibility to sup­port almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.

Single Bit Set/Reset Feature (Figure 5)

Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.

When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.

Interrupt Control Functions

When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting or resettingthe associated INTE flip-flop, using the
bit set/reset function of port C.

This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.

INTE Flip-Flop Definition

(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable

NOTE: All Mask flip-flops are automatically reset during mode se­lection and device Reset.

Operating Modes

Mode 0 (Basic Input/Output). This functional configuration

provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply writ­ten to or read from a specific port.

Mode 0 Basic Functional Definitions:

• Two 8-bit ports and two 4-bit ports

• Any Port can be input or output

• Outputs are latched

• Input are not latched

• 16 different Input/Output configurations possible

FIGURE 5. BIT SET/RESET FORMAT

D7 D6 D5 D4 D3 D2 D1 D0

BIT SET/RESET
1 = SET
0 = RESET

BIT SELECT

0

BIT SET/RESET FLAG

CONTROL WORD

DON’T

CARE

XXX

0 = ACTIVE

1234567
01010101
00110011
00001111

B0
B1
B2

MODE 0 PORT DEFINITION

A B GROUP A

#

GROUP B

D4 D3 D1 D0 PORTA

PORTC

(Upper) PORTB

PORTC
(Lower)

0 0 0 0 Output Output 0 Output Output
0 0 0 1 Output Output 1 Output Input
0 0 1 0 Output Output 2 Input Output
0 0 1 1 Output Output 3 Input Input
0 1 0 0 Output Input 4 Output Output
0 1 0 1 Output Input 5 Output Input
0 1 1 0 Output Input 6 Input Output
0 1 1 1 Output Input 7 Input Input
1 0 0 0 Input Output 8 Output Output
1 0 0 1 Input Output 9 Output Input
1 0 1 0 Input Output 10 Input Output
1 0 1 1 Input Output 11 Input Input
1 1 0 0 Input Input 12 Output Output
1 1 0 1 Input Input 13 Output Input
1 1 1 0 Input Input 14 Input Output
1 1 1 1 Input Input 15 Input Input

82C55A

6

Mode 0 (Basic Input)

Mode 0 (Basic Output)

Mode 0 Configurations

CONTROL WORD #0 CONTROL WORD #2

CONTROL WORD #1 CONTROL WORD #3

tRA

tHR

tRR

tIR

tAR

tRD tDF

RD

INPUT

CS, A1, A0

D7-D0

tAW

tWA

tWB

tWW

tWD

tDW

WR

D7-D0

CS, A1, A0

OUTPUT

1

D7

0D60D50D40D30D20D10

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D50D40D30D21D10

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D50D40D30D20D11

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D50D40D30D21D11

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

82C55A

7

CONTROL WORD #4 CONTROL WORD #8

CONTROL WORD #5 CONTROL WORD #9

CONTROL WORD #6 CONTROL WORD #10

CONTROL WORD #7 CONTROL WORD #11

Mode 0 Configurations (Continued)

1D70D60D50D41D30D20D10

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D51D40D30D20D10

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D50D41D30D20D11

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D51D40D30D20D11

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D50D41D30D21D10

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D51D40D30D21D10

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D50D41D30D21D11

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D51D40D30D21D11

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

82C55A

8

Operating Modes

Mode 1 - (Strobed Input/Output). This functional configura-

tion provides a means for transferring I/O data to or from a
specified port in conjunction with strobes or “hand shaking”
signals. In mode 1, port A and port B use the lines on port C
to generate or accept these “hand shaking” signals.

Mode 1 Basic Function Definitions:

• Two Groups (Group A and Group B)

• Each group contains one 8-bit port and one 4-bit
control/data port

• The 8-bit data port can be either input or output. Both
inputs and outputs are latched.

• The 4-bit port is used for control and status of the 8-bit
port.

Input Control Signal Definition

(Figures 6 and 7)

STB (Strobe Input)

A “low” on this input loads data into the input latch.

IBF (Input Buffer Full F/F)

A “high” on this output indicates that the data has been
loaded into the input latch: in essence, and acknowledg­ment. IBF is set by

STB input being low and is reset by the

rising edge of the

RD input.

CONTROL WORD #12 CONTROL WORD #14

CONTROL WORD #13 CONTROL WORD #15

Mode 0 Configurations (Continued)

1D70D60D51D41D30D20D10

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D51D41D30D21D10

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D51D41D30D20D11

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

1D70D60D51D41D30D21D11

D0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

D7 - D0

82C55A

A

B

C

FIGURE 6. MODE 1 INPUT

1D70D61D51D41/0

D3

D2 D1 D0

CONTROL WORD

MODE 1 (PORT A)

PC4

8

IBFAPC5

INTE

A

PA7-PA0

STBA

INTRA

PC3

PC6, PC7

I/O

2

RD

PC6, PC7
1 = INPUT

0 = OUTPUT

1

D7

D6 D5 D4 D3 D2 D1 D0

CONTROL WORD

MODE 1 (PORT B)

PC2

8

IBFBPC1

INTE

B

PB7-PB0

STBB

INTRB

PC0

RD

11

82C55A

9

INTR (Interrupt Request)

A “high” on this output can be used to interrupt the CPU
when and input device is requesting service. INTR is set by
the condition:

STB is a “one”, IBF is a “one” and INTE is a

“one”. It is reset by the falling edge of

RD. This procedure
allows an input device to request service from the CPU by
simply strobing its data into the port.

INTE A

Controlled by bit set/reset of PC4.

INTE B

Controlled by bit set/reset of PC2.

Output Control Signal Definition

(Figure 8 and 9)
OBF - Output Buffer Full F/F). The OBF output will go “low”

to indicate that the CPU has written data out to be specified
port. This does not mean valid data is sent out of the part at
this time since

OBF can go true before data is available.

Data is guaranteed valid at the rising edge of

OBF, (See

Note 1). The

OBF F/F will be set by the rising edge of the

WR input and reset by ACK input being low.
ACK - Acknowledge Input). A “low” on this input informs the

82C55A that the data from Port A or Port B is ready to be
accepted. In essence, a response from the peripheral device
indicating that it is ready to accept data, (See Note 1).

INTR - (Interrupt Request). A “high” on this output can be
used to interrupt the CPU when an output device has
accepted data transmitted by the CPU. INTR is set when
ACK is a “one”, OBF is a “one” and INTE is a “one”. It is
reset by the falling edge of

WR.

INTE A

Controlled by Bit Set/Reset of PC6.

INTE B

Controlled by Bit Set/Reset of PC2.

NOTE:

1. To strobe data into the peripheral device, the user must operate
the strobe line in a hand shaking mode. The user needs to send
OBF to the peripheral device, generates an ACK from the pe­ripheral device and then latch data into the peripheral device on
the rising edge of OBF.

FIGURE 7. MODE 1 (STROBED INPUT)

tST

STB

INTR

RD

INPUT FROM

IBF

PERIPHERAL

tSIB

tSIT

tPH

tPS

tRIT

tRIB

FIGURE 8. MODE 1 OUTPUT

1D70D61D51D41/0

D3

D2 D1 D0

CONTROL WORD

MODE 1 (PORT A)

PC7

8

ACKAPC6

PA7-PA0

OBFA

INTRA

PC3

PC4, PC5

2

WR

PC4, PC5
1 = INPUT

0 = OUTPUT

1

D7

D6 D5 D4 D3 D2 D1 D0

CONTROL WORD

MODE 1 (PORT B)

PC1

8

ACKBPC2

INTE

B

PB7-PB0

OBFB

INTRB

PC0

WR

10

INTE

A

82C55A

10

Operating Modes

Mode 2 (Strobed Bi-Directional Bus I/O)

The functional configuration provides a means for communi­cating with a peripheral device or structure on a single 8-bit
bus for both transmitting and receiving data (bi-directional
bus I/O). “Hand shaking” signals are provided to maintain
proper bus flow discipline similar to Mode 1. Interrupt gener­ation and enable/disable functions are also available.

Mode 2 Basic Functional Definitions:

• Used in Group A only

• One 8-bit, bi-directional bus Port (Port A) and a 5-bit
control Port (Port C)

• Both inputs and outputs are latched

• The 5-bit control port (Port C) is used for control and
status for the 8-bit, bi-directional bus port (Port A)

Bi-Directional Bus I/O Control Signal Definition

(Figures 11, 12, 13, 14)

INTR - (Interrupt Request). A high on this output can be
used to interrupt the CPUfor both input or outputoperations.

Output Operations
OBF - (Output Buffer Full). The OBF output will go “low” to

indicate that the CPU has written data out to port A.
ACK - (Acknowledge). A “low” on this input enables the

three-state output buffer of port A to send out the data. Oth­erwise, the output buffer will be in the high impedance state.

INTE 1 - (The INTE flip-flop associated with

OBF). Con-

trolled by bit set/reset of PC4.

Input Operations
STB - (Strobe Input). A “low” on thisinput loads data into the

input latch.
IBF - (Input Buffer Full F/F). A “high” on this output indicates

that data has been loaded into the input latch.
INTE 2 - (The INTE flip-flop associated with IBF). Controlled

by bit set/reset of PC4.

FIGURE 9. MODE 1 (STROBED OUTPUT)

tWOB

tWB

tAK tAIT

tAOB

tWIT

OBF

WR

INTR

ACK

OUTPUT

Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O
applications.

FIGURE 10. COMBINATIONS OF MODE 1

1D70D61D51D41/0

D3

D2 D1 D0

CONTROL WORD

PORT A - (STROBED INPUT)

PC4

8

OBFB

PA7-PA0

STBA

INTRB

PC0

PC6, PC7

2

WR

PC6, PC7
1 = INPUT

0 = OUTPUT

PORT B - (STROBED OUTPUT)

8

IIBFA

PC5

INTRA

PC3

ACKB

PC2

I/O

PC1

PB7, PB0

RD

10 1

D7

0D61D50D41/0

D3

D2 D1 D0

CONTROL WORD

PORT A - (STROBED OUTPUT)

PC7

8

STBB

PA7-PA0

OBFA

INTRB

PC0

PC4, PC5

2

RD

PC4, PC5
1 = INPUT

0 = OUTPUT

PORT B - (STROBED INPUT)

8

ACKA

PC6

INTRA

PC3

IBFB

PC1

I/O

PC2

PB7, PB0

WR

11

82C55A

11

FIGURE 11. MODE CONTROL WORD FIGURE 12. MODE 2

NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD ÷ OBF •

MASK • ACK • WR)

FIGURE 13. MODE 2 (BI-DIRECTIONAL)

1

D7

D6 D5 D4 D3 D2 D1 D0

CONTROL WORD

1/0 1/01 1/0

PC2-PC0
1 = INPUT
0 = OUTPUT

PORT B
1 = INPUT
0 = OUTPUT

GROUP B MODE
0 = MODE 0
1 = MODE 1

PC7

OBFA

PC6

INTE

PA7-PA0

ACKA

IBFA

PC4

WR

INTE

RD

PC3

PC5

PC2-PC0

1

2

8

STBA

3

I/O

INTRA

tWOB

tAOB

tAK

tAD

tKD

tPH

tPS

tSIB

tST

OBF

WR

INTR

ACK

IBF

STB

PERIPHERAL

BUS

RD

tRIB

DATA FROM

PERIPHERAL TO 82C55A

DATA FROM

82C55A TO PERIPHERAL

DATA FROM

82C55A TO CPU

DATA FROM

CPU TO 82C55A

82C55A

12

MODE 2 AND MODE 0 (INPUT) MODE 2 AND MODE 0 (OUTPUT)

MODE 2 AND MODE 1 (OUTPUT) MODE 2 AND MODE 1 (INPUT)

FIGURE 14. MODE 2 COMBINATIONS

1D71

D6

D5 D4 D3 D2 D1 D0

CONTROL WORD

PC7

8

STBA

PA7-PA0

OBFA

IBFA

PC5

PC2-PC0

3

RD

PC2-PC0
1 = INPUT

0 = OUTPUT

ACKA

PC6

INTRA

PC3

I/O

PC4

PB7-PB0

01

1/0

8

WR

1

D7

1

D6

D5 D4 D3 D2 D1 D0

CONTROL WORD

PC7

8

STBA

PA7-PA0

OBFA

IBFA

PC5

PC2-PC0

3

RD

PC2-PC0
1 = INPUT

0 = OUTPUT

ACKA

PC6

INTRA

PC3

I/O

PC4

PB7, PB0

00

1/0

8

WR

1

D7

1

D6

D5 D4 D3 D2 D1 D0

CONTROL WORD

PC7

8

STBA

PA7-PA0

OBFA

IBFA

PC5

RD

ACKA

PC6

INTRA

PC3

PC4

PB7-PB0

10

8

WR

PC1

OBFB
ACKB

PC2
PC0

INTRB

1

D7

1

D6

D5 D4 D3 D2 D1 D0

CONTROL WORD

PC7

8

STBA

PA7-PA0

OBFA

IBFA

PC5

RD

ACKA

PC6

INTRA

PC3

PC4

PB7-PB0

11

8

WR

PC2

STBB
PC1
PC0

INTRB

IBFB

82C55A

13

Special Mode Combination Considerations

There are several combinations of modes possible. For any
combination, some or all of Port C lines are used for control
or status. The remaining bits are either inputs or outputs as
defined by a “Set Mode” command.

During a read of Port C, the state of all the Port C lines,
except the

ACK and STB lines, will be placed on the data

bus. In place of the

ACK and STB line states, flag status will
appear on the data bus in the PC2, PC4, and PC6 bit
positions as illustrated by Figure 17.

Through a “Write Port C” command, only the Port C pins
programmed as outputs in a Mode 0 group can be written.
No other pins can be affected by a “Write Port C” command,
nor can the interrupt enable flags be accessed. To write to
any Port C output programmed as anoutput in Mode 1 group
or to change an interrupt enable flag, the “Set/Reset Port C
Bit” command must be used.

With a “Set/Reset Port Cea Bit” command, any Port C line
programmed as an output (including IBF and

OBF) can be
written, or an interrupt enable flag can be either set or reset.
Port C lines programmed as inputs, including

ACK and STB
lines, associated with Port C fare not affected by a
“Set/Reset Port C Bit” command. Writing to the correspond­ing Port C bit positions of the

ACK and STB lines with the
“Set Reset Port C Bit” command will affect the Group A and
Group B interrupt enable flags, as illustrated in Figure 17.

Current Drive Capability

Any output on Port A, B or C can sink or source 2.5mA. This
feature allows the 82C55A to directly drive Darlington type
drivers and high-voltage displays that require such sink or
source current.

MODE DEFINITION SUMMARY

MODE 0 MODE 1 MODE 2

IN OUT IN OUT GROUP A ONLY

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

INTRB

IBFB

STBB

INTRA

STBA

IBFA

I/O
I/O

INTRB

OBFB
ACKB

INTRA

I/O

I/O
ACKA
OBFA

I/O
I/O
I/O

INTRA

STBA

IBFA
ACKA
OBFA

Mode 0
or Mode 1
Only

INPUT CONFIGURATION

D7 D6 D5 D4 D3 D2 D1 D0

I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB

OUTPUT CONFIGURATION

D7 D6 D5 D4 D3 D2 D1 D0

OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB

FIGURE 15. MODE 1 STATUS WORD FORMAT

D7 D6 D5 D4 D3 D2 D1 D0

OBFA INTE1 IBFA INTE2 INTRA X X X

(Defined by Mode 0 or Mode 1 Selection)

FIGURE 16. MODE 2 STATUS WORD FORMAT

GROUP A

GROUP B

GROUP A

GROUP B

GROUP A

GROUP B

82C55A

14

Reading Port C Status (Figures 15 and 16)
In Mode 0, Port C transfers data to or from the peripheral

device. When the 82C55A is programmed to function in
Modes 1 or 2, Port C generates or accepts “hand shaking”
signals with the peripheral device. Reading the contents of
Port C allows the programmer to test or verify the “status” of
each peripheral device and change the program flow
accordingly.

There is not special instruction to read the status information
from Port C. A normal read operation of Port C is executed to
perform this function.

Applications of the 82C55A

The 82C55A is a very powerful tool for interfacing peripheral
equipment to the microcomputer system. It represents the
optimum use of available pins and flexible enough to inter­face almost any I/O device without the need for additional
external logic.

Each peripheral device in a microcomputer system usually
has a “service routine” associated with it. The routine
manages the software interface between the device and the
CPU. The functional definitionof the 82C55Ais programmed
by the I/O service routine and becomes an extension of the
system software. By examining the I/O devices interface
characteristics for both data transfer and timing, and
matching this information to the examples and tables in the
detailed operational description, a controlword can easily be
developed to initialize the 82C55A to exactly “fit” the
application. Figures 18 through 24 present a few examples
of typical applications of the 82C55A.

INTERRUPT

ENABLE FLAG POSITION

ALTERNATE PORT C

PIN SIGNAL (MODE)

INTE B PC2 ACKB (Output Mode 1)

or STBB (Input Mode 1)

INTE A2 PC4 STBA (Input Mode 1 or

Mode 2)

INTE A1 PC6 ACKA (Output Mode 1 or

Mode 2)

FIGURE 17. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2

FIGURE 18. PRINTER INTERFACE

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC7
PC6
PC5
PC4

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC1
PC2

DATA READY
ACK
PAPER FEED
FORWARD/REV.

DATA READY
ACK

PAPER FEED
FORWARD/REV.
RIBBON
CARRIAGE SEN.

MODE 1

(OUTPUT)

82C55A

MODE 1

(OUTPUT)

CONTROL LOGIC

AND DRIVERS

INTERRUPT

REQUEST

PC0

INTERRUPT

REQUEST

PC3

HAMMER

RELAYS

HIGH SPEED

PRINTER

82C55A

15

FIGURE 19. KEYBOARD AND DISPLAY INTERFACE

FIGURE 20. KEYBOARDAND TERMINAL ADDRESS

INTERFACE

FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL FIGURE 22. BASIC CRT CONTROLLER INTERFACE

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC4
PC5

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC1
PC2

STROBE
ACK

DATA READY
ACK

MODE 1

(OUTPUT)

82C55A

MODE 1
(INPUT)

FULLY

DECODED

INTERRUPT

REQUEST

INTERRUPT

REQUEST

PC3

PC6
PC7

KEYBOARD

R0
R1
R2
R3
R4
R5
SHIFT
CONTROL

B0
B1
B2
B3
B4
B5
BACKSPACE
CLEAR

BURROUGHS

SELF-SCAN

DISPLAY

BLANKING
CANCEL WORD

STROBE
ACK

FULLY

DECODED

KEYBOARD

R0
R1
R2
R3
R4
R5
SHIFT
CONTROL

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC4
PC5
PC6
PC7

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

MODE 0

(INPUT)

82C55A

MODE 1

(INPUT)

PC3

BUST LT
TEST LT

TERMINAL

ADDRESS

INTERRUPT

REQUEST

PA0
PA1
PA2
PA3
PA4
PA5
PA6

PA7
PC4
PC5
PC6
PC7

PC1

PC2
PC3

PB0
PB1
PB2

PC4
PC5

LSB

STB DATA

MAB

MODE 0
(INPUT)

82C55A

MODE 0

(OUTPUT)

12-BIT

A/D

CONVERTER

(DAC)

PC0

PB3

PC6
PC7

BIT

SET/RESET

SAMPLE EN
STB

LSB

8-BIT

D/A

CONVERTER

(ADC)

ANALOG
INPUT

ANALOG
OUTPUT

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC7
PC6
PC5
PC4

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC2
PC1

MODE 0

(OUTPUT)

82C55A

MODE 1

(OUTPUT)

PC3

DATA READY
ACK

CRT CONTROLLER

• CHARACTER GEN.

INTERRUPT

REQUEST

• REFRESH BUFFER

R0
R1
R2
R3
R4
R5
SHIFT
CONTROL

ROW STB
COLUMN STB
CURSOR H/V STB

CURSOR/ROW/COLUMN

• CURSOR CONTROL

PC0

ADDRESS
H&V

BLANKED
BLACK/WHITE

82C55A

16

FIGURE 23. BASIC FLOPPY DISC INTERFACE FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC4
PC5
PC7
PC6

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC1
PC0

MODE 0

(OUTPUT)

82C55A

MODE 2

PC3

DATA STB
ACK (IN)

FLOPPY DISK

INTERRUPT

REQUEST

D0
D1
D2
D3
D4
D5
D6
D7

TRACK “0” SENSOR
SYNC READY
INDEX

DATA READY
ACK (OUT)

PC2

ENGAGE HEAD
FORWARD/REV.
READ ENABLE
WRITE ENABLE
DISC SELECT
ENABLE CRC
TEST
BUSY LT

CONTROLLER

AND DRIVE

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC4
PC5
PC6

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC1
PC2

MODE 0

(OUTPUT)

82C55A

MODE 1

PC3

STB
ACK

B LEVEL

INTERRUPT

REQUEST

R0
R1
R2
R3
R4
R5
R6
R7

START/STOP
LIMIT SENSOR (H/V)
OUT OF FLUID

STOP/GO

PC0

CHANGE TOOL
LEFT/RIGHT
UP/DOWN
HOR. STEP STROBE
VERT. STEP STROBE
SLEW/STEP
FLUID ENABLE
EMERGENCY STOP

PAPER

TAPE

READER

(INPUT)

MACHINE TOOL

MODE 0
(INPUT)

82C55A

17

Absolute Maximum Ratings T

A

= 25oC Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V

Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC+0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V

Operating Temperature Range

C82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC

I82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

M82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Thermal Resistance (Typical, Note 1) θ

JA

θ

JC

CERDIP Package . . . . . . . . . . . . . . . . 50oC/W 10oC/W

CLCC Package . . . . . . . . . . . . . . . . . . 65oC/W 14oC/W

PDIP Package. . . . . . . . . . . . . . . . . . . 50oC/W N/A

PLCC Package . . . . . . . . . . . . . . . . . . 46oC/W N/A

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Junction Temperature

CDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(PLCC Lead Tips Only)

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications V

CC

= 5.0V ±10%; TA = 0oC to +70oC (C82C55A);

TA = -40oC to +85oC (I82C55A);
TA = -55oC to +125oC (M82C55A)

SYMBOL PARAMETER

LIMITS

UNITS TEST CONDITIONSMIN MAX

V

IH

Logical One Input Voltage 2.0

2.2

- V I82C55A, C82C55A,
M82C55A

V

IL

Logical Zero Input Voltage - 0.8 V

V

OH

Logical One Output Voltage 3.0

VCC -0.4

-VI

OH

= -2.5mA,

IOH = -100µA

V

OL

Logical Zero Output Voltage - 0.4 V IOL +2.5mA

I

I

Input Leakage Current -1.0 +1.0 µAVIN = VCC or GND,

DIP Pins: 5, 6, 8, 9, 35, 36

IO I/O Pin Leakage Current -10 +10 µA VO = VCC or GND DIP Pins: 27 - 34

IBHH Bus Hold High Current -50 -400 µA VO = 3.0V. Ports A, B, C

IBHL Bus Hold Low Current 50 400 µA VO = 1.0V. Port A ONLY

IDAR Darlington Drive Current -2.5 Note 2, 4 mA Ports A, B, C. Test Condition 3
ICCSB Standby Power Supply Current - 10 µAVCC = 5.5V, VIN = VCC or GND. Output Open
ICCOP Operating Power Supply Current - 1 mA/MHz TA = +25oC, VCC = 5.0V, Typical (See Note 3)

NOTES:

2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current.

3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0µs I/O Read/Write cycle time = 1mA).

4. Tested as VOH at -2.5mA.

Capacitance T

A

= 25oC

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

CIN Input Capacitance 10 pF FREQ = 1MHz, All Measurements are

referenced to device GND

CI/O I/O Capacitance 20 pF

82C55A

18

AC Electrical Specifications V

CC

= +5V± 10%, GND = 0V; TA = -55oC to +125oC (M82C55A) (M82C55A-5);

TA = -40oC to +85oC (I82C55A) (I82C55A-5);
TA = 0oC to +70oC (C82C55A) (C82C55A-5)

SYMBOL PARAMETER

82C55A-5 82C55A

UNITS

TEST

CONDITIONSMIN MAX MIN MAX

READ TIMING
(1) tAR Address Stable Before

RD 0-0-ns

(2) tRA Address Stable After

RD 0-0-ns

(3) tRR

RD Pulse Width 250 - 150 - ns

(4) tRD Data Valid From

RD - 200 - 120 ns 1

(5) tDF Data Float After

RD 10 75 10 75 ns 2

(6) tRV Time Between

RDs and/or WRs 300 - 300 - ns
WRITE TIMING
(7) tAW Address Stable Before

WR 0-0-ns

(8) tWA Address Stable After

WR 20 - 20 - ns

(9) tWW

WR Pulse Width 100 - 100 - ns

(10) tDW Data Valid to

WR High 100 - 100 - ns

(11) tWD Data Valid After

WR High 30 - 30 - ns
OTHER TIMING
(12) tWB

WR = 1 to Output - 350 - 350 ns 1

(13) tIR Peripheral Data Before

RD 0-0-ns

(14) tHR Peripheral Data After

RD 0-0-ns
(15) tAK ACK Pulse Width 200 - 200 - ns
(16) tST STB Pulse Width 100 - 100 - ns
(17) tPS Peripheral Data Before STB High 20 - 20 - ns
(18) tPH Peripheral Data After STB High 50 - 50 - ns
(19) tAD ACK = 0 to Output - 175 - 175 ns 1
(20) tKD ACK = 1 to Output Float 20 250 20 250 ns 2
(21) tWOB

WR = 1 to OBF = 0 - 150 - 150 ns 1
(22) tAOB ACK = 0 to OBF = 1 - 150 - 150 ns 1
(23) tSIB STB = 0 to IBF = 1 - 150 - 150 ns 1
(24) tRIB

RD = 1 to IBF = 0 - 150 - 150 ns 1
(25) tRIT

RD = 0 to INTR = 0 - 200 - 200 ns 1
(26) tSIT STB = 1 to INTR = 1 - 150 - 150 ns 1
(27) tAIT ACK = 1 to INTR = 1 - 150 - 150 ns 1
(28) tWIT

WR = 0 to INTR = 0 - 200 - 200 ns 1
(29) tRES Reset Pulse Width 500 - 500 - ns 1, (Note)

NOTE: Period of initial Reset pulse after power-on must be at least 50µsec. Subsequent Reset pulses may be 500ns minimum.

82C55A

19

Timing Waveforms

FIGURE 25. MODE 0 (BASIC INPUT)

FIGURE 26. MODE 0 (BASIC OUTPUT)

FIGURE 27. MODE 1 (STROBED INPUT)

tRA (2)

tHR (14)

tRR (3)

tIR (13)

tAR (1)

tRD (4) tDF (5)

RD

INPUT

CS, A1, A0

D7-D0

tAW (7)

tWA (8)

tWS (12)

tWW (9)

tWD (11)

tDW

WR

D7-D0

CS, A1, A0

OUTPUT

(10)

tST (16)

STB

INTR

RD

INPUT FROM

IBF

PERIPHERAL

tSIB

tSIT

tPH

tPS (17)

tRIT

tRIB (24)

(23)

(26)

(25)

(18)

82C55A

20

FIGURE 28. MODE 1 (STROBED OUTPUT)

FIGURE 29. MODE 2 (BI-DIRECTIONAL)

NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD • OBF •

MASK • ACK • WR)

Timing Waveforms

(Continued)

tWOB (21)

tWB (12)

tAK (15) tAIT (27)

tAOB (22)

tWIT

OBF

WR

INTR

ACK

OUTPUT

(28)

tWOB

tAOB

tAK

tAD (19)

tKD

tPH (18)

tPS (17)

tSIB

tST

OBF

WR

INTR

ACK

IBF

STB

PERIPHERAL

BUS

RD

tRIB (24)

DATA FROM

PERIPHERAL TO 82C55A

DATA FROM

82C55A TO PERIPHERAL

DATA FROM

82C55A TO CPU

DATA FROM

CPU TO 82C55A

(21)

(22)

(15)

(16)

(20)

(23)

(NOTE)

(NOTE)

82C55A

21

AC Test Circuit AC Testing Input, Output Waveforms

Burn-In Circuits

FIGURE 30. WRITE TIMING FIGURE 31. READ TIMING

Timing Waveforms

(Continued)

WR

DAT A

A0-A1,

CS

BUS

tWW (9)

tDW (10) tWD (11)

tWA (8)

tAW (7)

RD

DAT A

A0-A1,

CS

BUS

tRR (3)

tRA (2)

tAR (1)

VALID

(4) tRD

tDF (5)

HIGH IMPEDANCE

R1

V1

OUTPUT FROM

DEVICE UNDER

TEST

NOTE: Includes STRAY and JIG Capacitance

TEST
POINT

C1

R2

(SEE NOTE)

TEST CONDITION DEFINITION TABLE

TEST CONDITION V1 R1 R2 C1

1 1.7V 523Ω Open 150pF
2VCC2kΩ 1.7kΩ 50pF
3 1.5V 750Ω Open 50pF

INPUT

VIH + 0.4V

VIL - 0.4V

1.5V 1.5V

VOH

VOL

OUTPUT

AC Testing: All AC Parameters tested as per test circuits. Input RISE and

FALL times are driven at 1ns/V.

MD82C55A CERDIP

NOTES:

1. VCC = 5.5V ± 0.5V

2. VIH = 4.5V ± 10%

3. VIL = -0.2V to 0.4V

4. GND = 0V

MR82C55A CLCC

NOTES:

1. C1 = 0.01µF minimum

2. All resistors are 47kΩ± 5%

3. f0 = 100kHz ± 10%

4. f1 = f0 ÷ 2; f2 = f1 ÷ 2; . . . ; f15 = f14 ÷ 2

F7
F8

F9
F4
F3

GND

F0
F1

F10

F6
F7
F8
F9

F6
F7
F8
F9

F10

F6

33

34

35

36

37

38

40

32
31
30
29

24

25

26

27

28

21

22

23

13

2
3
4
5
6
7
8

9
10
11
12

14
15
16
17
18
19
20

39

1

F12
F13

F14
F2
F5

F15
F11

F12
F13
F14
F15
F11
F12

V

CC

F13
F14
F15
F11
F12

F11

C1

F10

V

CC

F13

F14

F10

F9

F8

F7

F12

F11

F15

GND

F0

F10

F6
F7

F8
F9

F10

F6

F1

14

13

12

11

10

9

8

7

17

16

15

25

30

35

39
38
37
36

33

34

32
31

29

4

6 3

1

40414243

44

2827262524232221201918

F3F4F9

F8

F12

F13

F14

F2

F5
F15

F12
F13
F14
F15
F11
F12

F11

F11

F6

F7

C1

82C55A

22

Die Characteristics

DIE DIMENSIONS:

95 x 100 x 19 ±1mils

METALLIZATION:

Type: Silicon - Aluminum
Thickness: 11k

Å ±1kÅ

GLASSIVATION:

Type: SiO

2

Thickness: 8kű1kÅ

WORST CASE CURRENT DENSITY:

0.78 x 10

5

A/cm

2

Metallization Mask Layout

82C55A

RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR

CS

GND

A1

A0

PC7

PC6

PC5

PC4

PC0

PC1

PC2 PD3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

V

CC

D7

D6

D5

D4

D3

D2

D1

D0

RESET

82C55A

23

82C55A

Dual-In-Line Plastic Packages (PDIP)

NOTES:

1. Controlling Dimensions: INCH. In caseofconflict between English
and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO SeriesSymbol List” in Section 2.2
of Publication No. 95.

4. Dimensions A, A1 and L are measuredwith the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensionsdonotincludemoldflash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be per­pendicular to datum .

7. eB and eC are measured at the lead tips with the leads uncon­strained. eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will havea B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

e

A

-C-

C

L

E

e

A

C

e

B

e

C

-B-

E1

INDEX

1 2 3 N/2

N

AREA

SEATING

BASE

PLANE

PLANE

-C-

D1

B1

B

e

D

D1

A

A2

L

A1

-A-

0.010 (0.25) C AM BS

E40.6 (JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.250 - 6.35 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.030 0.070 0.77 1.77 8

C 0.008 0.015 0.204 0.381 -

D 1.980 2.095 50.3 53.2 5
D1 0.005 - 0.13 - 5

E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC -

e

A

0.600 BSC 15.24 BSC 6

e

B

- 0.700 - 17.78 7

L 0.115 0.200 2.93 5.08 4

N40 409

Rev. 0 12/93

24

82C55A

Plastic Leaded Chip Carrier Packages (PLCC)

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions
are not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allow­able mold protrusion is 0.010 inch (0.25mm) per side. Dimen­sions D1 and E1 include mold mismatch and are measured at
the extreme material condition at the body parting line.

4. To be measured at seating plane contact point.

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

-C-

A1

A

SEATING
PLANE

0.020 (0.51)
MIN

VIEW “A”

D2/E2

0.025 (0.64)

0.045 (1.14)

R

0.042 (1.07)

0.056 (1.42)

0.050 (1.27) TP

EE1

0.042 (1.07)

0.048 (1.22)
PIN (1) IDENTIFIER

C

L

D1

D

0.020 (0.51) MAX
3 PLCS

0.026 (0.66)

0.032 (0.81)

0.045 (1.14)
MIN

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)
MIN

VIEW “A” TYP.

0.004 (0.10) C

-C-

D2/E2

C

L

N44.65 (JEDEC MS-018AC ISSUE A)

44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

SYM-

BOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.165 0.180 4.20 4.57 -

A1 0.090 0.120 2.29 3.04 -

D 0.685 0.695 17.40 17.65 ­D1 0.650 0.656 16.51 16.66 3
D2 0.291 0.319 7.40 8.10 4, 5

E 0.685 0.695 17.40 17.65 ­E1 0.650 0.656 16.51 16.66 3
E2 0.291 0.319 7.40 8.10 4, 5

N44 446

Rev. 2 11/97

25

82C55A

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

NOTES:

1. Index area: Anotch or a pin one identification markshall be locat­ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, andN/2+1)may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass
overrun.

6. Dimension Q shall be measured from the seating plane to the
base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

bbb C A - B

S

c

Q

L

A

SEATING

BASE

D

PLANE

PLANE

-D-

-A-

-C-

-B-

α

D

E

S1
b2

b

A

e

M

c1

b1

(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

eA/2

A

M

S

S

ccc C A - BMD

S

S

aaa C A - B

M

D

S S

eA

F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)

40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.225 - 5.72 -

b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 ­b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3

D - 2.096 - 53.24 5

E 0.510 0.620 12.95 15.75 5

e 0.100 BSC 2.54 BSC ­eA 0.600 BSC 15.24 BSC -

eA/2 0.300 BSC 7.62 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.070 0.38 1.78 6

S1 0.005 - 0.13 - 7

α

90

o

105

o

90

o

105

o

­aaa - 0.015 - 0.38 ­bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2, 3
N40 408

Rev. 0 4/94

26

82C55A

Ceramic Leadless Chip Carrier Packages (CLCC)

D

j x 45

o

D3

B

h x 45

o

A

A1

E

L

L3

e

B3

L1

D2

D1

e1

E2

E1

L2

PLANE 2

PLANE 1

E3

B2

0.010 E HS S

0.010 E FSS

-E-

0.007 E FM S HS

B1

-H-

-F-

J44.A MIL-STD-1835 CQCC1-N44 (C-5)

44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.064 0.120 1.63 3.05 6, 7

A1 0.054 0.088 1.37 2.24 -

B 0.033 0.039 0.84 0.99 4
B1 0.022 0.028 0.56 0.71 2, 4
B2 0.072 REF 1.83 REF ­B3 0.006 0.022 0.15 0.56 -

D 0.640 0.662 16.26 16.81 ­D1 0.500 BSC 12.70 BSC ­D2 0.250 BSC 6.35 BSC ­D3 - 0.662 - 16.81 2

E 0.640 0.662 16.26 16.81 ­E1 0.500 BSC 12.70 BSC ­E2 0.250 BSC 6.35 BSC ­E3 - 0.662 - 16.81 2

e 0.050 BSC 1.27 BSC ­e1 0.015 - 0.38 - 2

h 0.040 REF 1.02 REF 5

j 0.020 REF 0.51 REF 5

L 0.045 0.055 1.14 1.40 ­L1 0.045 0.055 1.14 1.40 ­L2 0.075 0.095 1.90 2.41 ­L3 0.003 0.015 0.08 0.38 -

ND 11 11 3
NE 11 11 3

N44 443

Rev. 0 5/18/94

NOTES:

1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.

2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)

3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.

4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.

5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.

6. Chip carriers shall be constructed of a minimum of two ceramic
layers.

7. Dimension “A” controls the overall package thickness. The maxi­mum “A” dimension is package height before being solder dipped.

8. Dimensioning and tolerancing per ANSI Y14.5M-1982.

9. Controlling dimension: INCH.