Harris Semiconductor CA3160T, CA3160E, CA3160AE Datasheet

Semiconductor

CA3160, CA3160A

September 1998 File Number 976.3

4MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output

The CA3160A and CA3160 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip.TheCA3160seriesare
frequency compensated versions of the popular CA3130
series.

Gate protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field effect transistors in the
input stage results in common-mode input voltage capability
down to 0.5V below the negative supply terminal, an
important attribute in single supply applications.

A complementary symmetry MOS (CMOS) transistor-pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.

The CA3160 Series circuits operate at supply voltages
ranging from 5V to 16V, or ±2.5V to ±8V when using split
supplies, and have terminals for adjustment of offset voltage
for applications requiring offset null capability. Terminal
provisions are also made to permit strobing of the output
stage.

The CA3160A offers superior input characteristics over
those of the CA3160.

Ordering Information

TEMP.

PART NUMBER

CA3160AE -55 to 125 8 Ld PDIP E8.3
CA3160E -55 to 125 8 Ld PDIP E8.3
CA3160T -55 to 125 8 Pin Metal Can T8.C

RANGE (oC) PACKAGE

PKG.

NO.

Features

• MOSFET Input Stage Provides:

- Very High Z

- Very Low I

= 1.5TΩ (1.5 x 1012Ω) (Typ)

I

. . . . . . . . . . . . . 5pA (Typ) at 15V Operation

I

. . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) at 5V Operation

• Common-Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can Be Swung

0.5V Below Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either (or
Both) Supply Rails

Applications

• Ground Referenced Single Supply Amplifiers

• Fast Sample Hold Amplifiers

• Long Duration Timers/Monostables

• High Input Impedance Wideband Amplifiers

• Voltage Followers (e.g., Follower for Single Supply
D/A Converter)

• Wien-Bridge Oscillators

• Voltage Controlled Oscillators

• Photo Diode Sensor Amplifiers

Pinouts

CA3160

(METAL CAN)

TOP VIEW

COMPENSATION

OFFSET

NULL

INV.

INPUT

NON-INV.

INPUT

1

2

3

CA3160

TOP VIEW

TAB

8

-

+

4
V- AND CASE

(PDIP)

STROBESUPPLEMENTARY

7

5

V+

OUTPUT

6

OFFSET
NULL

OFFSET NULL

NON-INV.

NOTE: CA3160 Series devices have an on-chip frequency
compensation network. Supplementary phase compensation or
frequency roll-off (if desired) can be connected externally between
Terminals 1 and 8.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

INV.

INPUT

INPUT

1
2

-

+

3

V-

4

8

STROBE

7

V+

6

OUTPUT

5

OFFSET NULL

© Harris Corporation 1998

Copyright

CA3160, CA3160A

Absolute Maximum Ratings Thermal Information

Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . +16V

Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .8V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)

Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA

Output Short Circuit Duration (Note 2). . . . . . . . . . . . . . . . Indefinite

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

2. Short Circuit may be applied to ground or to either supply.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . 110 N/A

Metal Can Package . . . . . . . . . . . . . . . 170 85

Maximum Junction Temperature (Metal Can). . . . . . . . . . . . . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

Electrical Specifications T

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage |VIO|VS = ±7.5V - 6 15 - 2 5 mV
Input Offset Current |IIO|VS = ±7.5V - 0.5 30 - 0.5 20 pA
Input Current I
Large-Signal Voltage Gain A

Common-Mode Rejection Ratio CMRR 70 90 - 80 95 - dB
Common-Mode Input-Voltage Range V
Power-Supply Rejection Ratio PSRR ∆VIO/∆VS, VS = ±7.5V - 32 320 - 32 150 µV/V
Maximum Output Voltage VOM+RL = 2kΩ 12 13.3 - 12 13.3 - V

Maximum Output Current IOM+VO = 0V (Source) 12 22 45 12 22 45 mA

Supply Current (Note 3) I+ VO = 7.5V, R L = ∞ - 10 15 - 10 15 mA

Input Offset Voltage Temperature Drift ∆VIO/∆T-8--6-µV/oC

= 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

A

CA3160 CA3160A

VS = ±7.5V - 5 50 - 5 30 pA

I

VO = 10V

OL

lCR

VOM- - 0.002 0.01 - 0.002 0.01 V
VOM+RL = ∞ 14.99 15 - 14.99 15 - V
VOM- - 0 0.01 - 0 0.01 V

IOM-VO = 15V (Sink) 12 20 45 12 20 45 mA

VO = 0V, R L = ∞ -23-23mA

, RL = 2kΩ 50 320 - 50 320 - kV/V

P-P

94 110 - 94 110 - dB

0 -0.5 to 12 10 0 -0.5 to 12 10 V

UNITSMIN TYP MAX MIN TYP MAX

Electrical Specifications For Design Guidance, V

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or

Input Resistance R
Input Capacitance C
Equivalent Input Noise Voltage e

Equivalent Input Noise Voltage e

= ±7.5V, TA = 25oC, Unless Otherwise Specified

SUPPLY

Terminals 4 and 1

I

f = 1MHz 4.3 4.3 pF

I

BW = 0.2MHz RS = 1MΩ 40 40 µV

N

RS = 10MΩ 50 50 µV

RS = 100Ω 1kHz 72 72 nV/√Hz

N

10kHz 30 30 nV/√Hz

2

CA3160 CA3160A

UNITSTYP TYP

±22 ±22 mV

1.5 1.5 TΩ

CA3160, CA3160A

Electrical Specifications For Design Guidance, V

= ±7.5V, TA = 25oC, Unless Otherwise Specified (Continued)

SUPPLY

CA3160 CA3160A

PARAMETER SYMBOL TEST CONDITIONS

Unity Gain Crossover Frequency f

T

4 4 MHz

UNITSTYP TYP

Slew Rate SR 10 10 V/µs
Transient Response Rise and Fall Time t

CL = 25pF, RL = 2kΩ, (Voltage Follower) 0.09 0.09 µs

r

Overshoot OS 10 10 %

Settling Time t

Electrical Specifications For Design Guidance, V+ = +5V, V- = 0V, T

CL= 25pF, RL=2kΩ, (Voltage F ollow er)

S

To <0.1%, VIN = 4V

A

P-P

= 25oC, Unless Otherwise Specified

1.8 1.8 µs

CA3160 CA3160A

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage V
Input Offset Current I
Input Current I

IO

IO

l

62mV

0.1 0.1 pA
22pA

UNITSTYP TYP

Common-Mode Rejection Ratio CMRR 80 90 dB
Large Signal Voltage Gain A

OL

VO = 4V

, RL = 5kΩ 100 100 kV/V

P-P

100 100 dB

Common-Mode Input Voltage Range V

lCR

0 to 2.8 0 to 2.8 V

Supply Current I+ VO = 5V, RL = ∞ 300 300 µA

VO = 2.5V, RL = ∞ 500 500 µA

Power Supply Rejection Ratio PSRR ∆VIO/∆V+ 200 200 µV/V

NOTE:

3. ICC typically increases by 1.5mA/MHz during operation.

Block Diagram

+

3

INPUT

2

-

OFFSET

NULL

200µA 1.35mA 200µA

BIAS CKT.

A

≈

A

≈5X

V

COMPENSATION

(WHEN DESIRED)

V

6000X

C

C

7

8mA
(NOTE 4)

0mA
(NOTE 5)

V+

NOTES:

4. Totalsupply voltage (for indicated voltage
gains) = 15V with input terminals biased so
that Terminal 6 potential is +7.5V above
Terminal 4.

5. Total supply voltage (for indicated voltage
gains) = 15V with output terminal driven to
either supply rail.

OUTPUT

A

≈30X

V

815

STROBE

6

V-

4

3

Schematic Diagram

BIAS CURRENT “CURRENT SOURCE

CA3160, CA3160A

CURRENT SOURCE

FOR Q

AND Q

6

7

LOAD” FOR Q

V+

7

11

Q

Z

1

8.3V

R

1

40kΩ

R

5kΩ

NON-INV.

INPUT

INV. INPUT

2kΩ

30
pF

Q

Q

3

Q

5

OUTPUT
STAGE

11

Q

Q

12

STROBING

8

OUTPUT

6

4815

Q

1

D

1

D

2

D

3

D

4

2

INPUT STAGE

D

5

3

+

2

-

R

1kΩ

1kΩ

2

Q

4

Q

6

3

Q

9

R

5

OFFSET NULL

SECOND
STAGE

7

SUPPLEMENTARY
COMP IF DESIRED

Q

R

4

1kΩ

10

R
1kΩ

D

6

D

6

Q

7

NOTE: Diodes D5 Through D7 Provide Gate Oxide Protection For MOSFET Input Stage.

Application Information

Circuit Description

Refer to the Block Diagram of the CA3160 series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3160 series circuits are
ideal for single supply operation. Three class A amplifier
stages, having the individual gain capability and current
consumption shown in the Block Diagram provide the total
gain of the CA3160. A biasing circuit provides two potentials
for common use in the first and second stages. Terminals 8
and 1 can be used to supplement the internal phase
compensation network if additional phase compensation or
frequency roll-off is desired. Terminals 8 and 4 can also be
used to strobe the output stage into a low quiescent current
state. When Terminal 8 is tied to the negative supply rail
(Terminal 4) by mechanical or electrical means, the output
potential at Terminal 6 essentially rises to the positive supply­rail potential at Terminal 7. This condition of essentially zero
current drain in the output stage under the strobed “OFF”
condition can only be achieved when the ohmic load

resistance presented to the amplifier is very high (e.g., when
the amplifier output is used to drive MOS digital circuits in
comparator applications).

Input Stage - The circuit of the CA3160 is shown in the
Schematic Diagram. It consists of a differential-input stage
using PMOS field-effect transistors (Q
mirror-pair of bipolar transistors (Q
resistors together with resistors R

, Q7) working into a

6

) functioning as load

9,Q10

through R6. The mirror-

3

pair transistors also function as a differential-to-single-ended
converter to provide base drive to the second-stage bipolar
transistor (Q

). Offset nulling, when desired, can be effected

11

by connecting a 100,000Ω potentiometer across Terminals 1
and 5 and the potentiometer slider arm to Terminal 4.
Cascode-connected PMOS transistors Q

, Q4, are the

2

constant-current source for the input stage. The biasing circuit
for the constant-current source is subsequently described.
The small diodes D

through D7provide gate-oxide protection

5

against high-voltage transients, including static electricity
during handling for Q

and Q7.

6

Second-Stage - Most of the voltage gain in the CA3160 is
provided by the second amplifier stage, consisting of bipolar

4

CA3160, CA3160A

transistor Q11 and its cascode-connected load resistance
provided by PMOS transistors Q

and Q5. The source of bias

3

potentials for these PMOS transistors is described later. Miller
Effectcompensation (roll off) is accomplished bymeans of the
30pF capacitor and 2kΩ resistor connected between the base
and collector of transistor Q

. These internal components

11

provide sufficient compensation for unity gain operation in
most applications. However, additional compensation, if
desired, may be used between Terminals 1 and 8.

Bias-Source Circuit - At total supply voltages , some what
above8.3V, resistor R

and zener diode Z1serve to establish a

2

voltage of 8.3V across the series-connected circuit, consisting
of resistor R
A tap at the junction of resistor R
gate-bias potential of about 4.5V for PMOS transistors Q
Q

with respect to Terminal 7. A potential of about 2.2V is

5

developed across diode-connected PMOS transistor Q

, diodes D1through D4, and PMOS transistor Q1.

1

and diode D4 provides a

1

with

1

4

and

respect to Terminal 7 to provide gate bias for PMOS transistors
Q

and Q3. It should be noted that Q1 is “mirror-connected” to

2

both Q
be identical, the approximately 200µA current in Q
a similar current in Q

and Q3. Since transistors Q1, Q2, Q3 are designed to

2

and Q3 as constant-current sources for

2

establishes

1

both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V,zener diode

Z

becomes nonconductive and the potential, dev eloped

1

across series-connected R

, D1 - D4, and Q1, varies directly

1

with variations in supply voltage. Consequently, the gate bias
for Q

, Q5 and Q2, Q3 varies in accordance with supply-

4

voltage variations. This variation results in deterioration of the
power-supply-rejection ratio (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about

4.5V results in seriously degraded performance.
Output Stage - The output stage consists of a drain-loaded

inverting amplifier using CMOS transistors operating in the
Class A mode. When operating into very high resistance loads,
the output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier,its gain is
dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 17. Typical op amp
loads are readily driven by the output stage. Because large­signal excursions are non-linear , requiring feedbac k for good
wavef orm reproduction, transient dela ys may be encountered.
As a voltage follower,the amplifier can achieve0.01% accuracy
levels, including the negativ e supply r ail.

Offset Nulling

Offset-voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
potentiometer's total range.

Input Current Variation with Common Mode Input
Voltage

As shown in the Electrical Specifications, the input current for
the CA3160 Series Op Amps is typically 5pA at T

= 25oC

A

when Terminals 2 and 3 are at a common-mode potential of
+7.5V with respect to negative supply Terminal 4. Figure 23
contains data showing the variation of input current as a
function of common-mode input voltage at T

=25oC. These

A

data show that circuit designers can advantageously exploit
these characteristics to design circuits which typically require
an input current of less than 1pA, provided the common-mode
input voltage does not exceed 2V. As previously noted, the
input current is essentially the result of the leakage current
through the gate-protection diodes in the input circuit and,
therefore, a function of the applied voltage . Although the finite
resistance of the glass terminal-to-case insulator of the metal
can package also contributes an increment of leakage current,
there are useful compensating factors. Because the gate­protection network functions as if it is connected to Terminal 4
potential, and the metal can case of the CA3160 is also
internally tied to T erminal 4, input Terminal 3 is essentially
“guarded” from spurious leakage currents.

Input-Current Variation with Temperature

The input current of the CA3160 Series circuits is typically 5pA

o

at 25

C. The major portion of this input current is due to
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor junction device,including op
amps with a junction-FET input stage, the leakage current
approximately doubles for every 10

o

C increase in temperature.
Figure 24 provides data on the typical variation of input bias
current as a function of temperature in the CA3160.

In applications requiring the lowest practical input current and
incremental increases in current because of “warm-up” effects,
it is suggested that an appropriate heat sink be used with the
CA3160. In addition, when “sinking” or “sourcing” significant
output current the chip temperature increases, causing an
increase in the input current. In such cases, heat-sinking can
also very markedly reduce and stabilize input current variations.

Input Offset Voltage (VIO) Variation with DC Bias
vs Device Operating Life

It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magnitude
of the change is increased at high temperatures. Users of the
CA3160 should be alert to the possible impacts of this effect if
the application of the device involves extended operation at
high temperatures with a significant differential DC bias voltage
applied across Terminals 2 and 3. Figure 25 shows typical data
pertinent to shifts in offset voltage encountered with CA3160
devices in metal can packages during life testing. At lo wer
temperatures (metal can and plastic) for example at 85
change in voltage is considerably less. In typical linear
applications where the differential voltage is small and
symmetrical, these incremental changes are of about the same

o

C, this

5

CA3160, CA3160A

magnitude as those encountered in an operational amplifier
employing a bipolar transistor input stage. The 2V diff erential
voltage example represents conditions when the amplifier
output state is “toggled”, e.g., as in comparator applications.

Power Supply Considerations

Because the CA3160 is very useful in single supply
applications, it is pertinent to review some considerations
relating to power supply current consumption under both
single and dual supply service. Figures 1A and 1B show the
CA3160 connected for both dual and single supply operation.

Dual-supply operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q
increasingly positive with respect to ground, current flow
through Q

(from the negative supply) to the load is

12

increased and current flow through Q
supply) decreases correspondingly.When the gate terminals
of Q

and Q12 are driven increasingly negative with respect

8

to ground, current flow through Q
flow through Q

is decreased accordingly.

12

Single supply operation: Initially, let it be assumed that the
value of R

is very high (or disconnected), and that the input-

L

terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2, i.e., the voltage-drops
across Q

and Q12are of equal magnitude. Figure 18 shows

8

typical quiescent supply-current vs supply voltage for the
CA3160 operated under these conditions.

Since the output stage is operating as a Class A amplifier, the
supply current will remain constant under dynamic operating
conditions as long as the transistors are operated in the linear
portion of their voltage-transfer characteristics (see Figure 17).
If either Q

or Q12 are swung out of their linear regions toward

8

cutoff (a non-linear region), there will be a corresponding
reduction in supply-current. In the extreme case, e.g., with
Terminal 8 swung down to ground potential (or tied to ground),
NMOS transistor Q

is completely cut off and the supply

12

current to series connected transistors Q
essentially to zero. The two preceding stages in the CA3160,
howev er, continue to draw modest supply-current (see the
lower curve in Figure 18) ev en though the output stage is
strobed off. Figure 1A shows a dual-supply arrangement for the
output stage that can also be strobed off, assuming R
pulling the potential of Terminal 8 down to that of Terminal 4.

Let it now-be assumed that a load resistance of nominal value
(e.g., 2kΩ) is connected between Terminal 6 and ground in the
circuit of Figure 1B. Let it further be assumed again that the
input-terminal bias (T erminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2. Since PMOS transistor Q
must now supply quiescent current to both RL and transistor
Q

, it should be apparent that under these conditions the

12

supply current must increase as an inverse function of the R
magnitude. Figure 20 shows the voltage-drop across PMOS
transistor Q

as a function of load current at several supply

8

and Q12 are driven

8

(from the positive

8

is increased and current

8

, Q12 goes

8

= ∞, by

L

8

L

voltages.Figure 17 shows the voltagetransfercharacteristics of
the output stage for sev eral values of load resistance.

Wideband Noise

Fromthe standpoint of low-noise performance considerations,
the use of the CA3160 is most advantageous in applications
where in the source resistance of the input signal is on the
order of 1MΩ or more. In this case, the total input-referred
noise voltage is typically only 40µV when the test circuit
amplifier of Figure 2 is operated at a total supply voltage of
15V. This value of total input-referred noise remains
essentially constant, even though the v alue of source
resistance is raised by an order of magnitude. This
characteristic is due to the fact that reactance of the input
capacitance becomes a significant factor in shunting the
source resistance. It should be noted, however, that for values
of source resistance very much greater than 1MΩ, the total
noise voltage generated can be dominated by the thermal
noise contributions of both the feedback and source resistors.

7

3

2

FIGURE 1A. DUAL POWER SUPPLY OPERATION

3

2

FIGURE 1B. SINGLE POWER SUPPLY OPERATION

FIGURE 1. CA3160 OUTPUT STAGE IN DUAL AND SINGLE

+

CA3160

-

8

+

CA3160

-

8

POWER SUPPLY OPERATION

V+

Q

8

OUTPUT

Q

STAGE

12

4

NEGATIVE

V-

SUPPLY

V+

7

Q

8

OUTPUT

Q

STAGE

12

4

6

R

L

6

R

L

6