HARRIS Semiconductor 82C55A Service Manual

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Semiconductor

June 1998

82C55A

CMOS Programmable

Peripheral Interface

Features

• Pin Compatible with NMOS 8255A

• 24 Programmable I/O Pins

• Fully TTL Compatible

• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88

• Direct Bit Set/Reset Capability

• Enhanced Control Word Read Capability

• L7 Process

• 2.5mA Drive Capability on All I/O Ports

• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA

Ordering Information

P AR T NUMBERS

P ACKAGE

CP82C55A-5 CP82C55A
IP82C55A-5 IP82C55A -40
CS82C55A-5 CS82C55A
IS82C55A-5 IS82C55A -40
CD82C55A-5 CD82C55A
ID82C55A-5 ID82C55A -40
MD82C55A-5/B MD82C55A/B -55
8406601QA 8406602QA SMD# F40.6

MR82C55A-5/B MR82C55A/B
8406601XA 8406602XA SMD# J44.A

40 Ld PDIP

44 Ld PLCC

40 Ld
CERDIP

44 Pad
CLCC

TEMPERA TURE

RANGE

0oC to 70oC E40.6

o

C to 85oC E40.6

o

0

C to 70oC N44.65

o

C to 85oC N44.65

o

0

C to 70oC F40.6

o

C to 85oC F40.6

o

C to 125oC F40.6

o

C to 125oC J44.A

-55

PKG.

NO.5MHz 8MHz

Description

The Harris 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.

Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Harris advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.

Pinouts

82C55A (DIP)

TOP VIEW

1

PA3

2

PA2

3

PA1

4

PA0

5

RD

6

CS

7

GND

8

A1

9

A0

10

PC7

11

PC6

12

PC5

13

PC4

14

PC0

15

PC1

16

PC2

17

PC3

18

PB0

19

PB1

20

PB2

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

40

PA4

39

PA5

38

PA6

37

PA7

36

WR

35

RESE

34

D0

33

D1

32

D2

31

D3

30

D4

29

D5

28

D6

27

D7

26

V

CC

25

PB7

24

PB6

23

PB5

22

PB4

21

PB3

7

GND

8

NC

9

A1

10

A0

11

PC7

12

PC6

13

PC5

14

PC4

15

PC0
PC1

16

PC2

17

18 19 20 21 22 23 24 25 26 27 28

CS

PC3

RD

PB0

PA0

PB1

82C55A (CLCC)

TOP VIEW

PA1

PA2

PA3

PA4

PA5

PB3

PB2

PB4

PB5

PB6

PA6

PB7

1

WR

PA7

4065 321444342414

39

NC

38

RESET

37

D0

36

D1

35

D2

34

D3

33

D4

32

D5

31

D6

30

D7

29

NC

CC

NC

V

CS

GND

A1
A0

PC7

NC
PC6
PC5
PC4
PC0
PC1

7
8
9
10
11
12
13
14
15
16
17

82C55A (PLCC)

RD

PA0

PA1

PA2

PC2

PC3

PB0

PB1

TOP VIEW

NC

PA3

PA4

PA5

PA6

PA7

44 4342 41 40

123456

2827

262524232221201918

NC

PB2

PB3

PB4

PB5

PB6

File Number 2969.2

WR

PB7

39

RESET

38

D0
D1

37

D2

36

D3

35

NC

34

D4

33

D5

32

D6

31

D7

30

V

29

CC

82C55A

Pin Description

PIN

SYMBOL

V

CC

GND 7 GROUND

D0-D7 27-34 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the

RESET 35 I RESET: A high on this input clears the control register and all ports (A, B, C) are set

CS 6 I CHIP SELECT: Chip selectis an activelowinput used toenable the 82C55Aonto the

RD 5 I READ: Read is an active low input control signal used by the CPU to read status

WR 36 I WRITE: Write is an active low input control signal used by the CPU to load control

A0-A1 8, 9 I ADDRESS: These input signals, in conjunction with the RD and WR inputs, control

PA0-PA7 1-4, 37-40 I/O PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are

PB0-PB7 18-25 I/O PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PC0-PC7 10-17 I/O PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.

NUMBER TYPE DESCRIPTION

26 VCC: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is

recommended for decoupling.

system data bus.

to the input mode with the “Bus Hold” circuitry turned on.

Data Bus for CPU communications.

information or data via the data bus.

words and data into the 82C55A.

the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.

present on this port.

Functional Diagram

POWER

SUPPLIES

BI-DIRECTIONAL

DATA BUS

D7-D0

RD

WR

A1
A0

RESET

+5V
GND

DATA BUS

BUFFER

READ

WRITE

CONTROL

LOGIC

GROUP A

CONTROL

GROUP B

CONTROL

8-BIT

INTERNAL

DATA BUS

GROUP A

PORT A

(8)

GROUP A

PORT C

UPPER

(4)

GROUP B

PORT C
LOWER

(4)

GROUP B

PORT B

(8)

I/O

PA7-PA0

I/O

PC7-PC4

I/O

PC3-PC0

I/O

PB7-PB0

CS

2

82C55A

Functional Description

Data Bus Buffer

This three-state bi-directional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status informa­tion are also transferred through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of theControl Groups.

(CS) Chip Select. A “low” on this input pin enables the
communcation between the 82C55A and the CPU.

(RD) Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.

(WR) Write. A “low” on this input pin enables the CPU to
write data or control words into the 82C55A.

(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).

82C55A BASIC OPERATION

INPUT OPERATION

A1 A0 RD WR CS

00010Port A → Data Bus

01010Port B → Data Bus

10010Port C → Data Bus

11010Control Word → Data Bus

00100Data Bus → Port A

01100Data Bus → Port B

(READ)

OUTPUT OPERATION

(WRITE)

I/O

PA7-

POWER

SUPPLIES

BI-DIRECTIONAL

DATA BUS

D7-D0

RD

WR

A1
A0

RESET

CS

FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,

+5V
GND

DAT A

BUS

BUFFER

READ

WRITE

CONTROL

LOGIC

READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS

GROUP A

CONTROL

8-BIT

INTERNAL

DATA BUS

GROUP B

CONTROL

GROUP A

PORT A

(8)

GROUP A

PORT C

UPPER

(4)

GROUP B

PORT C
LOWER

(4)

GROUP B

PORT B

(8)

PA0

I/O

PC7-

PC4

I/O

PC3-

PC0

I/O

PB7-

PB0

(RESET) Reset. A “high” on this input initializes the control

register to 9Bh and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the 82C55A will hold
the I/O port inputs to a logic “1” state with a maximum hold
current of 400µA.

Group A and Group B Controls

The functional configuration of each port is programmed by
the systems software. In essence, the CPU “outputs” a con­trol word to the 82C55A. The control word contains
information such as “mode”, “bitset”, “bit reset”,etc., that ini­tializes the functional configuration of the 82C55A.

Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.

Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as

shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
“1”, as this implies control word mode information.

10100Data Bus → Port C

11100Data Bus → Control

DISABLE FUNCTION

XXXX1Data Bus → Three-State

X X 1 1 0 Data Bus → Three-State

3

82C55A

Ports A, B, and C

The 82C55A contains three 8-bit ports (A, B, and C). All can
be configured to a wide variety of functional characteristics
by the system software but each has itsown special features
or “personality” to further enhance the power and flexibility of
the 82C55A.

Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus-hold devices
are present on Port A. See Figure 2A.

Port B One 8-bit data input/output latch/buffer and one 8-bit
data input buffer. See Figure 2B.

Port C One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
two 4-bit ports under the mode control. Each 4-bit port con­tains a 4-bit latch and it can be used for the control signal
output and status signal inputs in conjunction with ports A
and B. See Figure 2B.

MASTER

RESET

OR MODE

CHANGE

INTERNAL

DATA IN

INTERNAL

DATA OUT

(LATCHED)

FIGURE 2A. PORT A BUS-HOLD CONFIGURATION

RESET

OR MODE

CHANGE

INPUT MODE

OUTPUT MODE

V

CC

P

EXTERNAL
PORT A PIN

register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 82C55A to
service a variety of peripheraldevices with a simple software
maintenance routine. Any port programmed as an output
port is initialized to all zeros when thecontrol word iswritten.

ADDRESS BUS

CONTROL BUS

DATA BUS

RD, WR

MODE 0

MODE 1

MODE 2

B

8 I/O

PB7-PB0

B

8 I/O

PB7-PB0 CONTROL

B

8 I/O

PB7-PB0

FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE

D7-D0 A0-A1

82C55A

C

4 I/O

PC3-PC0

OR I/O

PC7-PC4

C

CONTROL

OR I/O

C

CONTROL

4 I/O

CS

A

8 I/O

PA7-PA0

A

8 I/O

PA7-PA0

A

BI­DIRECTIONAL

PA7-PA0

INTERNAL

DATA IN

INTERNAL

DATA OUT

(LATCHED)

OUTPUT MODE

EXTERNAL
PORT B, C
PIN

FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION

FIGURE 2. BUS-HOLD CONFIGURATION

Operational Description

Mode Selection

There are three basic modes of operation than can be
selected by the system software:

Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-directional Bus

When the reset input goes “high”, all ports will be set to the
input mode with all 24 port lines held ata logic “one” level by
internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional ini­tialization required. This eliminates the need to pullup or pull­down resistors in all-CMOS designs. The control word

CONTROL WORD

D7 D6 D5 D4 D3 D2 D1 D0

FIGURE 4. MODE DEFINITION FORMAT

GROUP B

PORT C (LOWER)
1 = INPUT
0 = OUTPUT

PORT B
1 = INPUT
0 = OUTPUT

MODE SELECTION
0 = MODE 0
1 = MODE 1

GROUP A

PORT C (UPPER)
1 = INPUT
0 = OUTPUT

PORT A
1 = INPUT
0 = OUTPUT

MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2

MODE SET FLAG
1 = ACTIVE

4

82C55A

The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display compu­tational results, Group A could be programmed in Mode 1 to
monitor a keyboard or tape reader on an interrupt-driven
basis.

The mode definitions and possible mode combinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal defi­nition vs. PC layout and complete functional flexibility to sup­port almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.

Single Bit Set/Reset Feature (Figure 5)

Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.

When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.

CONTROL WORD

D7 D6 D5 D4 D3 D2 D1 D0

XXX

DON’T

CARE

FIGURE 5. BIT SET/RESET FORMAT

BIT SET/RESET
1 = SET
0 = RESET

BIT SELECT

0

1234567
01010101
00110011
00001111

BIT SET/RESET FLAG
0 = ACTIVE

B0
B1
B2

Interrupt Control Functions

When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting orresetting the associated INTE flip-flop, using the
bit set/reset function of port C.

This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.

INTE Flip-Flop Definition

(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable

NOTE: All Mask flip-flops are automatically reset during mode se­lection and device Reset.

Operating Modes

Mode 0 (Basic Input/Output). This functional configuration

provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply writ­ten to or read from a specific port.

Mode 0 Basic Functional Definitions:

• Two 8-bit ports and two 4-bit ports

• Any Port can be input or output

• Outputs are latched

• Input are not latched

• 16 different Input/Output configurations possible

MODE 0 PORT DEFINITION

A B GROUP A

PORTC

D4 D3 D1 D0 PORTA

0 0 0 0 Output Output 0 Output Output
0 0 0 1 Output Output 1 Output Input
0 0 1 0 Output Output 2 Input Output
0 0 1 1 Output Output 3 Input Input
0 1 0 0 Output Input 4 Output Output
0 1 0 1 Output Input 5 Output Input
0 1 1 0 Output Input 6 Input Output
0 1 1 1 Output Input 7 Input Input
1 0 0 0 Input Output 8 Output Output
1 0 0 1 Input Output 9 Output Input
1 0 1 0 Input Output 10 Input Output
1 0 1 1 Input Output 11 Input Input
1 1 0 0 Input Input 12 Output Output
1 1 0 1 Input Input 13 Output Input
1 1 1 0 Input Input 14 Input Output
1 1 1 1 Input Input 15 Input Input

(Upper) PORTB

#

GROUP B

PORTC

(Lower)

5

Mode 0 (Basic Input)

RD

82C55A

tRR

INPUT

CS, A1, A0

D7-D0

Mode 0 (Basic Output)

WR

D7-D0

CS, A1, A0

OUTPUT

Mode 0 Configurations

tAW

tAR

tIR

tHR

tRA

tRD tDF

tWW

tDW

tWD

tWA

tWB

CONTROL WORD #0 CONTROL WORD #2

82C55A

C

D0

1D70D60D50D40D30D21D10

8

4

4

8

PA7 - PA0

PC7 - PC4

D7 - D0

PC3 - PC0

PB7 - PB0

A

B

D7

0D60D50D40D30D20D10

1

D7 - D0

CONTROL WORD #1 CONTROL WORD #3

D0

1D70D60D50D40D30D20D11

82C55A

D7 - D0

8

4

4

8

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

A

C

B

1D70D60D50D40D30D21D11

D7 - D0

82C55A

C

82C55A

C

D0

D0

8

4

4

8

8

4

4

8

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

A

B

A

B

6

82C55A

Mode 0 Configurations (Continued)

CONTROL WORD #4 CONTROL WORD #8

D0

1D70D60D50D41D30D20D10

82C55A

D7 - D0

8

4

4

PA7 - PA0

PC7 - PC4

PC3 - PC0

A

C

1D70D60D51D40D30D20D10

D7 - D0

82C55A

C

D0

8

4

4

PA7 - PA0

PC7 - PC4

PC3 - PC0

A

8

B

PB7 - PB0

CONTROL WORD #5 CONTROL WORD #9

D0

1D70D60D50D41D30D20D11

82C55A

D7 - D0

8

4

4

8

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

A

C

B

1D70D60D51D40D30D20D11

D7 - D0

CONTROL WORD #6 CONTROL WORD #10

D0

1D70D60D50D41D30D21D10

82C55A

D7 - D0

8

4

4

PA7 - PA0

PC7 - PC4

PC3 - PC0

A

C

1D70D60D51D40D30D21D10

D7 - D0

82C55A

C

82C55A

C

D0

D0

8

8

4

4

8

8

4

4

PB7 - PB0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

PA7 - PA0

PC7 - PC4

PC3 - PC0

B

A

B

A

8

B

PB7 - PB0

CONTROL WORD #7 CONTROL WORD #11

D0

1D70D60D50D41D30D21D11

82C55A

D7 - D0

8

4

4

8

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

A

C

B

1D70D60D51D40D30D21D11

D7 - D0

7

82C55A

C

D0

8

8

4

4

8

PB7 - PB0

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

B

A

B

82C55A

Mode 0 Configurations (Continued)

CONTROL WORD #12 CONTROL WORD #14

D0

1D70D60D51D41D30D20D10

82C55A

D7 - D0

8

4

4

PA7 - PA0

PC7 - PC4

PC3 - PC0

A

C

1D70D60D51D41D30D21D10

D7 - D0

82C55A

C

D0

8

4

4

PA7 - PA0

PC7 - PC4

PC3 - PC0

A

8

B

PB7 - PB0

CONTROL WORD #13 CONTROL WORD #15

D0

1D70D60D51D41D30D20D11

82C55A

D7 - D0

8

4

4

8

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

A

C

B

1D70D60D51D41D30D21D11

D7 - D0

Operating Modes

Mode 1 - (Strobed Input/Output). This functional configura-

tion provides a means for transferring I/O data to or from a
specified port in conjunction with strobes or “hand shaking”
signals. In mode 1, port A and port B use the lines on port C
to generate or accept these “hand shaking” signals.

Mode 1 Basic Function Definitions:

• Two Groups (Group A and Group B)

• Each group contains one 8-bit port and one 4-bit
control/data port

• The 8-bit data port can be either input or output. Both
inputs and outputs are latched.

• The 4-bit port is used for control and status of the 8-bit
port.

Input Control Signal Definition

(Figures 6 and 7)

CONTROL WORD

1D70D61D51D41/0

CONTROL WORD

D6 D5 D4 D3 D2 D1 D0

D7

1

D3

82C55A

D2 D1 D0

PC6, PC7
1 = INPUT

0 = OUTPUT

RD

11

B

D0

A

C

B

8

PB7 - PB0

8

PA7 - PA0

4

PC7 - PC4

4

PC3 - PC0

8

PB7 - PB0

MODE 1 (PORT A)

PA7-PA0

INTE

A

MODE 1 (PORT B)

INTE

B

PC4

PC3

PC6, PC7

PB7-PB0

PC2

2

8

STBA

IBFAPC5

INTRA

I/O

8

STBB
IBFBPC1

STB (Strobe Input)

A “low” on this input loads data into the input latch.

IBF (Input Buffer Full F/F)

A “high” on this output indicates that the data has been
loaded into the input latch: in essence, and acknowledg­ment. IBF is set by
rising edge of the

STB input being low and is reset by the

RD input.

PC0

RD

INTRB

FIGURE 6. MODE 1 INPUT

8