HARRIS Semiconductor 82C54 Service Manual
Semiconductor
82C54
March 1997
Features
• 8MHz to 12MHz Clock Input Frequency
• Compatible with NMOS 8254
- Enhanced Version of NMOS 8253
• Three Independent 16-Bit Counters
• Six Programmable Counter Modes
• Status Read Back Command
• Binary or BCD Counting
• Fully TTL Compatible
• Single 5V Power Supply
• Low Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .10mA at 8MHz
• Operating Temperature Ranges
- C82C54 . . . . . . . . . . . . . . . . . . . . . . . . . .0
- I82C54 . . . . . . . . . . . . . . . . . . . . . . . . . -40
- M82C54 . . . . . . . . . . . . . . . . . . . . . . . -55
o
o
o
C to +125oC
C to +70oC
C to +85oC
CMOS Programmable Interval Timer
Description
The Harris 82C54 is a high performance CMOS Programmable Interval Timer manufactured using an adv anced 2 micron
CMOS process.
The 82C54 has three independently programmable and
functional 16-bit counters, each capable of handling clock
input frequencies of up to 8MHz (82C54) or 10MHz
(82C54-10) or 12MHz (82C54-12).
The high speed and industry standard configuration of the
82C54 make it compatible with the Harris 80C86, 80C88,
and 80C286 CMOS microprocessors along with many other
industry standard processors. Six programmable timer
modes allow the 82C54 to be used as an event counter,
elapsed time indicator, programmable one-shot, and many
other applications. Static CMOS circuit design insures low
power operation.
The Harris advanced CMOS process results in a significant
reduction in power with performance equal to or greater than
existing equivalent products.
Pinouts
82C54 (PDIP, CERDIP, SOIC)
TOP VIEW
1
D7
D6
2
3
D5
D4
4
D3
5
D2
6
D1
7
8
D0
9
CLK 0
10
OUT 0
11
GATE 0
12
GND
24
23
22
21
20
19
18
17
16
15
14
13
VCC
WR
RD
CS
A1
A0
CLK 2
OUT 2
GATE 2
CLK 1
GATE 1
OUT 1
CLK 0
NC
82C54 (PLCC/CLCC)
TOP VIEW
VCC
WR
OUT 1
GATE 1
262728
RD
CLK 1
25
24
23
22
21
20
19
NC
CS
A1
A0
CLK2
OUT 2
GATE 2
D6
GATE 0
D7
GND
NC
1234
NC
D5
5
D4
6
D3
7
D2
8
D1
9
D0
10
11
12 13 14 15 16 17 18
OUT 0
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
4-1
File Number 2970.1
Ordering Information
82C54
PART NUMBERS
TEMPERATURE
RANGE PACKAGE PKG. NO.8MHz 10MHz 12MHz
CP82C54 CP82C54-10 CP82C54-12 0oC to +70oC 24 Lead PDIP E24.6
IP82C54 IP82C54-10 IP82C54-12 -40oC to +85oC 24 Lead PDIP E24.6
CS82C54 CS82C54-10 CS82C54-12 0oC to +70oC 28 Lead PLCC N28.45
IS82C54 IS82C54-10 IS82C54-12 -40oC to +85oC 28 Lead PLCC N28.45
CD82C54 CD82C54-10 CD82C54-12 0oC to +70oC 24 Lead CERDIP F24.6
ID82C54 ID82C54-10 ID82C54-12 -40oC to +85oC 24 Lead CERDIP F24.6
MD82C54/B MD82C54-10/B MD82C54-12/B -55oC to +125oC 24 Lead CERDIP F24.6
MR82C54/B MR82C54-10/B MR82C54-12/B -55oC to +125oC 28 Lead CLCC J28.A
SMD # 8406501JA - 8406502JA -55oC to +125oC 24 Lead CERDIP F24.6
SMD# 84065013A - 84065023A -55oC to +125oC 28 Lead CLCC J28.A
CM82C54 CM82C54-10 CM82C54-12 0oC to +70oC 24 Lead SOIC M24.3
Functional Diagram
DAT A/
BUS
8
- D
D
7
RD
WR
A
A
CS
0
0
1
BUFFER
READ/
WRITE
LOGIC
INTERNAL BUS
COUNTER
0
COUNTER
1
CLK 0
GATE 0
OUT 0
CLK 1
GATE 1
OUT 1
CONTROL
WORD
REGISTER
CONTROL
LOGIC
STATUS
LATCH
STATUS
REGISTER
INTERNAL BUS
CR
M
CE
CR
L
CONTROL
WORD
REGISTER
COUNTER
2
CLK 2
GATE 2
OUT 2
CLK n
GATE n
OUT n
COUNTER INTERNAL BLOCK DIAGRAM
OL
M
Pin Description
DIP PIN
SYMBOL
D7 - D0 1 - 8 I/O DATA: Bi-directional three-state data bus lines, connected to system data bus.
CLK 0 9 I CLOCK 0: Clock input of Counter 0.
OUT 0 10 O OUT 0: Output of Counter 0.
GATE 0 11 I GATE 0: Gate input of Counter 0.
GND 12 GROUND: Power supply connection.
OUT 1 13 O OUT 1: Output of Counter 1.
GATE 1 14 I GATE 1: Gate input of Counter 1.
CLK 1 15 I CLOCK 1: Clock input of Counter 1.
GATE 2 16 I GATE 2: Gate input of Counter 2.
OUT 2 17 O OUT 2: Output of Counter 2.
NUMBER TYPE DEFINITION
OL
L
4-2
82C54
Pin Description
DIP PIN
SYMBOL
CLK 2 18 I CLOCK 2: Clock input of Counter 2.
A0, A1 19 - 20 I ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
CS 21 I CHIP SELECT: A low on this input enables the 82C54 to respond toRD and WR signals. RD and
RD 22 I READ: This input is low during CPU read operations.
WR 23 I WRITE: This input is low during CPU write operations.
V
CC
NUMBER TYPE DEFINITION
(Continued)
operations. Normally connected to the system address bus.
A1 A0 SELECTS
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
WR are ignored otherwise.
24 VCC: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended
for decoupling.
Functional Description
General
The 82C54 is a programmable interval timer/counter
designed for use with microcomputer systems. It is a general
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.
- D
D
7
0
8
DAT A/
BUS
BUFFER
COUNTER
0
CLK 0
GATE 0
OUT 0
The 82C54 solves one of the most common problems in any
microcomputer system, the generation of accurate time
delays under software control. Instead of setting up timing
loops in software, the programmer configures the 82C54 to
match his requirements and programs one of the counters
for the desired delay. After the desired delay, the 82C54 will
interrupt the CPU. Software overhead is minimal and variable length delays can easily be accommodated.
Some of the other computer/timer functions common to microcomputers which can be implemented with the 82C54 are:
• Real time clock
• Event counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex waveform generator
• Complex motor controller
Data Bus Buffer
This three-state, bi-directional, 8-bit buffer is used to interface the 82C54 to the system bus (see Figure 1).
RD
WR
A
0
A
1
CS
FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC
READ/
WRITE
LOGIC
CONTROL
WORD
REGISTER
FUNCTIONS
COUNTER
1
INTERNAL BUS
COUNTER
2
CLK 1
GATE 1
OUT 1
CLK 2
GATE 2
OUT 2
Read/Write Logic
The Read/Write Logic accepts inputs from the system bus and
generates control signals for the other functional blocks of the
82C54. A1 and A0 select one of the three counters or the Control Word Register to be read from/written into. A “low” on the
RD input tells the 82C54 that the CPU is reading one of the
counters. A “low” on the
is writing either a Control Word or an initial count. Both
WR input tells the 82C54 that the CPU
RD and
WR are qualified by CS; RD and WR are ignored unless the
82C54 has been selected by holding
CS low.
4-3
Control Word Register
82C54
The Control Word Register (Figure 2) is selected by the
Read/Write Logic when A1, A0 = 11. If the CPU then does a
write operation to the 82C54, the data is stored in the Control Word Register and is interpreted as a Control Word used
to define the Counter operation.
The Control Word Register can only be written to; status
information is available with the Read-Back Command.
CLK 0
GATE 0
OUT 0
CLK 1
GATE 1
OUT 1
CLK 2
GATE 2
OUT 2
D
- D
7
0
RD
WR
A
0
A
1
CS
8
DAT A/
BUS
BUFFER
READ/
WRITE
LOGIC
CONTROL
WORD
REGISTER
INTERNAL BUS
COUNTER
0
COUNTER
1
COUNTER
2
FIGURE 2. CONTROL WORD REGISTER AND COUNTER
FUNCTIONS
Counter 0, Counter 1, Counter 2
These three functional blocks are identical in operation, so
only a single Counter will be described. The internal block
diagram of a signal counter is shown in Figure 3. The
counters are fully independent. Each Counter may operate
in a different Mode.
The Control Word Register is shown in the figure; it is not
part of the Counter itself, but its contents determine how the
Counter operates.
The status register, shown in the figure, when latched, contains the current contents of the Control Word Register and
status of the output and null count flag. (See detailed explanation of the Read-Back command.)
The actual counter is labeled CE (for Counting Element). It is
a 16-bit presettable synchronous down counter.
INTERNAL BUS
CONTROL
WORD
REGISTER
CONTROL
LOGIC
GATE n
CLK n
OUT n
STATUS
LATCH
STATUS
REGISTER
CR
OL
CE
CR
OL
L
L
M
M
FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM
OLM and OLL are two 8-bit latches. OL stands for “Output
Latch”; the subscripts M and L for “Most significant byte” and
“Least significant byte”, respectively. Both are normally referred
to as one unit and called just OL. These latches normally “follow” the CE, but if a suitable Counter Latch Command is sent to
the 82C54, the latches “latch” the present count until read by
the CPU and then return to “following” the CE. One latch at a
time is enabled by the counter’s Control Logic to drive the internal bus. This is how the 16-bit Counter communicates over the
8-bit internal bus. Note that the CE itself cannot be read; whenever you read the count, it is the OL that is being read.
Similarly, there are two 8-bit registers called CRM and CRL (for
“Count Register”). Both are normally referred to as one unit and
called just CR. When a new count is written to the Counter, the
count is stored in the CR and later transferred to the CE. The
Control Logic allows one register at a time to be loaded from
the internal bus. Both bytes are transferred to the CE simultaneously. CRM and CRL are cleared when the Counter is programmed for one byte counts (either most significant byte only
or least significant byte only) the other byte will be zero. Note
that the CE cannot be written into; whenever a count is written,
it is written into the CR.
The Control Logic is also shown in the diagram. CLK n,
GATE n, and OUT n are all connected to the outside world
through the Control Logic.
82C54 System Interface
The 82C54 is treated by the system software as an array of
peripheral I/O ports; three are counters and the fourth is a
control register for MODE programming.
Basically, the select inputs A0, A1 connect to the A0, A1
address bus signals of the CPU. The
CS can be derived
directly from the address bus using a linear select method or
it can be connected to the output of a decoder.
4-4
82C54
Operational Description
General
After power-up, the state of the 82C54 is undefined. The
Mode, count value, and output of all Counters are undefined.
How each Counter operates is determined when it is programmed. Each Counter must be programmed before it can
be used. Unused counters need not be programmed.
Programming the 82C54
Counters are programmed by writing a Control Word and
then an initial count.
All Control Words are written into the Control Word Register,
which is selected when A1, A0 = 11. The Control Word specifies which Counter is being programmed.
By contrast, initial counts are written into the Counters, not
the Control Word Register. The A1, A0 inputs are used to
select the Counter to be written into. The format of the initial
count is determined by the Control Word used.
ADDRESS BUS (16)
A1 A0
CONTROL BUS
I/OR I/OW
DATA BUS (8)
8
RD
COUNTER
2
WR
CS
A0
A1
COUNTER
0
OUTGATECLK
D0 - D7
82C54
COUNTER
1
OUTGATECLK OUTGATECLK
SC - Select Counter
SC1 SC0
0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 Read-Back Command (See Read Operations)
RW - Read/Write
RW1 RW0
0 0 Counter Latch Command (See Read Operations)
0 1 Read/Write least significant byte only.
1 0 Read/Write most significant byte only.
1 1 Read/Write least significant byte first, then most
significant byte.
M - Mode
M2 M1 M0
0 0 0 Mode 0
0 0 1 Mode 1
X 1 0 Mode 2
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
BCD - Binary Coded Decimal
0 Binary Counter 16-bit
1 Binary Coded Decimal (BCD) Counter (4 Decades)
NOTE: Don’t Care bits (X) should be 0 to insure compatibility with
future products.
FIGURE 4. 82C54 SYSTEM INTERFACE
Write Operations
The programming procedure for the 82C54 is ver y flexible.
Only two conventions need to be remembered:
1.For Each Counter, the Control Word must be written
before the initial count is written.
2.The initial count must follow the count format specified in the
Control Word (least significant byte only, most significant byte
only, or least significant byte and then most significant byte).
Since the Control Word Register and the three Counters have
separate addresses (selected by the A1, A0 inputs), and each
Control Word specifies the Counter it applies to (SC0, SC1 bits),
no special instruction sequence is required. Any programming
sequence that follows the con v entions abo v e is acceptab le .
Control Word Format
A1, A0 = 11;
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
CS = 0; RD = 1; WR = 0
Possible Programming Sequence
A1 A0
Control Word - Counter 0 1 1
LSB of Count - Counter 0 0 0
MSB of Count - Counter 0 0 0
Control Word - Counter 1 1 1
LSB of Count - Counter 1 0 1
MSB of Count - Counter 1 0 1
Control Word - Counter 2 1 1
LSB of Count - Counter 2 1 0
MSB of Count - Counter 2 1 0
Possible Programming Sequence
A1 A0
Control Word - Counter 0 1 1
Control Word - Counter 1 1 1
Control Word - Counter 2 1 1
LSB of Count - Counter 2 1 0
4-5
82C54
Possible Programming Sequence (Continued)
A1 A0
LSB of Count - Counter 1 0 1
LSB of Count - Counter 0 0 0
MSB of Count - Counter 0 0 0
MSB of Count - Counter 1 0 1
MSB of Count - Counter 2 1 0
Possible Programming Sequence
A1 A0
Control Word - Counter 2 1 1
Control Word - Counter 1 1 1
Control Word - Counter 0 1 1
LSB of Count - Counter 2 1 0
MSB of Count - Counter 2 1 0
LSB of Count - Counter 1 0 1
MSB of Count - Counter 1 0 1
LSB of Count - Counter 0 0 0
MSB of Count - Counter 0 0 0
Possible Programming Sequence
A1 A0
Control Word - Counter 1 1 1
Control Word - Counter 0 1 1
LSB of Count - Counter 1 0 1
Control Word - Counter 2 1 1
LSB of Count - Counter 0 0 0
MSB of Count - Counter 1 0 1
LSB of Count - Counter 2 1 0
MSB of Count - Counter 0 0 0
MSB of Count - Counter 2 1 0
NOTE: In all four examples, all counters are programmed to
Read/Write two-byte counts. These are only four of many
programming sequences.
A new initial count may be written to a Counter at any time
without affecting the Counter’s programmed Mode in any way.
Counting will be affected as described in the Mode definitions.
The new count must follo w the prog r ammed count format.
If a Counter is programmed to read/write two-byte counts,
the following precaution applies. A progr am must not tr ansf er
control between writing the first and second byte to another
routine which also writes into that same Counter. Otherwise,
the Counter will be loaded with an incorrect count.
Read Operations
It is often desirable to read the value of a Counter without
disturbing the count in progress. This is easily done in the
82C54.
There are three possible methods for reading the Counters.
The first is through the Read-Back command, which is
explained later. The second is a simple read operation of the
Counter, which is selected with the A1, A0 inputs. The only
requirement is that the CLK input of the selected Counter
must be inhibited by using either the GATE input or external
logic. Otherwise, the count may be in process of changing
when it is read, giving an undefined result.
Counter Latch Command
The other method for reading the Counters involves a special software command called the “Counter Latch Command”. Like a Control Word, this command is written to the
Control Word Register, which is selected when A1, A0 = 11.
Also, like a Control Word, the SC0, SC1 bits select one of
the three Counters, but two other bits, D5 and D4, distinguish this command from a Control Word.
.
A1, A0 = 11; CS = 0; RD = 1; WR = 0
D7 D6 D5 D4 D3 D2 D1 D0
SC1SC000XXXX
SC1, SC0 - specify counter to be latched
SC1 SC0 COUNTER
00 0
01 1
10 2
1 1 Read-Back Command
D5, D4 - 00 designates Counter Latch Command, X - Don’t Care.
NOTE: Don’t Care bits (X) should be 0 to insure compatibility with
future products.
The selected Counter’s output latch (OL) latches the count
when the Counter Latch Command is received. This count is
held in the latch until it is read by the CPU (or until the Counter
is reprogrammed). The count is then unlatched automatically
and the OL returns to “following” the counting element (CE).
This allows reading the contents of the Counters “on the fly”
without affecting counting in progress. Multiple Counter Latch
Commands may be used to latch more than one Counter.
Each latched Counter’s OL holds its count until read. Counter
Latch Commands do not affect the programmed Mode of the
Counter in any way.
If a Counter is latched and then, some time later, latched
again before the count is read, the second Counter Latch
Command is ignored. The count read will be the count at the
time the first Counter Latch Command was issued.
With either method, the count must be read according to the
programmed format; specifically, if the Counter is programmed for two byte counts, two bytes must be read. The
two bytes do not have to be read one right after the other ;
read or write or programming operations of other Counters
may be inserted between them.
Another feature of the 82C54 is that reads and writes of the
same Counter may be interleaved; for example, if the
Counter is programmed for two byte counts, the following
sequence is valid.
4-6
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