HARRIS Semiconductor 82C37A Service Manual

查询5962-9054303MQA供应商

SEMICONDUCTOR

March 1997

Features

• Compatible with the NMOS 8237A

• Four Independent Maskable Channels with Autoinitial­ization Capability

• Cascadable to any Number of Channels

• High Speed Data Transfers:

- Up to 4MBytes/sec with 8MHz Clock

- Up to 6.25MBytes/sec with 12.5MHz Clock

• Memory-to-Memory Transfers

• Static CMOS Design Permits Low Power Operation

- ICCSB = 10µA Maximum

- ICCOP = 2mA/MHz Maximum

• Fully TTL/CMOS Compatible

• Internal Registers may be Read from Software

82C37A

CMOS High Performance

Programmable DMA Controller

Description

The 82C37A is an enhanced version of the industry standard
8237A Direct Memory Access (DMA) controller, fabricated
using Harris’ advanced 2 micron CMOS process. Pin
compatible with NMOS designs, the 82C37A offers
increased functionality, improved performance, and
dramatically reduced power consumption. The fully static
design permits gated clock operation for even further
reduction of power.

The 82C37A controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea­ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.

The 82C37A is designed to be used with an external
address latch, such as the 82C82, to demultiplex the most
significant 8-bits of address. The 82C37A can be used with
industry standard microprocessors such as 80C286, 80286,
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and
others. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).

Ordering Information

PART NUMBER

PACKAGE

CP82C37A-5 CP82C37A CP82C37A-12 40 Ld PDIP 0oC to +70oC E40.6
IP82C37A-5 IP82C37A IP82C37A-12 -40oC to +85oC E40.6
CS82C37A-5 CS82C37A CS82C37A-12 44 Ld PLCC 0oC to +70oC N44.65
IS82C37A-5 IS82C37A IS82C37A-12 -40oC to +85oC N44.65
CD82C37A-5 CD82C37A CD82C37A-12 40 Ld CERDIP 0oC to +70oC F40.6
ID82C37A-5 ID82C37A ID82C37A-12 -40oC to +85oC F40.6
MD82C37A-5/B MD82C37A/B MD82C37A-12/B -55oC to +125oC F40.6
5962-9054301MQA 5962-9054302MQA 5962-9054303MQA SMD# F40.6
MR82C37A-5/B MR82C37A/B MR82C37A-12/B 44 Pad CLCC -55oC to +125oC J44.A
5962-9054301MXA 5962-9054302MXA 5962-9054303MXA SMD# J44.A

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

4-192

TEMPERATURE

RANGE PKG. NO.5MHz 8MHz 12.5MHz

File Number 2967.1

Pinouts

(GND) VSS

IOR

IOW

MEMR

MEMW

NC

READY

HLDA

ADSTB

AEN

HRQ

CS

CLK

RESET
DACK2
DACK3
DREQ3
DREQ2
DREQ1
DREQ0

82C37A (PDIP/CERDIP)

TOP VIEW

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A7
A6
A5
A4
EOP
A3
A2
A1
A0
VCC
DB0
DB1
DB2
DB3
DB4
DACK0
DACK1
DB5
DB6
DB7

82C37A

NC
NC

HLDA

ADSTB

AEN

HRQ

CS

CLK

RESET

DACK2

NC

82C37A (CLCC/PLCC)

MEMW

READY

NC

4

6 3

7
8

9
10
11
12
13
14
15
16
17

DACK3

DREQ3

DREQ2

TOP VIEW

IOR

MEMR

IOW

25

1

GND

DREQ1

DREQ0

A7

A6

A5

EOP

DB6

DB5

A4

DACK1

40414243

39

A3

38

A2

37

A1
A0

36

VCC

35

DB0

34

DB1

33

DB2

32

DB3

31

DB4

30

NC

29

2827262524232221201918

DACK0

44

DB7

Block Diagram

EOP

RESET

CS

READY

CLK
AEN

ADSTB

MEMR

MEMW

IOR

IOW

DREQ0 -

DREQ3

HLDA

DACK0 -

DACK3

4

HRQ

4

TIMING

AND

CONTROL

PRIORITY

ENCODER

AND

ROTATING

PRIORITY

LOGIC

DECREMENTOR

TEMP WORD

COUNT REG (16)

READ BUFFER

BASE

ADDRESS

(16)

COMMAND

(8)

MASK

(4)

REQUEST

(4)

16-BIT BUS

16-BIT BUS

BASE

WORD

COUNT

(16)

INC/DECREMENTOR

TEMP ADDRESS

REG (16)

READ WRITE BUFFER

CURRENT
ADDRESS

(16)

WRITE

BUFFER

MODE
(4 x 6)

CURRENT

WORD

COUNT

(16)

READ

BUFFER

INTERNAL DATA BUS

STATUS

(8)

A8 - A15

TEMPORARY

IO

BUFFER

OUTPUT
BUFFER

COMMAND

CONTROL

(8)

A0 - A3

A4 - A7

D0 - D1

IO

BUFFER

DB0 - DB7

4-193

Pin Description

PIN

SYMBOL

NUMBER TYPE DESCRIPTION

82C37A

V

CC

GND 20 Ground

CLK 12 I CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A

CS 11 I CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus f or

RESET 13 I RESET: This is an active high input which clears the Command, Status, Request, and Temporary

READY 6 I READY: This signal can be used to extend the memory read and write pulses from the 82C37A to

HLDA 7 I HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has

DREQ0-

DREQ3

31 VCC: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for

decoupling.

operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for
the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for
standby operation.

CPU communications.

registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore
requests. Following a Reset, the controller is in an idle cycle.

accommodate slow memories or I/O devices. READY must not make transitions during its specified
set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode.

relinquished control of the system busses. HLDA is a synchronous input and must not transition
during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising
edge of CLK, during which time HLDA must not transition.

16-19 I DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request

inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest
priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a
channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is
programmable. RESET initializes these lines to active high. DREQ must be maintained until the
corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused
DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set.

DB0-DB7 21-23

26-30

IOR 1 I/O I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con-

IOW 2 I/O I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con-

I/O DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data

bus. The outputs are enabled in the Program condition during the I/O Read to output the contents
of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle
when the CPU is programming the 82C37A control registers. During DMA cycles, the most signifi­cant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB.
In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during
the read-from-memory transfer, then during the write-to-memory transfer , the data bus outputs write
the data into the new memory location.

trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control
signal used by the 82C37A to access data from the peripheral during a DMA Write transfer.

trol signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output
control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.

4-194

82C37A

Pin Description

SYMBOL

EOP 36 I/O END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information

A0-A3 32-35 I/O ADDRESS: The four least significant address lines are bidirectional three-state signals. In the Idle

A4-A7 37-40 O ADDRESS: The four most significant address lines are three-state outputs and provide 4-bits of

HRQ 10 O HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus.

NUMBER TYPE DESCRIPTION

(Continued)

PIN

concerning the completion of DMA services is available at the bidirectional EOP pin.
The 82C37A allows an external signal to terminate an active DMA service by pulling the EOP pin

low. A pulse is generated by the 82C37A when terminal count (TC) for any channel is reached,
except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will
be output when the TC for channel 1 occurs.

The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor
to VCC.

When an EOP pulse occurs, whether internally or externally generated, the 82C37A will terminate
the service, and if autoinitialize is enabled, the base registers will be written to the current registers
of that channel. The mask bit and TC bit in the status word will be set for the currently active channel
by EOP unless the channel is programmed for autoinitialize . In that case, the mask bit remains clear .

cycle, they are inputs and are used by the 82C37A to address the control register to be loaded or
read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address.

address. These lines are enabled only during the DMA service.

When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made ,
the 82C37A issues HRQ. The HLDA signal then informs the controller when access to the system
busses is permitted. For stand-alone operation where the 82C37A always controls the b usses, HRQ
may be tied to HLDA. This will result in one S0 state before the transfer.

DACK0-

DACK3

AEN 9 O ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits

ADSTB 8 O ADDRESS STROBE: This is an active high signal used to control latching of the upper address

MEMR 3 O MEMORY READ: The Memory Read signal is an active low three-state output used to access data

MEMW 4 O MEMORY WRITE: The Memory Write signal is an active low three-state output used to write data

NC 5 NO CONNECT: Pin 5 is open and should not be tested for continuity.

14, 15
24, 25

O DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one

has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them
to active low.

onto the system address bus. AEN can also be used to disable other system bus drivers during DMA
transfers. AEN is active high.

byte. It will drive directly the strobe input of external transparent octal latches, such as the 82C82.
During block operations, ADSTB will only be issued when the upper address byte must be updated,
thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling
edge of the 82C37A clock.

from the selected memory location during a DMA Read or a memory-to-memory transfer.

to the selected memory location during a DMA Write or a memory-to-memory transfer.

4-195

Functional Description

82C37A

The 82C37A direct memory access controller is designed to
improve the data transfer rate in systems which must
transfer data from an I/O device to memory, or move a block
of memory to an I/O device. It will also perform memory-to­memory block moves, or fill a block of memory with data
from a single location. Operating modes are provided to
handle single byte transfers as well as discontinuous data
streams, which allows the 82C37A to control data movement
with software transparency.

The DMA controller is a state-driven address and control
signal generator, which permits data to be transferred
directly from an I/O device to memory or vice versa without
ever being stored in a temporary register. This can greatly
increase the data transfer rate for sequential operations,
compared with processor move or repeated string
instructions. Memory-to-memory operations require
temporary internal storage of the data byte between
generation of the source and destination addresses, so
memory-to-memory transfers take place at less than half the
rate of I/O operations, but still much faster than with central
processor techniques. The maximum data transfer rates
obtainable with the 82C37A are shown in Figure 1.

The block diagram of the 82C37A is shown on page 2. The
timing and control block, priority block, and internal registers
are the main components. Figure 2 lists the name and size
of the internal registers. The timing and control block derives
internal timing from clock input, and generates external
control signals. The Priority Encoder block resolves priority
contention between DMA channels requesting service
simultaneously.

For example, if a block of data is to be transferred from RAM
to an I/O device, the starting address of the data is loaded
into the 82C37A Current and Base Address registers for a
particular channel, and the length of the block is loaded into
the channel’s Word Count register. The corresponding Mode
register is programmed for a memory-to-I/O operation (read
transfer), and various options are selected by the Command
register and the other Mode register bits. The channel’s
mask bit is cleared to enable recognition of a DMA request
(DREQ). The DREQ can either be a hardware signal or a
software command.

Once initiated, the block DMA transfer will proceed as the
controller outputs the data address, simultaneous
and

IOW pulses, and selects an I/O device via the DMA

MEMR

acknowledge (DACK) outputs. The data byte flows directly
from the RAM to the I/O device. After each byte is
transferred, the address is automatically incremented (or
decremented) and the word count is decremented. The
operation is then repeated for the next byte. The controller
stops transferring data when the Word Count register
underflows, or an external

NAME SIZE NUMBER

Base Address Registers 16-Bits 4

Base Word Count Registers 16-Bits 4

Current Address Registers 16-Bits 4

Current Word Count Registers 16-Bits 4

EOP is applied.

82C37A

TRANSFER

TYPE 5MHz 8MHz 12.5MHz UNIT

Compressed 2.50 4.00 6.25 MByte/sec

Normal I/O 1.67 2.67 4.17 MByte/sec

Memory-to­Memory

0.63 1.00 1.56 MByte/sec

FIGURE 1. DMA TRANSFER RATES

DMA Operation

In a system, the 82C37A address and control outputs and
data bus pins are basically connected in parallel with the
system busses. An external latch is required for the upper
address byte. While inactive, the controller’s outputs are in a
high impedance state. When activated by a DMA request
and bus control is relinquished by the host, the 82C37A
drives the busses and generates the control signals to
perform the data transfer. The operation performed by
activating one of the four DMA request inputs has previously
been programmed into the controller via the Command,
Mode, Address, and Word Count registers.

Temporary Address Register 16-Bits 1

Temporary Word Count Register 16-Bits 1

Status Register 8-Bits 1

Command Register 8-Bits 1

Temporary Register 8-Bits 1

Mode Registers 6-Bits 4

Mask Register 4-Bits 1

Request Register 4-Bits 1

FIGURE 2. 82C37A INTERNAL REGISTERS

To further understand 82C37A operation, the states
generated by each clock cycle must be considered. The
DMA controller operates in two major cycles, active and idle.
After being programmed, the controller is normally idle until
a DMA request occurs on an unmasked channel, or a
software request is given. The 82C37A will then request
control of the system busses and enter the active cycle. The
active cycle is composed of several internal states,
depending on what options have been selected and what
type of operation has been requested.

4-196

82C37A

The 82C37A can assume seven separate states, each
composed of one full clock period. State I (SI) is the idle
state. It is entered when the 82C37A has no valid DMA
requests pending, at the end of a transfer sequence, or
when a Reset or Master Clear has occurred. While in SI, the
DMA controller is inactive but may be in the Program
Condition (being programmed by the processor).

State 0 (S0) is the first state of a DMA service. The 82C37A
has requested a hold but the processor has not yet returned
an acknowledge. The 82C37A may still be programmed until
it has received HLDA from the CPU. An acknowledge from
the CPU will signal the DMA transfer may begin. S1, S2, S3,
and S4 are the working state of the DMA service. If more
time is needed to complete a transfer than is available with
normal timing, wait states (SW) can be inserted between S3
and S4 in normal transfers by the use of the Ready line on
the 82C37A. For compressed transfers, wait states can be
inserted between S2 and S4. See timing Figures 14 and 15.

Note that the data is transferred directly from the I/O device
to memory (or vice versa) with
and

IOW) being active at the same time. The data is not read
into or driven out of the 82C37A in I/O-to-memory or
memory-to-I/O DMA transfers.

Memory-to-memory transfers require a read-from and a write­to memory to complete each transfer. The states, which
resemble the normal working states, use two-digit numbers
for identification. Eight states are required for a single transfer.
The first four states (S11, S12, S13, S14) are used for the
read-from-memory half and the last four state (S21, S22, S23,
S24) for the write-to-memory half of the transfer .

IOR and MEMW (or MEMR

Idle Cycle

Special software commands can be executed by the
82C37A in the Program Condition. These commands are
decoded as sets of addresses with
commands do not make use of the data bus. Instructions
include Set and Clear First/Last Flip-Flop, Master Clear,
Clear Mode Register Counter, and Clear Mask Register.

CS, IOR, and IOW. The

Active Cycle

When the 82C37A is in the Idle cycle, and a software
request or an unmasked channel requests a DMA service,
the device will issue HRQ to the microprocessor and enter
the Active cycle. It is in this cycle that the DMA service will
take place, in one of four modes:

Single Transfer Mode - In Single Transfer mode, the device
is programmed to make one transfer only. The word count
will be decremented and the address decremented or
incremented following each transfer. When the word count
“rolls over” from zero to FFFFH, a terminal count bit in the
status register is set, an
channel will autoinitialize if this option has been selected. If
not programmed to autoinitialize, the mask bit will be set,
along with the TC bit and

DREQ must be held active until DACK becomes active. If
DREQ is held active throughout the single transfer, HRQ will
go inactive and release the bus to the system. It will again go
active and, upon receipt of a new HLDA, another single
transfer will be performed, unless a higher priority channel
takes over. In 8080A, 8085A, 80C88, or 80C86 systems, this
will ensure one full machine cycle execution between DMA
transfers. Details of timing between the 82C37A and other
bus control protocols will depend upon the characteristics of
the microprocessor involved.

EOP pulse is generated, and the

EOP pulse.

When no channel is requesting service, the 82C37A will
enter the idle cycle and perform “SI” states. In this cycle, the
82C37A will sample the DREQ lines on the falling edge of
every clock cycle to determine if any channel is requesting a
DMA service.

Note that for standby operation where the clock has been
stopped, DMA requests will be ignored. The device will
respond to
microprocessor to write or read the internal registers of the
82C37A. When
enters the Program Condition. The CPU can now establish,
change or inspect the internal definition of the part by read­ing from or writing to the internal registers.

The 82C37A may be programmed with the clock stopped, pro­vided that HLDA is low and at least one rising clock edge has
occurred after HLDA was driven lo w, so the controller is in an SI
state. Address lines A0-A3 are inputs to the device and select
which registers will be read or written. The IOR and IOW lines
are used to select and time the read or write operations. Due to
the number and size of the internal registers, an internal flip-flop
called the First/Last Flip-Flop is used to generate an additional
bit of address. The bit is used to determine the upper or lower
byte of the 16-bit Address and Work Count registers. The flip­flop is reset by Master Clear or RESET. Separate software
commands can also set or reset this flip-flop.

CS (chip select), in case of an attempt by the

CS is low and HLDA is low, the 82C37A

Block Transfer Mode - In Block Transfer mode, the device
is activated by DREQ or software request and continues
making transfers during the service until a TC, caused by
word count going to FFFFH, or an external End of Process
(

EOP) is encountered. DREQ need only be held active until
DACK becomes active. Again, an Autoinitialization will occur
at the end of the service if the channel has been
programmed for that option.

Demand Transfer Mode - In Demand Transfer mode the
device continues making transf ers until a TC or e xternal EOP is
encountered, or until DREQ goes inactive. Thus, transfer may
continue until the I/O device has exhausted its data capacity.
After the I/O device has had a chance to catch up, the DMA
service is reestablished by means of a DREQ. During the time
between services when the microprocessor is allowed to oper­ate, the intermediate values of address and word count are
stored in the 82C37A Current Address and Current Word
Count registers. Higher priority channels may intervene in the
demand process, once DREQ has gone inactive. Only an EOP
can cause an Autoinitialization at the end of service. EOP is
generated either by TC or by an e xternal signal.

Cascade Mode - This mode is used to cascade more than
one 82C37A for simple system expansion. The HRQ and
HLDA signals from the additional 82C37A are connected to
the DREQ and DACK signals respectively of a channel for

4-197

82C37A

the initial 82C37A.This allows the DMA requests of the
additional device to propagate through the priority network
circuitry of the preceding device. The priority chain is
preserved and the new device must wait for its turn to
acknowledge requests. Since the cascade channel of the
initial 82C37A is used only for prioritizing the additional
device, it does not output an address or control signals of its
own. These could conflict with the outputs of the active chan­nel in the added device. The initial 82C37A will respond to
DREQ and generate DA CK but all other outputs except HRQ
will be disabled. An external

EOP will be ignored by the initial

device, but will have the usual effect on the added device.
Figure 3 shows two additional devices cascaded with an

initial device using two of the initial device’s channels. This
forms a two-level DMA system. More 82C37As could be
added at the second level by using the remaining channels
of the first level. Additional devices can also be added by
cascading into the channels of the second level devices,
forming a third level.

2ND LEVEL

80C86/88

MICRO-

PROCESSOR

1ST LEVEL

HRQ
HLDA

INITIAL DEVICE

82C37A

DREQ
DACK

DREQ
DACK

HRQ
HLDA

HRQ
HLDA

82C37A

82C37A

Autoinitialize - By setting bit 4 in the Mode register, a

channel may be set up as an Autoinitialize channel. During
Autoinitialization, the original values of the Current Address
and Current Word Count registers are automatically restored
from the Base Address and Base Word Count registers of
the channel following

EOP. The base registers are loaded
simultaneously with the current registers by the micropro­cessor and remain unchanged throughout the DMA service.
The mask bit is not set when the channel is in Autoinitialize
mode. Following Autoinitialization, the channel is ready to
perform another DMA service, without CPU intervention, as
soon as a valid DREQ is detected, or software request
made.

Memory-to-Memory - To perfor m block moves of data from
one memory address space to another with minimum of
program effort and time, the 82C37A includes a memory-to­memory transfer feature. Setting bit 0 in the Command
register selects channels 0 and 1 to operate as memory-to­memory transfer channels.

The transfer is initiated by setting the software or hardware
DREQ for channel 0. The 82C37A requests a DMA service
in the normal manner. After HLDA is true, the device, using
four-state transfers in Block Transfer mode, reads data from
the memory. The channel 0 Current Address register is the
source for the address used and is decremented or
incremented in the normal manner. The data byte read from
the memory is stored in the 82C37A internal Temporary reg­ister. Another four-state transfer moves the data to memor y
using the address in channel one’s Current Address register
and incrementing or decrementing it in the normal manner.
The channel 1 Current Word Count is decremented.

ADDITIONAL

DEVICES

FIGURE 3. CASCADED 82C37As

When programming cascaded controllers, start with the first
level device (closest to the microprocessor). After RESET,
the DACK outputs are programmed to be active low and are
held in the high state. If they are used to drive HLDA directly,
the second level device(s) cannot be programmed until
DACK polarity is selected as active high on the initial device.
Also, the initial device’s mask bits function normally on
cascaded channels, so they may be used to inhibit second­level services.

Transfer Types

Each of the three active transfer modes can perform three dif­ferent types of transfers. These are Read, Wr ite and Verify.
Write transfers move data from an I/O device to the memor y
by activating MEMW and IOR. Read transf ers mo ve data from
memory to an I/O device by activating MEMR and IOW.

Ver ify transfers are pseudo-transfers. The 82C37A operates
as in Read or Write transfers generating addresses and
responding to
control lines all remain inactive. Verify mode is not permitted
for memory-to-memory operation. READY is ignored during
Verify transfers.

EOP, etc., however the memory and I/O

When the word count of channel 1 decrements to FFFFH, a
TC is generated causing an

EOP output, terminating the
service, and setting the channel 1 TC bit in the Status
register. The channel 1 mask bit will also be set, unless the
channel 1 mode register is programmed for autoinitialization.
Channel 0 word count decrementing to FFFFH will not set
the channel 0 TC bit in the status register nor generate an
EOP, nor set the channel 0 mask bit in this mode. It will
cause an autoinitialization of channel 0, if that option has
been selected.

If full Autoinitialization for a memory-to-memory operation is
desired, the channel 0 and channel 1 word counts must be
set to equal values before the transfer begins. Otherwise, if
channel 0 underflows before channel 1, it will autoinitialize
and set the data source address back to the beginning of the
block. If the channel 1 word count underflows before channel
0, the memory-to-memory DMA ser vice will terminate, and
channel 1 will autoinitialize but channel 0 will not.

In memory-to-memory mode, Channel 0 may be
programmed to retain the same address for all transfers.
This allows a single byte to be written to a block of memory.
This channel 0 address hold feature is selected by setting bit
1 in the Command register.

The 82C37A will respond to external

EOP signals during
memory-to-memory transfers, but will only relinquish the
system busses after the transfer is complete (i.e. after an

4-198