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TR-0017-E
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HARRIS TR-0017-E RX IF

Maintenance Manual
MM101886V1 R1A
21.4 MHz RECEIVER IF MODULE
12.5/25 kHz CHANNEL SPACING CB101128V1
TABLE OF CONTENTS
Page
1.0 SPECIFICATIONS................................................................................................................................................. 3
2.0 DESCRIPTION ...................................................................................................................................................... 4
3.0 CIRCUIT ANALYSIS............................................................................................................................................ 5
3.3 INTEGRATED CIRCUIT AGC AMPLIFIER................................................................................................... 5
3.5 AUDIO AMPLIFIER ......................................................................................................................................... 6
3.6 SQUELCH.......................................................................................................................................................... 7
3.6.1 Buffer Amplifier ............................................................................................................................................. 7
3.6.2 Bandpass Filter ............................................................................................................................................... 8
3.6.3 Noise Detector ................................................................................................................................................ 8
3.6.4 DC Amplifier.................................................................................................................................................. 8
3.6.5 Schmitt Trigger............................................................................................................................................... 8
3.7 FAULT DETECTORS ....................................................................................................................................... 8
3.9 ADDRESS DECODER ......................................................................................................................................9
4.0 MAINTENANCE................................................................................................................................................. 10
4.1 RECOMMENDED TEST EQUIPMENT......................................................................................................... 10
4.2 ALIGNMENT PROCEDURE.......................................................................................................................... 10
4.3 CRYSTAL FILTER TUNING ......................................................................................................................... 11
4.3.1 Tuning FL1 and FL2..................................................................................................................................... 11
4.3.2 Tuning FL3 and FL4..................................................................................................................................... 11
4.4 AUDIO AND DATA OUTPUT ADJUSTMENTS.......................................................................................... 11
4.5 TROUBLESHOOTING.................................................................................................................................... 11
5.0 ASSEMBLY DIAGRAM..................................................................................................................................... 13
6.0 PARTS LIST ........................................................................................................................................................ 14
7.0 IC DATA .............................................................................................................................................................. 23
8.0 OUTLINE DIAGRAM......................................................................................................................................... 30
9.0 SCHEMATIC DIAGRAM ................................................................................................................................... 31
NOTE
This device made under license under one or more of the following US patents: 4,590,473; 4,636,791; 5,148,482; 5,185,796; 5,271,017; 5,377,229.
NOTE
The voice coding technology embodied in this product is protected by intellectual property rights including patent rights, copyrights, and trade secrets of Digital Voice Systems, Inc. The user of this technology is explicitly prohibited from attempting to decompile, reverse engineer, or disassemble the Object Code, or in any other way convert the Object Code into human-readable form.
This manual is published by M/A-COM Private Radio Systems, Inc., without any warranty. Improvements and changes to this manual necessitated by typographical errors, inaccuracies of current information, or improvements to programs and/or equipment, may be made by M/A-COM Private Radio Systems, Inc., at any time and without notice. Such changes will be incorporated into new editions of this manual. No part of this manual may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of M/A-COM Private Radio Systems, Inc.
Copyright© 2002, M/A-COM Private Radio Systems, Inc. All rights reserved.
2 MM101886V1 R1A
SPECIFICATIONS
1.0 SPECIFICATIONS
1
Item Specification
I.F. (Intermediate Frequency) 21.4 MHz Input Impedance 50 ohm l2 dB SINAD ≤-120 dBm (25 kHz); ≤-119 dBm (12.5 kHz) Adj. CH Rejection ≥85 dB (25 kHz); ≥80 dB (12.5 kHz) Image Rejection ≥100 dB Intermodulation Rejection ≥83 dB (25 kHz); ≥78 dB (12.5 kHz) Signal Displacement Bandwidth ≥2 kHz (25 kHz); ≥1 kHz (12.5 kHz) 2nd I.F. (Intermediate Frequency) 455 kHz 455 kHz Balanced Output Level 2.2 V PP per line, adjustable 2nd L.O. Frequency 20.945 MHz AF Output (J2, Pin 31C) 1 Vrms adjustable (with standard input signal) AF Output Impedance 1k ohm AF Distortion ≤3% (25 kHz); ≤5% (12.5 kHz) AF Response
10 Hz ≥-3 dB ref. 300 Hz ±1 dB ref. 1000 Hz 0 dB reference 3 kHz (25 kHz Channel) ±1.6 dB ref.
3 kHz (12.5 kHz Channel) ± 2.5 dB ref. Hum & Noise Rejection ≥55 dB (25 kHz); ≥50 dB (12.5 kHz) RSSI Output (J2, Pin 20C) 0.7 to 2.7 VDC RSSI Time Constant 5 ms SQ Threshold Sensitivity ≤-123 dBm (25 kHz); ≤-122 dBm (12.5 kHz) SQ Maximum Sensitivity ≤-110 dBm (25 kHz); ≤-109 dBm (12.5 kHz) SQ Clipping 3 kHz SQ Attack 150 ms SQ Close 250 ms SQ Output (J2, Pin 26C) 5V logic (low = squelched) Fault Output (J2, Pin 11C) 5V logic (low = fault) AGC Range 50 dB DC Supply 13.8V, 80 mA max.; 12.0V, 65 mA max.
1
These specifications are intended to be used by the service technician during servicing. Refer to the appropriate
Specification Sheet for the complete Specification.
MM101886V1 R1A 3
DESCRIPTION
2.0 DESCRIPTION
The MASTR III Receiver IF Module 19D902783G7/G11 provides amplification and demodulation of the 21.4 MHz Intermediate Frequency (IF) signal as well as Automatic Gain Controlled (AGC) 455 kHz outputs to the DSP Modem module(Figure 1 - 21.4 MHz Receiver IF Module). The IF Module also includes the receiver squelch circuitry. However, it does not include de-emphasis or squelch audio gating circuits. Figure 2 –
21.4 MHz IF Module Block Diagram shows the functional operation of the IF Module.
The IF Module circuitry contains the following:
• A 50 ohm input impedance IF Amplifier
• A chain of four crystal filters and IF amplifier
A two stage AGC amplifier
•
A two stage balanced output IF amplifier
•
• An integrated circuit containing a crystal oscillator, mixer, limiter, and quadrature
detector
• A variable gain AF amplifier
• A squelch circuit
• A fault detector circuit
• An integrated circuit voltage regulator
• An address decoder
Figure 1 - 21.4 MHz Receiver IF Module
4 MM101886V1 R1A
3.0 CIRCUIT ANALYSIS
CIRCUIT ANALYSIS
3.1
3.2

INPUT AMPLIFIER NETWORK

The input amplifier consisting of transistor Q1 and transformer TX1, provides a 50 ohm load for the receiver IF module.
Capacitor C1 provides AC coupling and a DC block on the input line (J1). This DC block protects the module in the event of a failure in a preceding module.
Capacitor C1 and inductor L1 are series-resonant at 21.4 MHz and provide a low­impedance path from J1 to amplifier transistor Q1. Capacitor C2 and inductor L2 are parallel-resonant at 21.4 MHz and provide a path to the 50-ohm load, resistor R1, for mixer products other than 21.4 MHz.

CRYSTAL FILTERS, IF AMPLIFIER

Crystal Filters FL1, FL2, FL3 and FL4, transistor Q2 circuit, and associated circuitry provide IF filtering and amplification at 21.4 MHz. Filters FL1 and FL2 are two pole crystal bandpass filters centered at 21.4 MHz with a typical combined 6 dB bandwidth of ±7.0 kHz. The loss of FL1 and FL2 combined is typically between 2.5 and 3.5 dB. When combined, the filter set has associated matching networks to match the combination to a 50-ohm input and output impedance. FL3 and FL4 are matched to a 50-ohm input impedance and a 470 ohm output impedance. The FL1 and FL2 pair is specified to have especially good intermodulation performance to meet the overall requirements for the module.
3.3

INTEGRATED CIRCUIT AGC AMPLIFIER

The first two stages of AGC Amplifier U100 consist of two IF amplifiers whose gain can be controlled with an AGC voltage. These two amplifiers are connected in cascade to combine their gains. The combined voltage gain varies from about 35 dB at an AGC voltage of 3.5 VDC down to about –25 dB at an AGC voltage of <1.5 VDC. The AGC voltage is supplied by the DSP Modem module. In the two level FM mode, when no DSP modem is present, the AGC voltage is set to a fixed voltage of 3.5 volts by voltage divider resistors R139 and R137 to set the cascaded AGC amplifier gain to maximum. The output of the second IF amplifier in U100 feeds the 21.4 MHz IF signal to the input of U101 through a matching network consisting of inductor L101 and capacitor C123. The matching network matches the output impedance of the second IF amplifier in U100 to resistor R103.
The video amplifier has a single ended voltage gain (from the input to one output) of from 25 to 43 dB. The gain is set in this range by adjusting resistor R100. The differential gain is 6 dB higher than the single ended gain. The input of this stage comes from the IC mixer U101 output by way of 455 kHz filter FL100. Filter FL100 has a 6 dB bandwidth of ±7.5 kHz to reduce the level of adjacent channel signals passing into the DSP Modem module. The differential output of the video amplifier is routed to U105, and then to the DSP Modem module via the Backplane board.
MM101886V1 R1A 5
CIRCUIT ANALYSIS
3.4

OSCILLATOR/MIXER/DETECTOR

Integrated circuit U101 performs several functions. The 20.945 MHz crystal oscillator provides local oscillator injection to the mixer in U101. This mixer converts the 21.4 MHz IF signal to 455 kHz. Capacitors C119 and C120 are oscillator feedback capacitors and have been chosen to provide the proper capacitance for crystal Y100. The frequency can be adjusted by means of L102. The proper oscillator output level is difficult to measure directly without affecting the circuit operation. The level at TP3 should be approximately 50 mVpk (Measured using a 10 megohm, 1lpF oscilloscope probe).
The mixer is internally connected to the crystal oscillator. Pins 1 and 20 of U101 are the mixer input and output respectively. Typical mixer conversion voltage gain is approximately 12 dB. The mixer output feeds the transistor Q100 IF amplifier circuit and each analog switch, U102 and U103. The output from Q100 is routed to ceramic filter FL100. In the 12.5 kHz bandwidth mode, analog switches U102 and U103 route the 455 kHz IF through FL101 to the U101 IF amplifier input. In the 25 kHz mode, the mixer output is switched around FL101 by U102 and U103 and is then routed to the IF amplifier input. In the four level FM mode, FL101 is bypassed as in the 25 kHz two level mode. Ceramic filters FL101 and FL102 have a minimum 6dB bandwidth of 455 kHz ±6kHz.
The IF amplifier input is U101, Pin 18. The output at U101, Pin 16 is passed through an attenuator consisting of resistors R143, R144, and R145 to ceramic bandpass filter FL102, then to the limiter input at U101, Pin 14. The limiter output drives one input of the quadrature detector via capacitor C129.
3.5
A Received Signal Strength Indicator (RSSI) is provided at U101, Pin 7. This indicator signal is generated within the limiter circuitry and provides an output current proportional to the logarithm of the input signal strength. This current develops a voltage across resistor R141. The voltage varies from about 1.6 VDC for noise input, to about 2.4 VDC for a 12 dB SINAD signal, to a maximum of about 4.7 VDC for a –75 dBm IF input signal at J1. RSSI Buffer U200A provides buffering to eliminate loading effects on the RSSI line. The RSSI line will provide a constant output level above a –75 dBm IF input level, since the input to U101 is held constant by AGC from the DSP Modem module.
The quadrature detector provides a demodulated audio frequency output. One input to the detector is internally connected to the limiter and is not externally available. The output of the detector is at U101, Pin 9. Capacitor C145 provides lowpass filtering to remove 455 kHz feed-through. Ceramic resonator Y101 provides the frequency-selective component needed for FM demodulation. Y101 replaces the typical LC resonant circuit found in most quadrature detectors. In contrast to the typical LC network, Y101 requires no adjustment. In the four level FM mode, the detector output of U101 is not used. The detected audio output is derived by other circuitry in the base station.
Integrated circuit U101 general: The DC supply to U101 is provided through voltage dropping resistor Rl04 to U101, Pin 6. The voltage drop across resistor R104 is used to monitor the dc voltage on U101 for fault detection.

AUDIO AMPLIFIER

Operational amplifier U200C provides audio frequency amplification. The gain of U200C is set by associated resistors, including variable resistor R203. Resistor R203 allows adjustment of the AF output level to 1 Vrms with a standard input signal to the
6 MM101886V1 R1A
CIRCUIT ANALYSIS
21.4 MHz
AGC AMP
21.4 MH
module (1 kHz AF, 3 kHz peak deviation in the 25 kHz mode).
The typical amplifier gain is approximately 5. In the 12.5 kHz mode the standard deviation is 1.5 kHz. To provide the same 1 Vrms output, the gain is increased by shunting resistor R202 with resistor R201 by means of electronic switch U207. Operational amplifier U200B is used as a voltage regulator to provide 6 VDC for biasing U200C.
21.4 MHz IF IN
21.4 MHz FM IF
IC IN
DIPLEXER
IF AMP
IF AMP
MIXER
Q1
IF BUFFER AMP
Q100
U102
455 kHz
XTAL FILTER
FL1,FL2 Q2
455 kHz
CER FILT
FL101
WB/NB
SA605 FM IF IC
U101
455 kHz
CER FILT
FL100
U103
IF AMP
IF AMP
XTAL FILTER
FL3,FL4
BUFFER AMP
UPC3206C
U100C
455 kHz
CER FILT
FL102
RSSI
z
LIMITER
UPC3206
U100A,B
BUFER AMP
LM6172
DETECTOR
U105A
U105B
TO FM
IF IC
AGC IN FROM
DSP MODEM
+
455 kHz TO
DSP MODEM
-
AUDIO
AMP
U200C
U200A
DATA
RSSI OUT
OUT
20.945 MHz
455 kHz
DISCRIMINATOR
RSSI
BUFFER
Figure 2 – 21.4 MHz IF Module Block Diagram
3.6

SQUELCH

3.6.1 Buffer Amplifier
Buffer amplifier U200D (Refer to Schematic Diagram WD-CB101128V1, Sh. 3) is configured as a unity gain buffer amplifier. Its purpose is to provide a high input impedance in order to minimize loading of preceding circuitry.
MM101886V1 R1A 7
CIRCUIT ANALYSIS
3.6.2 Bandpass Filter
Bandpass filter U203A, together with its associated circuitry, performs the function of an audio frequency bandpass filter, centered at 6 kHz with a gain of 2. The purpose of this filter is to reject all voice frequencies and allow only demodulated noise to pass. The functioning of the squelch circuit depends upon the presence or absence of this noise. When a signal is being received, i.e. the receiver is “quiet”, the squelch circuit senses the absence of noise and unsquelches the radio.
3.6.3 Noise Detector
Noise detector U203B along with associated components are configured as an amplifier. A single +12 V dc supply powers this op-amp, therefore the output can only be positive. Because the ac noise input goes both positive and negative U203B effectively acts as a rectifier with gain. The rectified output of U203B charges capacitors C213 and C214 to a nearly constant dc voltage. (Actually the R216-C213,C214 time constant will allow a 5 Hz variation.)
3.6.4 DC Amplifier
DC amplifier U203C is configured as a basic amplifier with a gain of 5.0 in the 25 kHz mode. In the 12.5 kHz mode, the gain is increased by about 6 dB by shunting resistor R218 with resistor R219 by means of transistor switch Q201.
3.7
3.6.5 Schmitt Trigger
Schmitt trigger U203D is configured as an amplifier with positive feedback. This arrangement provides hysteresis in the output versus input characteristic. This eliminates the possibility of the squelch circuit repeatedly cutting in and out when the input signal is near a threshold. Resistors R223 and R224 act as a voltage divider to provide a 5 volt logic level output.

FAULT DETECTORS

Voltage comparators U1, U104, and U106 are configured as "window detectors," which pull the FAULT DETECT line low (approximately 0 volts) if the voltage applied falls outside the specified range (window). For example: U106C senses whether the input voltage is greater than the upper limit of the window. This limit is set by the voltage divider R128, R129, and R130 (6.75 VDC). Comparator U106D senses whether the input is less than the lower limit of the window (4.88 VDC, again set by R128, R129, and R130). Therefore, in this example the window is 4.88 VDC to 6.75 VDC. The U106C/U106D window detector circuit is used to determine whether the U200D voltage regulator output (+6 VDC) is within this range. The other window detector circuits monitor dc operating voltages on transistors Ql and Q2 and integrated circuits U100 and U101 respectively.
Resistors R131 and R133 comprise a voltage divider to provide a 5 V logic level output. Also, these resistors act as a pull-up for the open collector comparators. A fault is indicated when the output drops to zero.
Diode Dl00 and transistor Q101 monitor the output of the 8 V regulator. Dl is a 8.2 Volt Zener diode. If the regulator output voltage should rise above 8.9 V (8.2 + 0.7 base-
8 MM101886V1 R1A
CIRCUIT ANALYSIS
emitter drop) Q101 will turn on and a fault will be indicated. Transistors Q3 and Q4 are drivers for the front panel LED D2. These are powered from the +13.8VDC supply. Therefore, if the 8V regulator opens, a fault will still be indicated.
3.8
3.9
3.10

VOLTAGE REGULATORS

8V regulator U201 is a monolithic integrated circuit voltage regulator providing 8 VDC (+8V). This powers all 8-volt circuitry in the module with the exception of U100 and Q100. A second 8 volt regulator, U208, supplies 8 VDC (+8VB) to U100 and Q100.
5V regulator U202 is a monolithic integrated circuit voltage regulator that provides 5VDC to U100, U204, U205, and U206. This regulator operates from the 8 VDC provided by U201.

ADDRESS DECODER

The address decoder circuit consists of binary-to-octal converter U204, quad or-gate U205, and eight bit shift register U206.
When a low (0) is present on the A0 line, and a high (1) on the A1 and A2 lines, U204, Pin 9 provides a low to U205A and U205B. When there is a clock input to U205A and an enable input to U205B, the output of U250C provides a latch clock input to U206, Pin 12, and U205A provides a shift clock input to U206, Pin 11. When U206 is enabled, it detects the data on the DATA input at Pin 14. Internal flip-flops latch the data to hold the output state on Pin 15. Depending on the data, U206, Pin 15 is either high for the narrowband (12.5 kHz) mode or low for the wideband (25 kHz) mode. A “high” is a voltage greater than 3.5 VDC, and a “low” is a voltage less than 1.0 VDC.

BUFFER AMPLIFIER U105

Operational amplifier U105 amplifies the 455kHz output from the video amplifier in U100 to a maximum level of 2.2 V peak-to-peak. The differential output of U105 is routed to J2, Pins A31 and A32. The differential signal passes through the backplane board to the DSP Modem module. Buffer amplifier U105 has a voltage gain of approximately 2.
MM101886V1 R1A 9
MAINTENANCE
4.0 MAINTENANCE
4.1
4.2

RECOMMENDED TEST EQUIPMENT

The following test equipment is required to test the IF Module
1. FM Signal Generator; HP 8640B, HP 8657A, or equivalent
2. AF Generator or Function Generator
3. Audio Analyzer; HP 8903B, HP 339A, or equivalent
4. Oscilloscope
5. Frequency Counter; Racal-Dana 9919 or equivalent
6. DC Meter for troubleshooting
7. Power Supply; 13.8 VDC @ 180 mA
8. Power Supply; 12 VDC @40 mA
9. M/A-COM Test Box TS101285V11

ALIGNMENT PROCEDURE

1. Apply 13.8 VDC and 12 Vdc supplies to the IF module.
2. Verify 13.8 VDC current consumption is between 55 and 80 mA, and 12 VDC
current is between 45 and 65 mA.
NOTE
The currents cannot be measured directly when the TS11285V11 test box is used. The currents can be determined by measuring the voltage drop across L201 and L202 on the Receiver IF printed wire board and the resistance of each coil. The current can be calculated with the following formula:
I = V
drop/Rcoil
3. Set the AGC switch on the test box to "HIGH."
4. Verify fault output is 0 to 0.5 VDC and front panel LED is off.
5. Apply a standard input signal to the module input (-75 dBm, 21.4 MHz signal
modulated with 1 kHz AF, 3 kHz peak deviation).
6. Monitor TP5 with a high-impedance probe connected to the frequency counter.
Adjust inductor L102 for a reading of 455 kHz ± 100 Hz.
7. Set variable resistor R203 for 1 Vrms ±3% at module output (pin 31C on 96 pin
connector J2).
10 MM101886V1 R1A
MAINTENANCE
4.3

CRYSTAL FILTER TUNING

4.3.1 Tuning FL1 and FL2
1. Connect test equipment as shown in Fig. 10.1.
2. Connect the high impedance probe to either side of resistor R152.
3. Set the span of the network analyzer to 20 kHz, and the center frequency to 21.4
MHz.
4. Set the analyzer RF output level to obtain –75 dBm at the input of the module.
5. Adjust C9, C12, and C17 for maximum response at 21.4 MHz.
4.3.2 Tuning FL3 and FL4
1. Adjust C24, C29, and C36 for maximum response at 21.4 MHz.
2. The 6 dB bandwidth displayed on the network analyzer shall be between fc +/- 6.1
and fc +/- 7.3 kHz. The peak-to-valley ripple shall be less than 1 dB.
3. If the requirements of step 2 are not met, adjust C9, C12, C17, C24, C29, and C36 as
needed until the requirements are met.
The bandwidth is controlled primarily by C12 and C29.
NOTE
4.4
4.5
4. Set the squelch pot on the test fixture to maximum (maximum means to set the wiper
for maximum signal at the Sq-Arm terminal)

AUDIO AND DATA OUTPUT ADJUSTMENTS

1. In the 25 kHz mode, apply a standard input signal (-75 dBm, 21.4000 MHz signal
modulated with a 1kHz Audio Frequency (AF), 3kHz peak deviation) to the module IF input. Turn the FM modulation off. Monitor TP5 with a high impedance probe connected to the frequency counter. Adjust L102 for a reading of 455 kHz ±100 Hz.
2. Turn the RF generator FM modulation on. Set R203 for 1.0 Vrms ±3% AF output at
module output (Pin 31C on 96 pin connector, Pin 52).
3. Remove the FM modulation from the test signal. Monitor the 455kHz+ jack on the
test box with an oscilloscope using a high-impedance probe. Adjust R100 for a
2.2±0.1 volts peak-to-peak level. The 455 kHz-jack shall have a level of 2.2 ± 0.2 V peak-to-peak.

TROUBLESHOOTING

When troubleshooting the module, it is most convenient if the standard test fixture is used. The following conditions are with the module in the 25 kHz mode. This can be set up using a PC with the necessary software connected to the test box. Alternatively, a wire link can be soldered between pads H1 and H2 on the PC board.
MM101886V1 R1A 11
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