Harris HSP50210EVAL, HSP50110EVAL User Manual
SEMICONDUCTOR
USER’s MANUAL
April 1996
HSP50110/210EVAL
DSP Demodulator Evaluation Board
Features
• Evaluation Kit for the HSP50110 Digital Quadrature
Tuner and the HSP50210 Digital Costas Loop
• PSK Demodulator Board for Rapid Prototyping
• Interfaces with HI5703 A/D Evaluation Boards for
Analog Inputs
• Interfaces to PC Serial Port
• DOS Based Control/Status Software
• HSP43124 Serial FIR Filters for Custom Filtering
• SERINADE FIR Filter Design Software
• Power and RS232 Cables Supplied
Applications
• Prototyping Tool for PSK Communication Receivers
• PSK Demodulators from 1 KBPS to 2.5 MBPS
• Bit Synchronizers
• Digital Downconversion
• Narrowband Tracking Filters
Description
Evaluation Kit
The HSP50110/210EVAL kit consists of a circuit board, a
Control/Status software program, the SERINADE™ FIR filter
development software, and interface cables. The kit provides
the necessary tools to evaluate the HSP50110 Digital
Quadrature Tuner , the HSP43124 FIR Filter and the HSP50210
Digital Costas Loop integrated circuits. The evaluation kit is
designed as a drop in prototype PSK demodulator for digitized
(A/D converted) IF communications applications. The circuit
board accepts an input signal of up to 10 bits of I and Q
samples and recovers baseband I/Q data and symbol clock.
Analog IF signals can also be processed by inserting an
HI5703 A/D evaluation board between the analog source and
the HSP50110/210EV AL circuit board.
Circuit Board
Figure 1 illustrates the major functions of the evaluation circuit
board. The circuit board is a 3U x 160mm VME/Eurocard form
factor with dual 96 pin I/O connectors. The connector pinouts
conforms to the VME P2 connector pinout (i.e. power pin
positions located on the middle row and I/O pin positions
located on the outer rows). Data enters the board on the P1 96
pin plug connector and is routed through the HSP50110 Digital
Quadrature Tuner to the HSP50210 Digital Costas Loop. Data
leaves the board through the P2 plug connector. For
applications requiring custom filtering, the HSP43124 Serial I/O
FIR Filter can be inserted in the data path prior to the Digital
Costas Loop. An on-board microcontroller , a Motorola 68HC11,
provides a control and status interface to the serial port of a
Personal Computer (PC) running the Control/Status software
program. The microcontroller EPROM contains the Motorola
monitor program which provides the serial interface to the PC.
Test connectors are provided at ke y signal and control locations
in the demodulator circuit.
Functional Block Diagram
JP1 JP2 JP3
HSP43124 (U4)
96 PIN
CONNECTOR
P1
IF OR BASEBAND
SAMPLED DATA
JP9
JP7
JP6
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
© Harris Corporation 1996
Copyright
SERINADE™ is a trademark of Harris Corporation.
RS232
CONFIGURE/CONTROL
HSP50110
DIGITAL
QUADRATURE
TUNER
(U1)
MICROCONTROLLER
MICROCONTROLLER
SERIAL I/O FIR FILTER
HSP43124 (U5)
SERIAL I/O FIR FILTER
DOWNCONVERTED
SAMPLED DATA
68HC11
(U12)
FIGURE 1.
1
8K x 8 RAM
(U13)
JP4 JP5
HSP50210
DIGITAL
COSTAS
LOOP
(U7)
I AND Q BASEBAND
DATA SYMBOLS
SERIAL I DATA
CLOCK
GENERATOR/BUFFER
(U2 AND U3)
File Number 4149
P2
JP8
HSP50110/210EVAL
Appendices A through H contain detailed information about
Circuit Board Layout, Initial Jumper Settings, Connector Pin
Assignments, Test Header Pin definitions, Detailed Schematics, Parts List, Memory Maps and a Descriptive File List.
Control/Status Software Program
The Control/Status software program, written for DOS based
PC’s, is included in the evaluation kit. This software supports
operation of the evaluation circuit board in basic PSK
demodulator and phased locked loop (PLL) configurations.
The menu driven software program allows the user to select
a variety of demodulator and data path configurations. It calculates demodulator/PLL configuration data based on the
user menu selections, downloads configuration data to the
evaluation circuit board and displays operational status. The
calculated configuration data are the register values for the
IC’s on the evaluation board. This data is downloaded to the
evaluation circuit board microcontroller using the COM1 or
COM2 serial port on the PC. Status is read from circuit
board registers using the same serial interface and displayed on the computer screen. The downloaded configuration data is available in a text file to facilitate editing, printing,
or exporting. Additionally, the software can configure the
HSP43124 FIR filter by importing .RPT files generated using
SERINADE, a Harris filter design application.
The Control/Status software MAIN MENU offers six submenus for various configuration selections and three command actions. The menu tree is illustrated in Figure 2.
The six configuration submenus are:
• Data Path/Modulation Setup Menu
• Carrier Tracking Loop Setup Menu
• Bit Synchronization Loop Setup Menu
• Acquisition/Tracking Setup Menu
• Configure Hardware Menu
• Generate Output Files
The three command actions are:
• Load Configuration File
• Save Configuration File
• Exit
A typical operational sequence is:
A. Load Configuration File.
Executing this MAIN MENU item brings up a screen with the
current file name and requests the name of the file to be
loaded. Once the new filename name is entered, this command
loads the configuration setup and returns to the MAIN MENU
screen. This command allows the user to select a previously
saved configuration file f or display, review and editing.
B. Edit Configuration File.
This is done by sequencing through each of the configura-
tion submenus and adjusting the parameters for the desired
hardware configuration.
- The DATA PATH/MODULATION SETUP MENU is used
to select clock rates, modulation type, filtering, signal
levels, SNR range and I/O formats.
- The CARRIER TRACKING LOOP SETUP MENU is
used to select loop bandwidth, loop filter order, damping
coefficient, sweep rate, and limits for both Carrier acquisition and tracking.
- The BIT SYNC LOOP SETUP MENU is used to select
loop bandwidth, loop filter order, damping coefficient,
and limits for both Bit Timing tracking and acquisition.
- The ACQUISITION AND TRACKING SETUP MENU is
used to select lock detection integration time, lock
detection thresholds and other acquisition and tracking
parameters.
C. Save Configuration File
Executing this MAIN MENU item brings up a screen with the
current file name and a request for a filename to be saved.
Once the new filename name is entered, this command
stores the configuration setup to the new file.
MAIN MENU
(6) SAVE CONFIGURATION FILE
(5) LOAD CONFIGURATION FILE
(1) (2) (3) (4) (7) (8)
DATA PATH/
MODULATION
SETUP MENU
ENTER
(1)
VALUE
MENU
ENTER
(27)
VALUE
MENU
NEW
NEW
CARRIER BIT SYNC
TRACKING LOOP
SETUP MENU
ENTER
(1) (1) (1) (1)
(15) (8) (10) (5)
NEW
VALUE
MENU
ENTER
NEW
VALUE
MENU
FIGURE 2. MENU TREE FOR THE CONTROL/STATUS SOFTWARE
LOOP
SETUP MENU
ENTER
NEW
VALUE
MENU
ENTER
NEW
VALUE
MENU
(9) EXIT
ACQUISITION
AND
TRACKING
SETUP MENU
ENTER
NEW
VALUE
MENU
ENTER
NEW
VALUE
MENU
GENERATE CONFIGURE
OUTPUT FILES
REVIEW MENU
2
HARDWARE
MENU
ENTER
NEW
VALUE
MENU
ENTER
NEW
VALUE
MENU
HSP50110/210EVAL
D. Generate Output Files
This command will generate a number of intermediate files
which contain the register values for the IC’s on the evaluation
circuit board. Four of the files, IFIRCOEF.ARY, IFIRREG.ARY,
QFIRCOEF.ARY and QFIRREG.ARY, contain FIR specific configuration and coefficient data. One additional file has a suffix of
.ARY, and the prefix of the last saved configuration filename. It
contains the configuration data for the Digital Tuner and Digital
PLL chips.
E. Configure Hardware
This command accesses a menu called the HARDWARE
INTERFACE MENU. The menu allows selection of full initialization, loading of only the HSP50110 and HSP50210 IC’s,
loading of only the FIR filters, or changing only one specific
register. Full initialization should be selected the first time the
evaluation board is configured. Selection of items 1 - 5 will
create a number of .S files that transfer the configuration
data to the microcontroller on the evaluation circuit board
and call microcontroller subroutines that load the data into
the IC’s on the evaluation board.
D. Display Status
This command in the HARDWARE INTERFACE MENU config-
ures the PC screen to display a variety of status information.
Should further adjustment in the configuration be required, a
partial hardware download can be done using the same process and using a command item other than Full Initialization
in the Hardware Interface menu.
For a detailed listing of the every Menu screen, with selection item definitions, refer to Appendix I.
Configuration/Test Headers
Ten dual row test headers located on the evaluation circuit
board are used to monitor signals and set control pins. The
pin assignments for each of these headers are found in
Appendix D. Headers JP1, 3, and 5 contain the data path signals for monitoring the input and output busses of the
HSP50110 and HSP50210. Input pins for the HSP50110 hav e
pull down resistors. Headers JP2 and JP4 contain the I/O signals for the HSP50110/210 that are not in the data path. JP2
also selects the clock source for the board. Header JP6 contains the microcontroller control signals. A microprocessor
RESET function can be implemented by installing a “normally
open” push button switch across pins 9 and 10 of JP6. Header
JP7 contains the RS232 connection to the 68HC11 microcontroller. Header JP8 contains the HSP50210 output I data at
RS232 levels. Header JP9 allows monitoring of the microcontroller busses. JP10 contains +5VDC and ground.
Typical Evaluation Configuration
Figure 3 identifies the equipment configuration in a typical
performance evaluation setup. A test data stream is generated in the Bit Error Rate Tester (BERT) and used by the
modulator to generate a modulated IF signal. Noise and
other signal impairments are summed with the IF signal, filtered, then digitized by an A/D converter. The digitized IF
signal is routed to the circuit board. From the evaluation
board, recovered clock and data are returned to the BERT
for calculation of BER performance. A computer is connected via RS232 for control and status of the circuit board.
A logic analyzer is shown for viewing real time display of the
I/Q constellations, filter outputs, or error detector outputs of
the HSP50210 during operation.
Getting Started
Evaluation Circuit Board Configuration and Set Up
1. ___ Connect the serial cable, provided in the e valuation kit,
to JP7 on the evaluation board.
2. ___ Connect the DB-9 end of the serial cable to the COM
port on the PC.
3. ___ Connect +5 VDC to the ev aluation board at J1, using
the cable provided in the kit. The lead with the white
stripe is the +5 VDC wire. (The board draws approximately 400mA when operated with the on board
40MHz oscillator)
4. ___ V erify that JP2 has pin 29 jumpered to pin 30, as well
as pin 31 jumpered to pin 32. Installing these jumpers
utilizes the on board 40MHz oscillator. (Set the jumpers on JP2, to connect pin 29 to 30, if the on board
oscillator is not desired. Supply an external clock
source on pins 3 and 4 of JP1.)
The circuit board is ready for use when the +5 VDC is
applied to it.
ADJ. CHANNEL
NOISE SOURCE
MODULATOR
INTERFERENCE
CONTROL/STATUS
MODULATED IF COMPOSITE IF
DATA AND CLOCK
FIGURE 3. TYPICAL DEMODULATOR PERFORMANCE EVALUTAION CONFIGURATION
Σ
BERT
IF FILTER
AND A/D
DATA AND CLOCK
DIGITIZED IF
PC
RS232
HSP50110/210EVAL
EVALUATION BOARD
3
LOGIC
ANALYZER
TEST
DAT A
HSP50110/210EVAL
Requirements for the Control/Status Software Program
In order to properly operate the Control/Status software program included in the evaluation kit, the PC m ust meet the f ollowing requirements:
PC/XT/AT or 100% compatible with a minimum of 640K of
RAM
DOS Version 3.0 or higher
One serial port with 9 pin connector (COM1 or COM2)
Installing the Software
The instructions that follow will load both the
HSP50110/210EVAL and SERINADE software onto the “C”
drive of the computer. If you do not wish to run the software
from the “C” drive, consult your computer user’s manual for
operation from another drive. It is always smart practice to
backup original disks prior to installing the software on your
computer
1. ___ Insert the HSP50110/210EVAL disk in Drive A and
copy the contents of the distribution diskette to the
target directory on Drive C.
2. ___ Insert the SERINADE disk into Drive A and install the
software carefully following the instructions found on
page 1-1 and 1-2 of the SERINADE User’s Manual.
The software must be run from the new target directory
established on the C drive.
Running the Control/Status Software Program
1. ___ On the PC, change the directory to be the one where
the Control/Status software is installed.
2. ___ Start the program by typing: DEMODEVB <Enter>.
The program will prompt for which COM port to use.
3. ___ Select a COM port and press <Enter>. The MAIN
MENU screen will appear. It will look like Figure 4.
4. ___ Select item (5) and load B128RRC.CFG (or a configuration of your choice)
5. ___ Select MAIN MENU item (1), by typing: 1<Enter>. The
DATA PATH/MODULATION MENU will appear. It
should match the entries found in Figure 5.
6. ___ Make any adjustments to the parameters b y entering
the desired item number and editing it.
7. ___ Repeat Steps 5 and 6 for MAIN MENU items (2), (3),
and (4). These Menus should match the items found
in Figures 6, 7 and 8 respectively.
8. ___ Select MAIN MENU item (6) by typing 6<Enter>. This
will save the edited file.
9. ___ Select MAIN MENU item (7) by typing 7<Enter>. This
will calculate the configuration parameters and generate the.AR Y files.
10. ___ V erify that the hardware test configur ation is ready
and that the evaluation circuit board has power applied to it. (Note that menu items 1 through 7 can be
executed without the evaluation circuit board connected to the PC)
11. ___ Select MAIN MENU item (8) by typing 8<Enter>.
12. ___ Select HARDW ARE INTERFACE MENU item (1) by
typing 1<Enter>. The menu should match Figure 9.
Item (1) does a full initialization of the board. Items (2)
and (3) of the HARDWARE INTERFACE MENU,
download the selected configurations to the
HSP50110 and HSP50210, item (2), and the
HSP43124 FIRs, item (3). Item (1) should be selected whenever the board has been reset. After that,
item (2) can be selected for a faster update . Items (1)
or (3) should be selected whenever a ne w FIR coefficient file is chosen.
13. ___ Select HARDW ARE INTERFACE MENU item (4) by
typing 4<Enter>. This starts the polling of the circuit
board for status. Some of the status is only v alid when
the demod is tracking and thus, is not displayed during acquisition. The status display is toggled on and
off by repeatedly selecting item (4).
--------------------------------------------------------------------
HSP50110/210 EVALUATION BOARD SOFTWARE
--------------------------------------------------------------------
MAIN MENU
(1) Data Path/Modulation Setup
(2) Carrier Tracking Loop Setup
(3) Bit Sync Loop Setup
(4) Acquisition and Tracking Setup
(5) Load Configuration File
(6) Save Configuration File
(7) Generate Output Files
(8) Configure Hardware
(9) Exit
ENTER SELECTION:
(C) Harris Semiconductor 1995 Version 1.0
FIGURE 4. MAIN MENU SCREEN
4
HSP50110/210EVAL
-------------------------------------------------------------------
HSP50110/210 EVALUATION BOARD SOFTWARE
--------------------------------------------------------------------
DATA PATH / MODULATION MENU
Current File Name.\B128RRC
(1) Master Clock Freq. . . . . . . . . . . . . . . . . . . . . . .40000000 Hz
(2) Input Sample Rate. . . . . . . . . . . . . . . . . . . . . . .40000000 Hz
(3) Input Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gated
(4) DQT Input Samples. . . . . . . . . . . . . . . . . . . . . .Real
(5) DQT Input Format. . . . . . . . . . . . . . . . . . . . . . .Offset Bin
(6) L.O. Center Freq.. . . . . . . . . . . . . . . . . . . . . . . .+5000000 Hz
(7) Data Modulation . . . . . . . . . . . . . . . . . . . . . . . .BPSK
(8) Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128000 Hz
(9) DQT Output Rate . . . . . . . . . . . . . . . . . . . . . . .256000 Hz
(10) I.F . NBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750000 Hz
(11) DQT Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .CIC w/ comp
(12) DCL RRC Filter . . . . . . . . . . . . . . . . . . . . . . .Enabled
(13) DCL I&D. . . . . . . . . . . . . . . . . . . . . . . . . . . . .Bypassed
(14) HSP43124 . . . . . . . . . . . . . . . . . . . . . . . . . . . .Bypassed
(15) Es/No (min) . . . . . . . . . . . . . . . . . . . . . . . . . . .+0 dB
(16) Es/No (max . . . . . . . . . . . . . . . . . . . . . . . . . . .+100 dB
(17) Es/No (design). . . . . . . . . . . . . . . . . . . . . . . . .+6 dB
(18) A/D backoff (min.) . . . . . . . . . . . . . . . . . . . . .12 dB
(19) A/D backoff (max.). . . . . . . . . . . . . . . . . . . . .18 dB
(20) DCL Output Vector. . . . . . . . . . . . . . . . . . . . . -6 dBFS
(21) DQT Output Level . . . . . . . . . . . . . . . . . . . . . -12 dBFS
(22) DCL Detect. Level . . . . . . . . . . . . . . . . . . . . . -12 dBFS
(23) Slicer Threshold. . . . . . . . . . . . . . . . . . . . . . . . 0.25
(24) DQT AGC Slew Rate . . . . . . . . . . . . . . . . . . . 30 dB/sec
(25) DCL AGC Slew Rate . . . . . . . . . . . . . . . . . . .10 dB/sec
(26) AGC Limits. . . . . . . . . . . . . . . . . . . . . . . . . . .FULL RANGE
(27) Output Mux Control . . . . . . . . . . . . . . . . . . . . 7
(0) MAIN MENU
ENTER SELECTION:
--------------------------------------------------------------------
HSP50110/210 EVALUATION BOARD SOFTWARE
--------------------------------------------------------------------
BIT SYNC LOOP MENU
(1) Bit Sync Loop Upper Limit . . . . . . . . . . . . . . .+500 Hz
(2) Bit Sync Loop Lower Limit . . . . . . . . . . . . . . .-500 Hz
(3) Symbol Tracking. . . . . . . . . . . . . . . . . . . . . . . .2nd order
(4) Bit Sync Fractional Loop BW (Acq) . . . . . . . . 0.01
(5) Bit Sync Fractional Loop BW (Trk . . . . . . . . . 0.003
(6) Bit Sync Loop Damping. . . . . . . . . . . . . . . . . . 1
(7) Symbol Tracking Bits . . . . . . . . . . . . . . . . . . . .32
(8) Bit Sync Serial Output @ . . . . . . . . . . . . . . . . . Fclk
(0) MAIN MENU
ENTER SELECTION:
FIGURE 7. BIT SYNC LOOP MENU
--------------------------------------------------------------------
HSP50110/210 EVALUATION BOARD SOFTWARE
--------------------------------------------------------------------
ACQUISITION / TRACKING (LOCK DETECTION) MENU
(1) Lk Det Integ. Time (A CQ) . . . . . . . . . . . . . . . .96 symbols
(2) Lk Det Integ. Time (TRK) . . . . . . . . . . . . . . . .512 symbols
(3) Lk Det Threshold (ACQ) . . . . . . . . . . . . . . . . .40 deg.
(4) Lk Det Threshold (TRK) . . . . . . . . . . . . . . . . .43 deg.
(5) Lock Verify Cycles (TRK Integ. times). . . . . . 8
(6) False Lock / Freq Error Integ . . . . . . . . . . . . . .False Lock
(7) False Lock Detector. . . . . . . . . . . . . . . . . . . . . . Disabled
(8) False Lock Threshold . . . . . . . . . . . . . . . . . . . .45
(9) False Lock Sweep Count . . . . . . . . . . . . . . . . . 8
(10) Acquisition T ype. . . . . . . . . . . . . . . . . . . . . . .Swept
(0) MAIN MENU
ENTER SELECTION:
FIGURE 5. DATA PATH/MODULATION MENU
----------------------------------------------------------------------
HSP50110/210 EVALUATION BOARD SOFTWARE
----------------------------------------------------------------------
CARRIER TRACKING LOOP MENU
(1) Carrier Tracking Loop Upper Limit. . . . . . . . +30000 Hz
(2) Carrier Tracking Loop Lower Limit. . . . . . . . -30000 Hz
(3) Carrier Tracking. . . . . . . . . . . . . . . . . . . . . . . . 2nd order
(4) Carrier Fractional Loop BW (Acq) . . . . . . . . 0.03
(5) Carrier Fractional Loop BW (Trk. . . . . . . . . . 0.01
(6) Carrier Tracking Loop Damping . . . . . . . . . . 0.707
(7) AFC.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disabled
(8) Frequency Error Gain (Acq). . . . . . . . . . . . . . n/a Hz/Hz
(9) Frequency Error Gain (Trk) . . . . . . . . . . . . . . n/a Hz/Hz
(10) Delay in Discriminator . . . . . . . . . . . . . . . . . 0.5 baud
(11) Acquisition Sweep Rate . . . . . . . . . . . . . . . . 5 Hz/baud
(12) Carrier Tracking Bits to DQT. . . . . . . . . . . . 32
(13) Carrier Tracking . . . . . . . . . . . . . . . . . . . . . . Lead & Lag to DQT
(14) DCL Serial Output Clock (SerClk) . . . . . . . Fclk/8
(15) Carrier Serial Output @ . . . . . . . . . . . . . . . . Fclk
(0) MAIN MENU
ENTER SELECTION:
FIGURE 6. CARRIER TRACKING LOOP MENU
FIGURE 8. ACQUISITION/TRACKING (LOCK DETECTION)
--------------------------------------------------------------------
HSP50110/210 EVALUATION BOARD SOFTWARE
--------------------------------------------------------------------
HARDWARE INTERFACE MENU
(1) Full Initialization
(2) Load filename.ary Registers to Board
(3) Load filter.ary FIR coefs to Board
(4) Turn Status Display ON
(5) Change one register
(0) MAIN MENU
ENTER SELECTION:
FIGURE 9. HARDWARE INTERFACE MENU
The hardware is now configured as a 128 KBPS BPSK
demodulator with root raised cosine data filters. The Control/Status software is now configured to report status to the
screen so that you can evaluate the performance of the
demodulator configuration.
5
HSP50110/210EVAL
Advanced Evaluation Configurations
Terminal/PC With Terminal Emulation Control of
Evaluation Board
The user has the option of communicating directly with the
evaluation board microcontroller monitor program using a
“dumb terminal” or a PC with a communications program
such as Terminal under Microsoft Windows
settings are 4800 baud, 8 bits, 1 stop bit, and no parity. The
download (.DLD) files generated by the Control/Status software contain monitor commands for loading the HSP registers. A terminal emulator program can be used to send these
files to the monitor program as a text file download. Faster
transfers result when using “Line at a Time” versus other
download options because the text transfers wait only for the
prompt string “>”.
1. On reset, the monitor program sends a greeting.
2. Press enter and the monitor will return a prompt.
3. To display a help screen, send “?”.
4. To initialize the 68HC11 to communicate with the HSP
parts enter the following commands:
MM 005A
00 88 08 03 04 01
This sets up the memory map and address decoding.
The memory map for the 68HC11 is provided in Appendix G.
A list of the file types on the distribution disk with a brief
description, is provided in Appendix H.
For further information on the MC68HC11K4 microprocessor, reference the following Motorola data books:
Motorola M68HC11 Reference Manual (M68HC11RM/AD)
Motorola MC68HC11K4 Technical Data (MC68HC11K4/D)
The source code for the monitor program (BUFK4.ASM,
.S19, and .LST) is available on the Motorola’s bulletin board
for microprocessor products. It can be accessed using either
anonymous ftp to freeware.aus.sps.mot.com or via modem
at (512) 891-3733 (8 bits, 1 stop bit, no parity).
Serial Data Output at RS232 Levels
A user can read the I symbol serial data directly from the
output bus of the HSP50210 at RS232 levels using JP8-3.
JP4 must have pin 31 jumpered to pin 32 to connect the output data to RS232 driver, U8.
Using SERINADE Designed Filters
Once SERINADE has been used to synthesize a filter, it is
possible to use this filter design in the FIR filters in the
demodulator on the evaluation board. This procedure
assumes that the SERINADE .RPT files are available for
import. Version 1.1 or higher is recommended.
™
. The COM port
Root Raised Cosine Filter
Several filter coefficient files have been included on the
HSP50110/210EVAL disk because the SERINADE program
does not compute square root of raised cosine filters. These
files are provided for import into SERINADE. Select FIR
type:
Imported
SERINADE will add the control register values for the raised
cosine filter and any half band stages that you might select.
SERINADE will generate the .RPT files as before. The root
raised cosine coefficient files have been provided for alpha =
0.2, 0.35, 0.4, and 0.5 at 2X, 4X, and 8X baud rate. The
impulse response length is 8 baud intervals for all cases.
Non Demodulator Configurations
If other configurations are needed, the software can be used
to generate computed data gain, filtering, and I/O settings.
These settings can be downloaded as a file, as before, or
modified as individual register IC parameters after an initial
download.
on the SERINADE design menu screen.
Detailed Circuit Description
The reader should reference the detailed schematics,
found in Appendix E, while reading the detailed circuit
description.
Signal Path
The signal path begins with digitized IF data samples input
to the P1 connector. These data samples form a complex
data bus, 10 bits of each I and Q samples, which is routed to
the input of the HSP50110 Digital Quadrature Tuner, U1. Pull
down resistors, RZ1-3, are provided for unused inputs. If the
input sampled IF data format is offset binary and it is a real
signal (either I or Q data only), the MSB of the unused input
bus (I or Q) should be pulled up to a logic “1” to set the bus
to midscale. Because all of the P1 signals pass through test
header JP1, it can also serve as an input connector. In
addition to the P1 signals, JP1 has two HSP50110 signals,
the input enable signal DQTENI# and the output signal
DQTHI/LO. JP1 also has the AGCLVL input signal for the
68HC11 internal A/D converter. The external access to the
DQTENI# signal provided on P1 allows the HSP50110 to be
evaluated in both the gated input and interpolated input
modes. The DQTHI/LO, when externally filtered, can be
used in designing an Automatic Gain Control (AGC) circuit
around the IF A/D converter. Both the threshold and logic
sense of the DQTHI/LO signal are programmable. The
AGCLVL signal is the return path for an external analog AGC
signal. The AGCLVL signal is digitized and read by the
processor.
Microsoft Windows™ is a trademark of Microsoft Corporation.
6
HSP50110/210EVAL
The digital downconverted complex parallel b us output of the
HSP50110 Digital Quadrature Tuner is routed to the
HSP50210 Digital Costas Loop, U7. This parallel bus is also
routed through test header JP3. The baseband data ready
signal (BBDRDY#), HSP50210 input AGC signal
(DCLHI/LO), and the 68HC11 imbedded A/D input
(AGCLVL) are also provided on JP3. The BBDRDY# provides synchronization for the parts following the HSP50110.
The DCL HI/LO is provided to allow external filtering for use
of this signal in designing an AGC circuit around the A/D
converter when the HSP50110 is bypassed. The AGCLVL
signal is the return path for an external analog AGC signal.
The AGCLVL signal is digitized and read by the processor.
Test header JP2 contains the remaining output signals from
the HSP50110, control inputs for the HSP50110, and card
clock source/polarity jumpered selections.
The serial outputs of the Digital Quadrature Tuner, IBB0 and
QBB0, are routed to two HSP43124 Serial I/O filters, U4 and
U5, and then to the U7, Digital Costas Loop, serial input.
This filtered serial signal path is provided for those applications requiring special filtering beyond the Root Raised
Cosine (RRC) and Integrate & Dump (I&D) filters offered by
the HSP50210 Digital Costas Loop integrated circuit. An
octal register, U6, is provided to ensure that setup and hold
times are guaranteed up to the 45MHz maximum clock rate
of the FIR filters. Selection of signal routing to the FIR filters
is done in the DATA PATH/MODULATION MENU, item (14).
A set of .ARY files (two each for I and Q FIR filter) is generated by the program. Selecting the DATA PATH/MODULATION MENU item (14) and identifying a .RPT file, sets the
FIR filter response. The HARDWARE INTERFACE MENU
item (3) allows the download of only the FIR filter files and is
useful when only the FIR filters need to be changed.
The I and Q output busses from the HSP50210, and the high
speed output clock are routed through the test header JP5 to
the 96 pin connector, P2. When a jumper is placed between
JP-5 pins 29 and 31, the data rate clock (DATACLK) is provided on both JP5 and P2. The I/Q output enable and loop
freeze control inputs, along with the loop tracking outputs of
the HSP50210, are routed to header JP4. Pin assignments
for all connectors and headers are provided in Appendices C
and D.
Clocking
Microcontroller
An on-board microcontroller, a 68HC11, provides the control
and status of the evaluation board. It includes RAM, EPROM
(programmed with Motorola’s BUFFALO™ monitor program),
EEPROM, a serial port, address decoding, a synchronous
serial port, an A/D converter, and other features. U8 provides
the RS232 drive levels for the serial port, JP7. U13 is an 8K x 8
static RAM for 68HC11 program and data storage. U14 provides the address decoding for the HSP parts. U15 provides
additional address decoding that is brought to JP9. U9 and U10
are the power-on reset and optional switch controlled reset v oltage detectors. U11 is the 8MHz oscillator for the 68HC11. JP8
provides an RS232 port for the I channel received symbol data
stream when JP4 pins 31 and 32 are jumpered. JP6 provides
for jumpering the operating mode of the 68HC11, installing a
RESET switch, and applying 12.25V for the programming the
68HC11 EPROM.
The jumper options for JP6 are:
Pins 1-2 Description
No Jumper IRQB = 1 (Note 1)
Jumpered HSP50110 LKDET INT = IRQB
Pins 3-4 Pins 5-6 Description
Jumpered Jumpered Special HC11 Bootstrap Mode
No Jumper Jumpered Special HC11 Test Mode
Jumpered No Jumper Special HC11 Single Chip Mode
No Jumper No Jumper Expanded HC11 Mode (Note 1)
Pins 7-8 Description
No Jumper XIRQ = Program Voltage (pin 8) (Note 1)
Jumpered XIRQ = 0 (GND)
Pins 9-10 Description
No Jumper OPERATE (Note 1)
Jumpered Microprocessor RESET (temporary connec-
tion only, is required for RESET)
NOTE:
1. Indicates normal operational mode for the evaluation board
JP9 is provided for monitoring the microcontroller and provides access to the address bus, the data bus, the SPI port,
control signals, and general purpose I/O signals.
Jumpered Options
The clock associated with the digitized IF samples can be
input at P1 pin 20 if the card is configured for external clock
(JP2 header pins 29-30). If the card is configured for internal
40MHz reference clock (JP2 header pins 29-31 and 30-32),
then the 40MHz reference clock is output on P1 pin 20.
Three ACT86 gates (U3) isolate the on-board and off-board
clock signals, allow different polarities for the clocks, and
provide the 3.0V minimum V
Installing a jumper between J2-25 and 26 inverts clock for
the Digital Quadrature Tuner, the Digital PLL and the FIR Filters. Installing a jumper between J2-27 and 28 inverts the
high speed output clock.
BUFFALO™ is a trademark of Motorola.
required by the HSP parts.
IH
Power Supply Connections
The +5V input jack is J1. The +5V can be supplied from any
generic +5VDC/500mA AC/DC power adapter. A cable that
has the mating connector to J1 is provided with the ev aluation
kit for use with a standard laboratory power supply. A zener
diode provides some protection against overvoltage or polarity reversal. The J1 input is fused f or protection from e xcessiv e
current draw . V
the JP10 header, or at either the P1 or P2 connectors. The
supply pins on these 96 pin connectors match VME P2 pins
for +5V and ground and also are compatible with the supply
pins on other Harris evaluation boards. The evaluation board
draws approximately 400mA at 40MHz.
7
and GND connections can also be made at
CC
Appendix A
Circuit Board Layout
HSP50110/210EVAL
Appendix B
P1
J1
JP10
ACT04 ACT86
JP1
OSC
8Kx8 RAM
HSP50110
JP6JP7JP8JP9
OSC
ACT138ACT138
JP2
MC68HC11K4
ACT574
JP3
HSP43124
HSP50210
HSP43124
JP4
RS232
JP5
P2
Initial Jumper Settings
INITIAL JUMPER SETTINGS
FROM TO
JP2-1 JP2-2
JP2-3 JP2-4
JP2-5 JP2-6
JP2-7 JP2-8
JP2-9 JP2-10
JP2-29 JP2-30
JP4-1 JP4-2
JP4-3 JP4-4
JP4-5 JP4-6
JP4-7 JP4-8
8
Appendix C
P1 and P2 Connector Pin Assignations
HSP50110/210EVAL
P1 CONNECTOR PIN ASSIGNMENTS
PIN SIGNAL PIN SIGNAL PIN SIGNAL
A1 N/C B1 +5V C1 GND
A2 N/C B2 GND C2 N/C
A3 N/C B3 N/C C3 N/C
A4 N/C B4 N/C C4 N/C
A5 QI0 B5 N/C C5 QI1
A6 GND B6 N/C C6 QI2
A7 QI3 B7 N/C C7 QI4
A8 QI5 B8 N/C C8 QI6
A9 QI7 B9 N/C C9 QI8
A10 QI9 B10 N/C C10 GND
A11 N/C B11 N/C C11 N/C
A12 N/C B12 GND C12 N/C
A13 N/C B13 +5V C13 N/C
A14 N/C B14 N/C C14 II0
A15 II1 B15 N/C C15 GND
A16 II2 B16 N/C C16 II3
A17 II4 B17 N/C C17 II5
A18 II6 B18 N/C C18 II7
A19 II8 B19 N/C C19 II9
A20 GND B20 N/C C20 CLKIN
A21 GND B21 N/C C21 N/C
A22 GND B22 GND C22 N/C
A23 GND B23 N/C C23 N/C
A24 GND B24 N/C C24 N/C
A25 GND B25 N/C C25 N/C
A26 N/C B26 N/C C26 N/C
A27 N/C B27 N/C C27 N/C
A28 N/C B28 N/C C28 N/C
A29 N/C B29 N/C C29 N/C
A30 N/C B30 N/C C30 GND
A31 N/C B31 GND C31 N/C
A32 N/C B32 +5V C32 N/C
P2 CONNECTOR PIN ASSIGNMENTS
PIN SIGNAL PIN SIGNAL PIN SIGNAL
A1 N/C B1 +5V C1 GND
A2 N/C B2 GND C2 N/C
A3 N/C B3 N/C C3 N/C
A4 N/C B4 N/C C4 N/C
A5 BO0 B5 N/C C5 BO1
A6 GND B6 N/C C6 BO2
A7 BO3 B7 N/C C7 BO4
A8 BO5 B8 N/C C8 BO6
A9 BO7 B9 N/C C9 BO8
A10 BO9 B10 N/C C10 GND
A11 N/C B11 N/C C11 N/C
A12 N/C B12 GND C12 N/C
A13 N/C B13 +5V C13 N/C
A14 N/C B14 N/C C14 AO0
A15 AO1 B15 N/C C15 GND
A16 AO2 B16 N/C C16 AO3
A17 AO4 B17 N/C C17 AO5
A18 AO6 B18 N/C C18 AO7
A19 AO8 B19 N/C C19 AO9
A20 GND B20 N/C C20 CLKOUT
A21 GND B21 N/C C21 GPOUT
A22 GND B22 GND C22 N/C
A23 GND B23 N/C C23 N/C
A24 GND B24 N/C C24 N/C
A25 GND B25 N/C C25 N/C
A26 N/C B26 N/C C26 N/C
A27 N/C B27 N/C C27 N/C
A28 N/C B28 N/C C28 N/C
A29 N/C B29 N/C C29 N/C
A30 N/C B30 N/C C30 GND
A31 N/C B31 GND C31 N/C
A32 N/C B32 +5V C32 N/C
9
HSP50110/210EVAL
Appendix D
JP1 through JP10 Test Header Pin Assignments
JP1 TEST HEADER PIN ASSIGNMENTS
PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION
1 DQTHI/LO DQT HI/LO Signal 2 GND Ground
3 CLKIN Input Clock to Board 4 GND Ground
5 II9 I Input Bus Bit 9 (MSB) 6 II8 I Input Bus Bit 8
7 II7 I Input Bus BIT 7 8 II6 I Input Bus Bit 6
9 II5 I Input Bus BIT 5 10 II4 I Input Bus Bit 4
11 II3 I Input Bus BIT 3 12 II2 I Input Bus Bit 2
13 II1 I Input Bus BIT 1 14 II0 I Input Bus Bit 0 (LSB)
15 GND Ground 16 GND Ground
17 QI9 Q Input Bus Bit 9 (MSB) 18 QI8 Q Input Bus Bit 8
19 QI7 Q Input Bus Bit 7 20 QI6 Q Input Bus Bit 6
21 QI5 Q Input Bus Bit 5 22 QI4 Q Input Bus Bit 4
23 QI3 Q Input Bus Bit 3 24 QI2 Q Input Bus Bit 2
25 QI1 Q Input Bus Bit 1 26 QI0 Q Input Bus Bit 0(LSB)
27 GND Ground 28 GND Ground
29 DQTENI# DQT Input Enable 30 GND Ground
31 AGCLVL A/D Input to 68HC11 32 GND Ground
JP2 TEST HEADER PIN ASSIGNMENTS
PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION
1 GND Ground 2 DQTPH1 DQT Phase Shift Bit1
3 GND Ground 4 DQTPH0 DQT Phase Shift Bit 0
5 GND Ground 6 DQTCFLD DQT Center Freq Load
7 GND Ground 8 DQTOEI# DQT Output Enable I
9 GND Ground 10 DQTOEQ# DQT Output Enable Q
11 GND Ground 12 DQTLOTP DQT L.O. Test Point
13 GND Ground 14 SPH0 Bit Sync Phase Bit 0
15 GND Ground 16 SPH1 Bit Sync Phase Bit 1
17 GND Ground 18 SPH2 Bit Sync Phase Bit 2
19 GND Ground 20 SPH3 Bit Sync Phase Bit 3
21 GND Ground 22 SPH4 Bit Sync Phase Bit 4
23 GND Ground 24 SSTRB# Bit Sync Strobe
25 GND Ground 26 INVDCLK Invert Demod Clock
27 GND Ground 28 INVCKOUT Invert Output Clock
29 CLKIN Input Clock to Board 30 MSTRCLK Master Clock Node
31 DRVCLK Clock Driver 32 OSCCLK Oscillator Output
NOTE: T o input the cloc k to the board, connect pin 29 to 30; to source the clock from the on-board oscillator, connect pin 29 to 31 and pin 30 to 32.
10
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