The contents of this manual are the property of the Haemonetics Corporation.
Any information or descriptions contained in this manual may not be
reproduced and released to any of the general public, or used in conjunction
with any professional instruction without written consent of Haemonetics
Corporation, USA.
Use of any portion(s) of this document to copy, translate, disassemble or
decompile, or create or attempt to create by reverse engineering (or otherwise)
the source code from the object code of Haemonetics products is expressly
prohibited.
DisclaimerThis manual is intended as a guide to provide the user with necessary
instructions on the proper use and maintenance of certain Haemonetics
Corporation products. This manual should be used in conjunction with
instruction and training supplied by qualified Haemonetics personnel.
Any failure to follow the instructions as described could result in impaired
product function, injury to the user or others, or void applicable product
warranties. Haemonetics accepts no responsibility for liability resulting from
improper use or maintenance of its products.
Utilization of Haemonetics products may require the user to handle and
dispose of blood-contaminated material. Users must fully understand and
implement all regulations governing the safe handling of blood products and
waste, including the policies and procedures of their facility.
Handling and use of any blood products collected or stored using Haemonetics
equipment are subject to the decisions of the attending physician or other
qualified medical personnel. Haemonetics makes no warranty with respect to
such blood products.
Patient diagnosis is the sole responsibility of the attending physician or other
qualified medical personnel.
The screenshots appearing in this manual are provided for illustrative purposes
only and may differ from the actual software screens. All organization, donor/
patient, and user names in this manual are fictitious. Any similarity to the name
of an organization or person is unintentional.
P/N SM-CS5-01-EN, Manual revision: ABHaemonetics® Cell Saver® 5/5+ Service Manual
Page 3
3
Document
Updates
Trademarks and
Patents
The document is furnished for information use only, is subject to change
without notice and should not be construed as a commitment by Haemonetics
Corporation. Haemonetics Corporation assumes no responsibility or liability for
any errors or inaccuracies that may appear in the informational content
contained in this material. For the purpose of clarity, Haemonetics Corporation
considers only the most recent version of this document to be valid.
Haemonetics®, THE Blood Management Company®, and Cell Saver® are
trademarks or registered trademarks of the Haemonetics Corporation in the
United States and/or other countries.
Other product names in this document may be trademarks of their respective
proprietors and are used for identification purposes only.
Reader comments
Any comments or suggestions regarding this publication are welcomed and
should be forwarded to the attention of:
Haemonetics® Cell Saver® 5/5+ Service ManualP/N SM-CS5-01-EN, Manual revision: AB
Page 14
14Introduction
Overview
What is the
purpose of this
manual?
This service manual provides detailed information for the installation and
maintenance of the Haemonetics® Cell Saver® 5 Autologous Blood Recovery
System.
The manual includes the following:
Detailed descriptions of the device and all components
How to troubleshoot and repair any difficulties
How to properly maintain the device
Use this manual in conjunction with training supplied by qualified Haemonetics
personnel.
This manual covers device list numbers
02005-110
02005-110-EP
02005-110-EPJ
02005-220-E
02005-220-EP
P/N SM-CS5-01-EN, Manual revision: ABHaemonetics® Cell Saver® 5/5+ Service Manual
Page 15
Introduction15
Symbols
Symbols found
in this
document
Symbols found
on the device
The terms Note, Caution, and Warning are used in this manual, with the
following symbols, to emphasize certain details for the operator:
Note: Provides useful information regarding a procedure or operating
technique when using Haemonetics material.
Caution: Advises the operator against initiating an action or creating a situation which could result in damage to equipment, or impair the quality of the
blood products; personal injury is unlikely.
Warning: Advises the operator against initiating an action or creating a
situation which could result in serious personal injury to the donor, the
operator, or the blood product recipient.
The following symbols may be found on the device or device packaging:
Attention
Consult accompanying documents.
Type CF
Type CF applied part provides a particular degree of protection
against electric shock; particularly regarding allowable-leak-
age current and reliability-of-the-protective-earth connection.
Electrical and electronic equipment waste (applies to EU
only)
Dispose of the device using a separate collection method (according to EU and local regulation for waste electrical and
electronic equipment).
IPX1
Haemonetics® Cell Saver® 5/5+ Service ManualP/N SM-CS5-01-EN, Manual revision: AB
Protection against ingress vertically dripping water
Indicates that the enclosure of the device is designed to be
drip-proof, providing a higher-than-ordinary protection level
from drips, leaks, and spills.
Manufacturer
Alternating Current
Page 16
16Introduction
Fuse
Equipotentiality
Identifies the terminals, which, when connected together,
brings various parts of a system to the same potential.
Authorized representative in the European Community
Rx only (applies to USA only)
Federal (USA) law restricts the sale of the device to be included by or on the order of a physician, only.
Serial number
Catalog number
0123
ETL
Laser radiation
Shock hazard
CE Mark
General symbol for recovery/recyclable
To indicate that a material is part of a recovery/recycling process.
Note: Applicable only to those products or materials for which,
at the end of life, there is a well-defined collection route and re-
P/N SM-CS5-01-EN, Manual revision: ABHaemonetics® Cell Saver® 5/5+ Service Manual
Page 17
Introduction17
cycling process, and which does not significantly impair the effectiveness of other recycling schemes.
250 mmHg
Maximum vacuum
Pollution control mark
Pollution control mark for products containing any of the six referenced substances (Lead, Mercury, Cadmium, and so on) according to new Chinese regulations.
Storage conditions, humidity level
Storage conditions, temperature level
Storage conditions, keep dry
Fragile, handle with care
This end up
Read the instruction manual
Haemonetics® Cell Saver® 5/5+ Service ManualP/N SM-CS5-01-EN, Manual revision: AB
Page 18
18Introduction
System overview
All Haemonetics Cell Saver® Autologous Blood Recovery Systems process
whole blood salvaged from the surgical field so that it may be reinfused to the
patient. Inside a spinning processing chamber (bowl) red blood cells (RBCs)
are separated from other blood components, such as platelets and plasma,
and from debris suctioned from the surgical site. The separated RBC are then
washed with saline solution. The washed, packed RBC may then be reinfused
to the patient. The Cell Saver 5/5+ can also collect platelet rich plasma (PRP)
before surgery.
The Cell Saver 5/5+ represents the fifth generation of Cell Saver 5/5+
Autologous Blood Collection Systems from Haemonetics. The CS5/CS5+
provides the highest level of automation available in a blood salvage system.
The design goal of the CS5/CS5+ was to produce a system that would rapidly
process a large volume of salvaged blood while keeping operation simple.
Great attention was given to keeping the control panel simple while providing
the operator with constant feedback on the operation of the device.
The control-panel displays only the keys that are available to the operator.
Manual operation keys are not visible in the automatic mode.
The tubing harness uses a manifold, so that the disposable setup is faster and
easier, while the possibility of improperly installing the tubing into the valves is
eliminated. The processing chamber, a Latham bowl, is held in place with a
mechanical chuck, making installation faster and easier. The top portion of the
bowl is visible, so that the operator can monitor blood separation.
The Cell Saver 5/5+ system consists of two parts: a device and a single-use
disposable set.
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Page 19
Introduction19
The major device components are identified in Figure 1.
Reservoir holder
with level sensor
Pigtails for saline,
anticoagulant and
Control panel
Fluid deck (with
valves, air detectors,
and pump)
reinfusion bags
Centrifuge
(with bowl optics
and fluid sensors)
Cover lock
Effluent-line sensor
Waste-bag
weigher hooks
Figure 1, Haemonetics® Cell Saver® 5+ Autologous Blood Recovery System
The centrifuge holds the disposable bowl in place and spins it at high
speed. Inside the bowl, red blood cells (RBCs) are separated from other
blood components, debris, and saline.
Bowl optics monitor the spinning bowl to determine the appropriate
moment to initiate certain actions such as cell washing.
Valves control the fluid pathway of the disposable tubing set.
A pump moves fluids through the tubing set. Salvaged whole blood is
brought from the reservoir into the bowl for processing. Saline wash
solution is brought from the saline bags on the IV pole to the bowl to wash
RBCs. The final product, washed packed RBCs, is pumped to a reinfusion
bag.
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20Introduction
An effluent linesensor monitors the line from the bowl to the waste bag
to ensure that a minimum of RBC are lost and that the Wash mode is
complete.
A waste bag weigher alerts the operator when the waste bag is full.
Figure 2 identifies major disposable set components:
HAEMONETICS
IOOO
9OO
8OO
7OO
6OO
5OO
4OO
Reinfusion bag
3OO
Saline (yellow) line
2OO
IOO
MILLILITERS
(APPROXIMATE)
DO NOT USE WITH PRESSURE CUFF
To reservoir
To saline bags
Reinfusion (blue) line
Reservoir (red) line
Centrifuge bowl
Tubing manifold
10
9
8
7
6
5
4
3
2
1
Waste bag
Figure 2, Cell Saver 5/5+ disposable set
The bowl is the main disposable component. Inside the spinning bowl,
RBCs are separated from other blood components and from debris that
may have been collected along with the whole blood. The 70 ml bowl is
the blow-molded-bowl design (not shown).
A tubing manifold is installed into a keyed slot on the CS5/CS5+ deck.
The keyed slot ensures that the tubing lines are installed in the
appropriate valves. There are three lines and three corresponding valves.
(The red line leads to the reservoir, the yellow line leads to the saline
bags, and the blue line leads to the reinfusion bag.)
A waste bag holds the supernatant and waste fluids, which flow out of the
spinning bowl as the red blood cells (RBCs) are washed.
A reservoir (not shown) stores whole blood and saline, which are
collected from the surgical field. The reservoir has a gross filter, which
removes large debris. The red line of the CS5/CS5+ disposable set
attaches to the reservoir.
Two saline bags (not shown) are connected to the bag spikes on the
yellow saline line.
A reinfusion bag is connected to the blue reinfusion line. After they are
processed, washed red blood cells suspended in saline are sent to this
bag.
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Introduction21
Additional support
Many factors affect the performance of blood processing instruments, including
the functional integrity of the device, the consistency of the disposable set, and
the quality of blood salvaged.
This manual attempts to anticipate any service needs of the Cell Saver 5/5+. If
this manual does not answer your questions, call the Haemonetics Customer
Care Center at (800) 537-2802. For locations outside the U.S., contact the
Haemonetics local office.
See “Haemonetics Worldwide” on page 3 for a list of local offices.
Haemonetics® Cell Saver® 5/5+ Service ManualP/N SM-CS5-01-EN, Manual revision: AB
P/N SM-CS5-01-EN, Manual revision: ABHaemonetics® Cell Saver® 5/5+ Service Manual
Page 25
Principles of operation25
Introduction
CS5/CS5+ devices manufactured after approximately October 2000 no longer
utilize the backplane PCB (P/N 36728-00) with the personality PCB (P/N
37253-00). These PCBs are combined in the new backplane PCB (P/N 49488-
00). The CS5/CS5+Service Manual chapters (Chapter 2, "Principles of
operation", Chapter 5, "Troubleshooting"; and Chapter 6, "Disassembly")
assume this newer configuration of the backplane PCB (P/N 49488-00). For
guidance on operation, troubleshooting, or disassembly of the older versions
of PCBs, refer to prior revisions of the CS5 Service Manual or contact the
Haemonetics Customer Care Center.
Haemonetics® Cell Saver® 5/5+ Service ManualP/N SM-CS5-01-EN, Manual revision: AB
Page 26
26Principles of operation
Safety card
Safety featuresThe following safety features are designed into the Cell Saver® 5:
Electrical safety
IEC 601-1:1988 medical equipment requirements for safety
EN 601-1-2:1993 EMC compliance
Logic supply over/under voltage
Overspeed limit for centrifuge
Mechanical safety
Centrifuge/pump construction
Interlocks
Cabinet design
Protection from over/under pressure
Pump agreement (direction/speed) with device state
Function and
safety structure
Motor driver-fault detection
Continual checking of CPU status and motor/valve feedback in order
to confirm device state
The safety card addresses all aspects of pump agreement with device state
and several aspects of electrical and mechanical safety.
The following is an outline of the function and safety structure employed by the
CS5/CS5+:
A single microprocessor (μP) has control tasks for the function of the
system.
The safety system consists of an independent, hardware safety board —
CS5/CS5+ safety card.
The μP performs a self-test during T1-test (RAM, ROM, registers and
safety I/O) to verify its functionality.
The safety system is tested by the μP, before every procedure, to see
whether it can fulfill its tasks in the correct manner.
The μP and safety card read the same input signals.
The μP sends test codes to the safety card; if any disagreement occurs,
the safety card sends an error message to the μP.
Both the μP and the safety card are able to stop the function of the system
by independent shutdown paths (de-energizing motor and valves) and
initiate acoustical alarms (unsafe equipment state).
When the μP T1 and safety card tests are completed the CS5/CS5+ is
considered a one-channel system (single fault analysis).
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Page 27
Principles of operation27
Sensor
T
Theory of
operation
The safety card is a system that accepts direct CPU information as to the
device state; it independently verifies this state via a pump encoder and valve
feedback; it tests all appropriate sensor-safety limits, as defined for this state;
and if a fault condition is detected, it removes power from both pumps and
valves. Further, whenever a fault condition exists, an audible alarm is sounded
and information, as to its cause, is latched and made available to the CPU for
diagnostic purposes.
For a better understanding of how the safety card is integrated and used within
the CS5/CS5+, refer to the block diagram in Figure 3.
First, note that the upper relay, known as the safety or K1, controls the power
applied to both the valves and pumps. This relay will be opened whenever a
critical fault condition is indicated by the CPU or safety card.
The output contact of K1 is sensed and the on/off status is readable by the
CPU. At power-up and at the start of each procedure, this relay is tested by the
CPU.
The second relay is known as the pump or K2 relay and it controls the power
applied to the pumps. The safety card has exclusive control over it. The status
of this relay is also sensed and made available to both the CPU and the safety
card.
K1 and K2 will be opened whenever a safety fault is encountered by the safety
card.
est
Signals
Sensors
K2 is opened/closed for each safety card test executed at the beginning of a
procedure or when a standby (Manual/Stop) mode is required.
Fault
Summer
Drv
CPU
Relay Feedback
Drv
+28v
+
–
Safety/
Master Relay
K1
Valve
Power
Safety
+
–
Pump Relay
K2
Pump
Power
Isolated
Outputs
Card
Sensor
Relay Feedback
Figure 3, Safety card functional block diagram
Haemonetics® Cell Saver® 5/5+ Service ManualP/N SM-CS5-01-EN, Manual revision: AB
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28Principles of operation
Safetycard
state codes/
interface
requirements
Input register
The sole input port, for the safety card, is an 8-bit register (supporting read
back), which accepts state/test codes from the CPU. These codes are used by
the safety card in order to verify the device state as indicated by independent
sensors.
Whenever a new, device state (determined by valve and pump operation) is
called for, a code, representing this state, must be issued by the CPU.
This code is written to the safety card before the actual change of device state
is executed. This allows the safety card to distinguish between a normal state
advance and a state fault condition.
Data format
The 8-bit data information is partitioned into two fields. The first field consists
of 5 bits (D0 through D4) and is dedicated to command/state information. (Each
code possesses a minimum Hamming Distance of two.) The second field,
formed by the remaining bits (D5 through D7), is used to provide test signals.
A description of each field is given in Table 1.
Note: In order for the safety card to recognize the correct pump activity when
transitioning from one state to another, it will be necessary to transition through
the Pause or Standby state first (i.e., change code, because re-issued codes
are not recognized).
Table 1, Test code field
D7D6D5Test
identifier
000NulNo testing
010State testNormally during the test phase
100Beeper testTo avoid annoying beeps during
110Time base testIntended to be used to simulate a
Test description
generation of a state fault is
inhibited (replaced by a motormovement fault). This code is
used as an override to ensure
that a state fault can open the
pump relay.
test, the beeper is disabled. This
code allows a test beep and is
required in order to enter the
application phase.
safety card clock failure, it also
aids (reduces the time required)
to synchronize the watchdog
signal.
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Principles of operation29
Table 1, Test code field (Continued)
Safety
operational
sequence
D7D6D5Test
identifier
001Spare testReserved for interlock application
011Not used
111Not used
101Not used
111Not used
Test description
Input register guidelines
After a code is issued by the CPU, proper pump and valve commands should
be issued (executing the code action).
Refer to the flow chart in Figure 4 as an aid in understanding the system
interactions with the safety card.
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30Principles of operation
There are two basic phases of operation to consider for the safety card: the test
phase and application phase.
Test Phase
Application Phase
Power On Reset
Test Entry Code
Timing Verification
Relay Testing
Beeper Check
State Fault Test
Recovery Path
Application Entry Code
Watchdog, 5V Supply Pumps and
Clamps Continuously Monitored
Pause
Standby
Conc
Pump Relay
Deenergized
During Pause Interlocks May Be Tested.
**
Figure 4, Safety card test-flow diagram
**
Clear Test Checklist
*
Normal
Operation
Standby Code
Check Interlocks
*
Test Checklist
*
Sequence Tests
Allowed
WashFill
Return
“Load
*
Disposable”
Test phase
The sequence starting point is defined by entry into the test phase. This phase
is entered whenever the safety card receives a start code.
There are two ways that can happen:
At power-up, the start code is obtained by default via the bus reset signal.
During operation by direct CPU input of this code — used before initiating
a new procedure.
During this phase, the complete end-to-end testing of the safety card is
accomplished by the CPU outputting state codes and exercising sensor testlines, then verifying the pump relay response and the safety card’s output
register data.
The key differences in functionality between test and application phases are:
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Principles of operation31
Pump motion is prohibited (unless in standby) during the test phase.
Motor movement fault replaces state fault. With pump safety, thus
ensured, the CPU is free to simulate the full range of state codes
available.
As certain safety criterion require that some sensor inputs be qualified by state
(future capability), code invariance between test and application is a necessary
condition for testability.
Fault recovery (removing the alarm and closing K2), by changing sensor
levels, is only possible during the test phase.
Transition from test to application may only take place after a test done bit
is set (minimum test requirement is satisfied), while the reverse can be
initiated anytime using a start test code.
Test 1, initialization
Test 1 is a test to determine the safety card’s time-base accuracy and relaydrive capability, as well as a watchdog setup (fast sync).
Notes on watchdog generation and synchronization
Proper synchronization, of the watchdog signal to the local, safety card time
gate, requires the following:
An accurate and reliable watchdog timing-period.
Each edge of the watchdog signal must be qualified separately.
The rising edge generation must be as accurate as possible
— minimum interrupt latency and software execution overhead.
The falling edge of the watchdog signal must be reliable — qualified
by a key-lock approach that is taken to meet TUV software safety
concerns.
Ability to synchronize the issuance of the time-base test signals (code-test
field signals) with the watchdog’s rising edge.
Read loop looking for watchdog 0 to 1 transition.
After the above transition is detected, write the following two consec-
utive start test codes.
Initialization test sequences
1. Issue the start test code / test NUL.
2. If New Procedure Entry, kill watchdog signal (not present if POR)
– Relay opens; WD Flt is posted.
3. Restart watchdog and perform Sync Sequence (item 2 of Watchdog
Generation & Sync)
– Relay closes; Watchdog Fault is removed.
4. Perform time base fault test by issuing
– Relay opens; TB Flt is posted.
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32Principles of operation
5. On Watchdog rising edge issue:
– Relay opens; fault is removed.
Test 2, state fault test
For this test, various state codes are transmitted to the safety card. All codes
except pause and standby cause a selected channel to post a state fault and
open K2.
Application
phase
Design
overview
To enter this phase, the safety card must have the test done flag set, receive a
start application code from the CPU, and receive a valid state code.
Any fault (state fault only at present) encountered by the safety card during this
phase results in the opening of relays K1 and K2, activation of the audible
alarm, and the posting of this fault by the output registers.
This is a latched condition (i.e., removal of the fault has no effect on the relays,
alarm, or output registers). To reset, a new start test code must be issued or
power must be recycled.
The design of the safety card was influenced by the following observations:
The safety card must track device states because the safety-related
sensor information is qualified by state.
Direct source of device state information (state codes) is from an input
port, driven by the μP.
Indirect source of device state information is derived from pump and valve
feedback-signals (i.e., motor encoder and valve position switches).
(Indirect source circuitry must be redundant.)
The safety card design must pay strict attention to pump dynamics and μP
update rates.
End-to-end testing of the safety card must include state codes — code
invariance between test phase and application.
Therefore, a unique start sequence is mandatory.
Note: The only difference in the safety card’s usage of state codes (between test
and application phases) is whether recovery from faults is allowed.
Design should allow the testing of sensors during any safe state (pause
and standby).
Suppressor and high-voltage-control sections are required for the safety
card in order to deal with a logical supply overrange (common system
fault).
The major blocks are listed below:
Bus interface
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Principles of operation33
Timing and watchdog logic
Code/state decoder
Safety evaluation circuit description
Connectors
The CS5/CS5+ safety card connects to the backplane using two (2) pin 96 DIN
connectors, P201 and P202. The pin identifications for each of these
connectors are shown in Table 2 and Table 3 below:
Table 2, P201 pin identification
PinSignalPin SignalPi
n
1A+28V11C22B
1B+28V RTN12A22C
1C12B23A
2A+28V12C23B
2B+28V RTN13A23C
2C13B24A
3ASafe +28V13C24B
3BSafe +28V
14A24CSYSGND
RTN
3C14B25A
4ASafe +28V14C25B
4BSafe +28V
15A25C
RTN
Signal
4C15B26A
5APump +28V15C26B
5BPump +28V
16A26C
RTN
5C16B27A
6APump +28V16CSYSGND27B
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34Principles of operation
Table 2, P201 pin identification (Continued)
PinSignalPin SignalPi
n
6BPump +28V
RTN
6C17B28A
7A17C28B
7B18A28C
7C18B29A
8A18C29BSafe SHDN CH1
8B19A29CSafe SHDN CH2
8C19B30A
9A+15V19C30B
9B-15V20A30CSYSGND
9CSYSGND20B31APMP SHDN CH1
17A27C
Signal
10A+5V20C31B
10B+5V21A31CPMP SHDN CH2
10 CSYSGND21B32A
11A21C32B
11B22A32CPump RLY FDBK
Table 3, 202 pin identification
PinSignalPin SignalPinSignal
1A+5V11CBUS D022B
1BFUGE SHDN
CH1
1C+5V12BCS5/CS5+
12A/BUS RD22C
23AVALVE 1 FDBK
FUGE CVR
SW
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Principles of operation35
Table 3, 202 pin identification (Continued)
PinSignalPin SignalPinSignal
2ASYSGND12C/BUS WR23BSYSGND
2BFUGE SHDN
CH2
2CSYSGND13B24A
3A13C24B
3BVALVE3 FDBK14ABUS INT24C
3C14B25A
4ABUS A714C25B
4B15ABUS RST25C
4CBUS A615B26AIBM AEN
5ABUS A515CWatchdog26B
5B16APUMP
5CBUS A416B27AIBM BUS RDY
6ABUS A316CPUMP
13A23CVALVE2 FDBK
26CIBM A9
ENCDR A
27B
ENCDR B
6B17A27CIBM A8
6CBUS A217B28AIBM RST
7ABUS A117C28B
7B18A28C
7C18B29ASYSGND
8ABUS D718CSYSGND29B
8B19ASYSGND29CSYSGND
8CBUS D619B30A+15 V
9ABUS D519C30B
9BANVIL POS.20A30C-15V
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36Principles of operation
Table 3, 202 pin identification (Continued)
PinSignalPin SignalPinSignal
9CBUS D420B31ASYSGND
10ABUS D320C31B
10BPLATEN POS.21A31CSYSGND
10 CBUS D221B32A+5V
11ABUS D121C32B
11B22A32C+5V
The test header P203 is located near the exposed card edge. In normal
operation, its contacts are jumpered by a shunt J203. Only during board testing
of voltage thresholds is the shunt removed. The pin identification is as shown
in Table 4.
Table 4, Pin identification P203
PinSignal
1+5V
2Safe 5V
Bus interfaceThis section contains all the decoding logic, registers, buffers, and transceivers
necessary for the CPU and the safety card to communicate. It interfaces
directly with the data, address, and control signals of the advanced backplane.
Bus address decoding is provided by U40 . This PAL device detects whenever
the safety card is addressed. The address range for this board is from 230h to
23FH. The outputs of U40 are DIR (direction), /ADDREQ (safety-card access),
and /EN (enable for data bus buffer).
Lower, order addresses (A4–A0) are first buffered by U24, then decoded by
U19 . Five-chip selects, for the various safety card registers, are generated
based on the /ADDREQ, address, read, and write signals. The data bus is
buffered and directed by U28 (octal bus-transceiver).
The read-and-write lines and the watchdog signal are buffered by U24 (octal
buffer). R16/C28 and U14 are used to condition the watchdog signal, resulting
in the signal named BFWD (buffered watchdog).
Both the CPU reset-signal (BUS RST) and the IBM PC reset-signal (test port IBM RST) are conditioned and combined by U27 and U23, with filtering
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Principles of operation37
provided by RN5D/C27 and RN7B/C26. The safety card’s reset signal is
named BRST (/BRST is also available via inverter U14).
Timing and
watchdog logic
Timing signals
This section provides the three timing-signals required for the entire card’s
operation. They are SCLK, 2SCLK, and TREF.
The master clock-reference is a 5MHz TTL-square-wave signal, derived from
U12. This signal is fed to an 8-bit synchronous, up-and-down counter (U5,
configured for up counting). 2SCLK is obtained from the divide-by-four tap (U5pin3 -1.25MHz), SCLK from the divide-by-eight (U5-pin4 - 625kHz).
The divide-by-256 (U5-pin10 - 19.53kHz) tap is fed to the circuitry, comprised
by U2, U4, U6, and U10, in order to generate TREF. This is a TTL signal, which
has a period of 0.1966 seconds and a duration of 51.2 micro-seconds in the
active low state.
The role of each signal is as follows:
SCLK — Internal state clock, which defines the process update rate of the
safety card channel.
2SCLK — 2X state clock frequency, which is used for substate clock event
timing.
TREF — Defines the period for motor-speed evaluation and the base unit for
measuring time intervals.
Watchdog/time base validation
The conditioned watchdog (WDOG), is applied to U10, in order to reset the
reference time-gate logic (TB Gate).
TB gate is derived from U1, U4, and U6, in a topology identical to that used in
generating TREF.
The WDOG and TB gate-signal transitions are compared on an edge-to-edge
basis with each other by U7, U10, and U11.
To prevent a watchdog fault from being generated, the watchdog must be a
repetitive signal with a time, between rising edges, from 98.5 to 104.7
microseconds (ms). It is also required that this signal remain at a logic high for
100 ms, at a minimum.
A time-base fault will be generated whenever the TB gate is static (i.e., remains
at either a high or low logic level). This is in effect, one simulation, made during
the test phase.
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38Principles of operation
Code/state
decoders
Code processing path
The basic function of this group of circuitry is to synchronize and decode the
information transmitted to this card by the CPU.
The input/readback register is implemented by U36 and is accessed at IO
address 230h. Data supplied to this port follows one of two paths. Code
information from the least significant 5 bits is synchronized to SCLK via the dual
synchronizers U20 and U29, and then decoded by U34 — while the most
significant 3 bits, used for direct test simulation, is decoded by U33.
U25 and U18 are used to determine if a new code has been received. When a
new code is detected, a pulse, /CODE CHG, is issued. Further processing of
this pulse, by U23, U27, and U35, results in a one-shot-qualifying signal (CHG
TIMER) of approximately one second duration. This signal is used by U30 to
qualify the PUMP_RLY_FDBK (K2 status) when a stop (suspend) command is
issued. If this relay is not opened within the time-out interval, then the safe relay
(K1) is commanded to open (SAF_SHDN_CMD).
State processing path
There are three steps performed in determining device state:
1. The incremental position of the pump is determined.
The pump encoder (500 line) channel A and B signals are each
buffered by U27 and applied to two 4-rank synchronizers made from
a single 74ALS273, U26. The synchronizers each have three usable
tap-outputs, which provide a discrete time history of the
corresponding encoder-channel’s signal level. These three signals
are input to U30.
U30 implements a pair of digital filters, one for each encoder channel,
then combines the A and B channels to produce the pump count and
direction signals.
Note: Filter Strategy: For each encoder channel, if the input level has the same
value on three consecutive SCLK rising edges, then that value becomes the
new value; otherwise the value remains unchanged.
The pump count and direction are inputs to the up/down counters,
U47 and U43. The control signals for these counters are provided by
U39.
The output BSPD[0.13] is proportional to the rate-of-change position
(velocity), as determined by accumulating counts, over the time of
0.1966 seconds (defined by TREF).
2. The BSPD[0.13] information is mapped into velocity range-elements.
At the end of every TREF update interval, U46 maps the accumulated
counts, indicated by BSPD data into velocity bins.
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Principles of operation39
3. The range elements are combined with valve status to define device
state.
Valve status and velocity data are combined in U42 to produce the
device-state signal set: MFILL, MWASH, MRETURN, MEMPTY,
MCONC and MPAUSE.
Safety
evaluation
circuits
The main fault-logic processing is provided by the PAL U38, a 22V10, . This
component continuously compares the CPU code to the current device state
and issues a state fault upon disagreement (in the application phase or if
overridden during the test phase). It also handles the detection of a movement
fault, MOV FLT (pump rotation during the test phase), and can determine if an
interlock failure has occurred (FUTURE).
The state fault and movement faults are logically OR’D within U38 to produce
the signal CRIT FLT (critical fault). This signal is processed by the digital-event
timer that is formed by U21 and U16. Should CRIT FLT remain active for more
than two seconds, CRIT FLT DLYD will go high and force U32
to post a safety fault (SAFE FLT).
U32 also processes the TB_FLT, WD_FLT (mentioned above) and the
PS_FLT (power supply: +5V fault, see below) to determine a safety fault. U32
provides the port 231h functionality.
Logic supply protection
The CS5/CS5+ safety board monitors the +5V power-supply and shuts the
device down whenever it is below 4.6VDC or greater than 6.1VDC. U7 (a dual
low-power comparator) is utilized for this function. It is powered by the safe 5V
power that is separated from +5V power by F1 (100 ma fuse) and is protected
by D4 (6.8Vzener diode). Should the +5V go outside of the established range,
Q1 (NPN transistor) will be turned off, thus cutting the power to U3 (dual highvoltage opto-isolator, which provides the PS_FLT flag) and to the lines
SAF_SHDN_CH2 and PUMP_SHDN_CH1.
It is important to mention that the output of U9 will be latched if the measured
voltage exceeds 6.1VDC and will not be latched if the measured voltage falls
below 4.6VDC. The output of U9 is rated to withstand up to 40 VDC.
Buzzer activation
The safety card is equipped with an audible indicator that sounds continuously
if improper device operation is detected by the safety board. The buzzer will
sound, only, if tested during the test phase, a requirement (set test done flag;
see U14, U23, and U13) or upon any fault during the application phase.
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40Principles of operation
Miscellaneous
circuits
U22 and U23 provide the local-board reset pulse, PRST, anytime a system
reset (BRST) or a test-phase start code is received.
U41 and U37 provide the interface for ports 232h and 233h, respectively. The
information read from these ports is latched whenever a safety fault is issued.
U44 handles the centrifuge’s cover-interlock safety by removing power to the
centrifuge relay (FUGE_SHDN_CH1) whenever the cover is open.
U8 logically sums all faults and controls the pump relay operation
(PUMP_SHDN_CH1). Logic high opens the relay.
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Principles of operation41
Valvedriver card
FunctionThe valve driver card is a four-layer PC board. Its basic function is to interface
the processor card, also referred to as the CPU card, to the following system
components:
Pneumatic valves (any combination, up to 12)
Pneumatic compressor (24 VDC)
Safety relay (solid state)
Interface
Circuit
description
Connectors
The valve driver connects to the backplane board (P/N 49488) using two (2)
pin-96 DIN connectors, P301 and P302. The pin identifications for each of these
connectors are shown in Table 5 and Table 6, respectively.
Table 5, Pin identification for P301
PinSignalPin SignalPinSignal
1A+28V11CSYSGND22B
1B+28V RTN12A22C
1C12B23A
2A+28V12CSYSGND23B
2B+28V RTN13AVALVE1 A23C
2C13BVALVE1 B24A
3ASafe +28V 13CVALVE3 A24B
3BSafe +28V R14AVALVE2 A24CSYSGND
3C14BVALVE2 B25A
4ASafe +28V14CVALVE3 B25B
4BSafe +28V R15AVALVE4 A25C
4C15BVALVE4 B26ACMPR DRV
5APUMP +28V15C26BCMPR RTN
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42Principles of operation
Table 5, Pin identification for P301 (Continued)
PinSignalPin SignalPinSignal
5BPUMP +28V R16A26C
5C16B27A
6APUMP +28V16C27B
6BPUMP +28V R17A27C
6C17B28A
7A17C28B
7B18A28C
7CValve SIG
COM
8A18C29BSAF SHDN CH1
8B19A29CSAF SHDN CH2
8CPUMP SIG
COM
9A+15V19C30B
9B-15V20A30CSYSGND
9CSYSGND20B31APUMP SHDN
10A+5V20C31BCPU SHDN
10B-5V21A31CPUMP SHDN
10 CSYSGND21B32ASAF RLY FDBK
11A21C32BFUGE RLY
18B29A
19B30A
CH1
CMD
CH2
FDBK
11B22A32CPUMP RLY
FDBK
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Principles of operation43
Table 6, Pin identification for P302
PinSignalPin SignalPinSignal
1A+5V 11CBUS D022B
1BFUGE SHDN
CH1
1C+5V12BCVR CLOSE SW23AVALVE1
2ASYSGND12C/BUS WR23BSYSGND
2BFUGE SHDN
CH2
2CSYSGND13B24A
3ABUS A913CBUS RDY24B
3BVALVE3 FDBK14A24C
3CBUS A814B25A
4ABUS A714C25B
4BVALVE4 FDBK15ABUS RST25C
4CBUS A615BCVR CLOSE SW26AIBM AEN
12A/BUS RD22C
FDBK
13ABUS CLK23CVALVE2
FDBK
5ABUS A515C26B
5BDIG316A26CIBM A9
5CBUS A416B27AIBM BUS
RDY
6ABUS A316C27B
6BDIG217A27CIBM A8
6CBUS A217B28AIBM RST
7ABUS A117C28B
7BDIG418A28C
7CBUS A018B29ASYSGND
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44Principles of operation
Table 6, Pin identification for P302 (Continued)
PinSignalPin SignalPinSignal
8ABUS D718CSYSGND29B
8BDIG219ASYSGND29CSYSGND
8CBUS D619B30A+15V
9ABUS D519C30B
9BANVIL POS SW20A30C-15V
9CBUS D420B31ASYSGND
10ABUS D320C31B
10BPLATEN POS
SW
10 CBUS D221B32A+5V
11ABUS D121C32B
11B22A32C+5V
Additionally, some test headers are provided; the pin definitions and functions
are shown in Table 7.
Table 7, P1test headers
PinSignal
1U1 pin 8
2U1 pin 7
Note: When a jumper is applied, U2 SSR is continuously energized and
therefore always closed.
21A31CSYSGND
Bus interface
This section contains all the decoding logic, registers, buffers, and transceivers
necessary for the CPU and the valve card to communicate. It interfaces directly
with the data, address, and control signals of the backplane/mother card.
Bus address decoding is provided by U15 . This PAL device detects whenever
the valve card is addressed. The outputs of 15 are DIR (direction), /ADDREQ
(safety-card access), and /EN (enable for data bus buffer).
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Principles of operation45
Lower-order addresses are first buffered by U22 and then decoded by U19 and
U20 . The eleven chip selects for the various valve card, and IO functions are
generated based on the /ADDREQ, address, read, and write signals. The data
bus is buffered by U25 (octal bus-transceiver). The read-and-write lines are
buffered by U22.
Both the CPU reset-signal (BUS RST) and the IBM PC reset-signal (test port IBM RST) are conditioned and combined by U30 and U31 — with filtering
provided by R22/C19 and RN23/C20. The valve card’s reset-signal is named
BRST (/BRST is also available — U30-2 output).
Pneumatic
valve drivers
Overview
The advanced valve card is capable of controlling up to twelve (12) pneumatic
valves. These valves are typically used to supply air, under pressure, to an air
cylinder. Air cylinder (under pressure) overcomes the spring and allows the
tubing to be unclamped. In the CS5/CS5+, for example, three such
mechanisms are employed.
Each valve assembly has a proximity sensor that is utilized for feedback
purposes.
BiMOS high-voltage and high-current latched drivers (UCN5801) are utilized
for driving pneumatic valves. The bipolar/MOS combination provides an
extremely low-power latch with a maximum interface-flexibility. U9 (address
341h) controls Valve1–Valve8, U18 (address 342h) controls Valve9–Valve12.
Pneumatic valves require 20 ma of current at 24 VDC. Since a 28-volt supply
is used in the system, 4 volts (28V-24V=4V) are dropped across 220 ohm
resistors connected in series with each valve (RN6, RN3, and RN9).
These resistors also provide a convenient place to measure valve-current.
When a valve is energized, a voltage is developed across a series resistor. This
voltage serves as a direct indication of the presence of current through the
valve. Multichannel opto-isolators (U8,U6, and U10) are used to convert
voltage information into a digital form available for the CPU to read. U7
(address 343h) and U11 (address 344h) are employed for this function. Low
corresponds to energized valve.
As mentioned above, proximity sensors are used for feedback purposes. When
the valve is closed (de-energized), the feedback is low. U26 provides feedback
information to the CPU. Feedback signals are pulled up and filtered in order to
improve noise immunity.
Pneumatic
compressor
Haemonetics® Cell Saver® 5/5+ Service ManualP/N SM-CS5-01-EN, Manual revision: AB
The function of this compressor is to pressurize the air accumulation chamber,
which is used for valve activation.
The compressor control is accomplished by writing the on or off command to
the U18 BiMOS-octal high-voltage and high-current latched driver.
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46Principles of operation
This compressor requires 24VDC at 150 ma to run. D5 (3.9V zener diode) is
used to bring the supply voltage, of 28VDC, to this level. A voltage drop across
the zener, provides an indication of compressor state. This information is
available to the CPU at U11.
Safety relayU2 is a solid-state relay (VN20AN), which controls the power (28VDC) to both
the pumps and the valves.
The safety card produces the necessary drive for both sides of U2 input
section. P1 jumper is provided to force the relay to be energized in order to
ease troubleshooting and testing. U4 (dual opto-isolator) is utilized for relay
feedback and status.
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Principles of operation47
Motor driver card
Function The basic function of the motor driver card is to interface the processor card,
also referred to as the CPU card, to the following system components:
Pump motor drivers: any combination of up to four (4) brush/brushless
types
Centrifuge controller: brushless DC drive with velocity control and
dynamic break
Relay safety elements: solid-state relays; one each for pump and
centrifuge power-control
In addition to controlling the above components, this board provides interfaces
for the operational status of the pumps, centrifuge, and relay components.
Circuit
description
Connectors
The motor driver connects to the backplane board (P/N 49488) using two (2)
pin-96 DIN connectors P401 and P402. The pin identifications for each of these
connectors are shown in Table 8 and Table 9, respectively.
Table 8, Pin identification for P401
PinSignalPin SignalPinSignal
1A+28V11CSYSGND22BPUMP1 B
1B+28V RTN12A22CPUMP1 C
1C12B23A
2A+28V12CSYSGND23B
2B+28V RTN13A23C
2C13B24A
3ASafe +28V13C24B
3BSafe +28V RTN14A24C
3C14B25A
4ASafe +28V14C25B
4BSafe +28V RTN15A25C
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48Principles of operation
Table 8, Pin identification for P401 (Continued)
PinSignalPin SignalPinSignal
4C15B26A
5APump +28V15C26B
5BPump +28V RTN16A26C
5CFuge +48V16B27A
6APump +28V16C27B
6BPump +28V RTN17A27C
6CFuge +48V17B28A
7A+48V17C28B
7B+48V RTN18A28C
7CValve SIG COM18B29AFUGE A
8A+48V18C29BFUGE A
8B+48V RTN19A29CFUGE C
8CPump SIG COM19B30AFUGE B
9A+15V19C30BFUGE B
9B-15V20A30CFUGE C
9CSYSGND20B31APUMP SHDN
CH1
10A+5V20C31BCPU SHDN
CMD
10B+5V21APUMP1 A31CPUMP SHDN
CH2
10 CSYSGND21BPUMP1 A32ASYSGND
11A21CPUMP1 C32BFUGE_RLY_F
DBK
11B22APUMP1 B32CPUMP_RLY_F
DBK
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Principles of operation49
Table 9, Pin identification for P402
PinSignalPin SignalPinSignal
1A+5V 11CBUS D022B
1BFUGE_SHDN_CH112A/BUS RD22C
1C+5V12B23A
2ASYSGND12C/BUS WR23BSYSGND
2BFUGE SHDN CH213ABUS CLK23C
2CSYSGND13B24A
3ABUS A913C24B
3B14A24C
3CBUS A814B25AFUGE HALL
A
4ABUS A714C25BFUGE HALL
B
4B15ABUS RST25CFUGE HALL
C
4CBUS A615B26AIBM AEN
5ABUS A515C26B
5B16APUMP1
ENCDR A
5CBUS A416B27AIBM BUS
6ABUS A316CPUMP1
ENCDR B
6B17A27CIBM A8
6CBUS A217B28AIBM RST
26CIBM A9
RDY
27B
7ABUS A117C28B
7B18A28C
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50Principles of operation
Table 9, Pin identification for P402 (Continued)
PinSignalPin SignalPinSignal
7CBUS A018B29ASYSGND
8ABUS D718CSYSGND29B
8B19ASYSGND29CSYSGND
8CBUS D619B30A+15V
9ABUS D519C30B
9B20APUMP1
HALL A
9CBUS D420BPUMP1
HALL B
10ABUS D320CPUMP1
HALL C
10B21A31CSYSGND
10 CBUS D221B32A+5V
11ABUS D121C32B
11B22A32C+5V
Additionally, some test/configuration headers are provided; the pin definitions
and functions for brush/brushless motors are described in Table 10,
Table 11, Table 12, and Table 13.
Table 10, P1 Pin identification
PinSignal
30C-15V
31ASYSGND
31B
1SYSGND
2PUMP1 HALL A
Note: A jumper installed in any of the above locations will configure the
respective driver to accommodate a brush type DC motor.
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Principles of operation51
Test/configuration headers for relays are shown in Table 11 and Table 12.
Table 11, P3 Pin identification
PinSignal
1U37 pin 8
2U37 pin 72
Table 12, P4 Pin identification
PinSignal
1U15 pin 4
2SYSGND
Note: When a jumper is applied, the selected relay is continuously energized
and therefore always closed. Jumper is applied to P3 to perform pump test
within the Diagnostics mode (for applicable revisions); however, it must be
removed during normal operation.
The centrifuge’s speed test points are shown in Table 13.
Table 13, P5 Pin identification
PinSignal
1CENT TACH
2SYSGND
The centrifuge overspeed disable pins are shown in Table 14.
Table 14, P6 Pin identification
PinSignal
1CENT OVERSPEED JUMPER
2SYSGND
Note: The jumper disables overspeed circuitry.
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52Principles of operation
Bus interfaceThis section contains all the decoding logic, registers, buffers, and transceivers
necessary for the CPU and the motor driver card to communicate. It interfaces
directly with the data, address, and control signals of the Advanced backplane.
Bus address decoding is provided by U68 . This PAL device detects whenever
the motor driver card is addressed.
The outputs of U68 are DIR (direction), /ADDREQ (safety card access), and /
EN (enable for data bus buffer).
Lower, order addresses are first buffered by U45 and then decoded by U75 and
U76. The thirteen chip selects for the various motor driver card, and I/O
functions are generated based on the /ADDREQ, address, read, and write
signals. The data bus is buffered by U58 (octal bus transceiver). The read-andwrite lines are also buffered by U45.
Both the CPU reset-signal (BUS RST) and the IBM PC reset signal (test port IBM RST) are conditioned and combined by U28 and U36, with filtering
provided by RN19B/C45 and RN19D/C39. The motor driver card’s reset signal
is named BRST (/BRST is also available — U52C output).
Pump motor
drivers
Overview
In the CS5/CS5+ device, one reversible peristaltic-pump is employed.
In a CS5/CS5+ device, one pump revolution moves approximately 5.5 mL of
fluid; however, the actual flow will depend on a specific tubing’s dimensions
and wear. The general rule is that the pump will efficiently deliver a proposed
volume to within ±15%.
Each pump motor is required to be equipped with a quadrature encoder. For
the CS5/CS5+ device, a 500-line encoder is used.
The CPU transmits to the motor driver card the desired pump rate and
direction. The motor driver card in turn compares this information with that
received from the encoder and adjusts the motor’s drive level, using pulsewidth modulation, to compensate for any error. Additionally, each motor driver
has an independent enable input, which allows the CPU direct control over the
driver power (interface provided by U23, U32, and U38).
Because the motor driver card implements a position-control-loop-servo
approach, no adjustment of the motor speed is required.
As all pump servos are identically implemented, the descriptions, which follow,
will be simplified by referencing the Pump 1 servo components.
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Principles of operation53
LM629 (U73)
This IC is a dedicated microprocessor peripheral, which performs all the control
functions for the pump servo-system.
The LM 629 receives instructions from the CPU concerning filter coefficients,
trajectory, and error handling; processes this information and the encoder
feedback (PID algorithm); creates a PWM (pulse width modulated) signal and
direction signal for loop control; and finally provides the CPU with data
regarding the actual motion status and fault conditions.
Note: For detailed hardware and software descriptions of the LM629, refer to
the following National Semiconductor application: AN-693, LM628/LM629; and
Programming Manual AN-706; and LM628/LM629 User Guide.
The encoder signals are buffered by U28 and U56 (74HCT14) before being
processed by the LM629. The output PWM and direction data-signals are
optically isolated by U61 and U62 in order to eliminate any ground noise.
U2 is a PAL assembly, which functions in place of the discontinued National
Semiconductor LM621, a brushless motor commutator IC. This PAL provides
the correct on/off sequencing for the MOSFET drivers contained within U9 by
processing the isolated direction signal along with the hall effect position
sensor signals obtained from the brushless motor.
U12 (TC4469) is a TTL to MOS level translator, which accepts the isolated
PWM signal, AND’ed with the TTL level low side drive-outputs from the PAL
assembly, and provides the required drive to the lower (N-channel), MOSFET
components of U9.
U16 and U18 (75471) are peripheral drivers again, functioning as TTL to MOS
level translators, which accept the TTL level high side drive outputs from the
PAL assembly and provide the required drive to the upper (P-channel)
MOSFET components of U9.
U9 (MPM3003) is the power-stage IC. It contains three P-channel and three Nchannel MOSFETS, arranged in a three-phase bridge topology. It is these
outputs that are routed to the phase windings of the pump motor.
The controller fault status for all pump channels is available to the CPU via port
310h (U65).
The circuits described in this section are responsible for controlling centrifuge
acceleration, deceleration, slew speed, and braking.
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54Principles of operation
Centrifuge
controller and
driver
Main loop
A closed loop-velocity control-system is employed. Its operation follows:
The CPU transmits digital-speed information to U69 (AD7248 on sheet 3),
which in turn produces an analog (12-bit) output that is proportional to this
speed. The scale factor is chosen so that (10V out) = 10240 RPM.
The analog voltage is, next, divided (by R90 and R91) so that 3.65V is the
full-scale input, applied to U20 (AD822).
An analog feedback signal that is proportional to the centrifuge velocity
(TACH feedback), is provided by U22 (MC33039). It accomplishes this by
producing a fixed on-time pulse whenever any of the three hall effect
sensors transition. (Any of the three inputs buffered by U30 a 74C14.)
Over current/over speed
Current limiting on a PWM cycle basis is achieved by feeding back a differential
voltage signal (to pin9 through pin 15 of U7) proportional to the output current
(provided by passive elements R20, R23, and R25, which are connected
between pin1 of U8 and ground). The nominal current limit is set for 3.1 amp.
Overspeed is checked locally by filtering the Cent Tach output (R46, C26, and
U20) and comparing this voltage (U25) with a level representing approximately
8000 RPM. Should an overspeed condition be sensed the signal Cent
Overspeed will be latched High (U48).
The CPU can independently check centrifuge speed by accumulating the Hall
B output pulses from the centrifuge motor in U59 (82C54 counter I.C.).
Centrifuge enable and break controls
A direct centrifuge enable/disable is provided by U63 (high=enable) in
conjunction with U36 and U57. An indirect disable occurs whenever the break
bit is set.
The break command is by default a pulse break. Normally, timer 2 of U59
(82C54) is set up (on power-up) in the divide by N mode (mode 2), with N=8.
Whenever the break bit is set, the output pulse train from U59 pin20 will be
gated through U36, inverted by U32, and then applied to break input of U7
(sheet 9). Therefore the term pulse break really means a duty cycle (pulse
position modulation) control of breaking. Note, however, that a change of mode
to timer 2 can be used to implement a hard break (i.e., continuous break signal
application).
There are two power solid state relays on the motor driver card.
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Principles of operation55
Safety relay
The first is known as the pump relay. It is realized by U24 (VN20AN). The relay
is known in the CS5/CS5+ system as the K2 relay and controls the power
applied to all pump motors. It is under the control of the safety card (via signals
pump Shdn Ch1 and pump Shdn Ch2) and the pump heatsink temperature
monitoring system (Logically Or’ed in U37). This relay has internal low voltage
and current limit protection.
U41 provides isolation for the safety system and the temperature fault logic.
While U29 provides an isolated feedback path for the relay’s on/off status to
both the CPU and safety systems.
Jumper connections provided by P3 are used to force the relay to a closed
position during board tests. Normal safety-card tests will differentiate between
a shorted/jumpered relay and a nominal condition.
The second relay is realized by U15 (ODCH-5H). This relay is controlled in a
CS5/CS5+ system by the centrifuge cover mechanical interlocks and the
overspeed/overtemperature fault signals mentioned above.
Testable jumper connections are provided by P4 for unconditionally powering
the centrifuge.
Components U67, U46, U52, and U53 are used to monitor the +48 volts to
ensure that no undervoltage (42.0V nom.) condition exists (+48V fail signal will
be latched if limit is not met).
As with the other previous fault signals mentioned, a reset line is provided ->
+48V fail reset (U57 pin2).
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56Principles of operation
Processor card
FunctionThe processor board is also known as the CPU board. This card is based on
the Intel 80C188 microprocessor. The CPU can address a full megabyte of
memory that consists of static.
System test capability under a well accepted computer system
16 channel 12-bit A/D with self-test and auto zero capability
4000-volt isolated RS-232 port
Buffered display/keyboard bus
Air detector interface with interrupt capability
Watchdog timer — TUV accepted lost processing prevention
All digital and analog I/O signals are available on test connectors (clinical
/ MFG. test facility)
Hardware CRC accelerator
Onboard graphics controller (64K byte video memory)
Remote smart-card access
Five air monitors and two air/drip monitors
Three weighers
Four pressure monitors
Three line sensors
Adjustable audiolevel for beeper
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Principles of operation57
ProcessorThe 80C188XL processor U51, has an 8-bit data bus, which is multiplexed with
the lower address-bits, 0 through 7. The CPU data bus is buffered and
demultiplexed by U58, a 74ALS645 8-bit bidirectional bus driver. The
processor DT/R (Data Transmit/Receive) line controls the flow of data in or out
of U58. U58 is enabled by PAL U72, which will be discussed later. The 20-bit
address bus is latched and demultiplexed by U58, U59, and U70. U58 and U59
are transparent latched (74ALS573) for address bits A0 through A15. Address
bits, A16 through A19, are transparently latched by PAL U63. U63 buffers the
ALE (address latch) signal from the processor, which is connected to the clock
inputs of the latches and the internal clock for the latch within the PAL. When
ALE is high, the address information is allowed to propagate through the
latches; when ALE goes low, the address information is frozen. The output
control of the latches are controlled by PAL U63, which will be discussed later.
Microprocessor
kernel PALS
PAL U72 controls the functions for board, I/O-base address decode, board
master/slave operation, CPU data buffer enable (U58), board ready buffer, and
direction control for backplane data bus. Inputs BRD A9 through BRD A4 are
decoded and drive the /ADDREQ and /ADDREQ1 output lines low between the
address range of 260h to 26FH and 290 to 29F, respectively.
When jumper E3 is present, the board is configured in the Slave/IBM mode.
The input /IBM SEL is low, which drives outputs IBM high and /IBM low. /BRD
G will go low, which enables data buffer U58 when the inputs /IBM SEL is high,
DEN is low, and /8256_CS is high. Therefore, the CPU data buffer is only active
when the 8256 is not selected, the CPU data enable (DEN) is active, and the
board is in the Master/CPU mode.
PAL U62 functions are: Memory and I/O read and write strobes
(/MEM_RD, /MEM_WR, /IO_RD, and IO_WR), processor clock divider, and
processor reset-line (BRD RST) buffer. These outputs are tri-stated when the
board is configured in the Slave/IBM mode. The 8-MHz processor clock
(PROS_CLK) is divided by two (2) and output on (BRD_CLK). The CPU’s read
and write strobes (/RD and/WR) are conditioned with the BOARD_IO. When
BOARD_IO is high, I/O is being accessed, and when low, memory is being
accessed. The /MEM_WR line is further conditioned by /NVRAM_CS, PT WR
PRO, and SW WR PRO signals. These last conditions perform the NVRAM
write protect function. When the NVRAM chip select is active (low) and the
switch or port write protection function is enabled, active (high) the /MEM_WR
line is disabled and kept high.
PAL U63 functions include ALE (address latch enable) buffer, processor S2
(board I/O) transparent latch, address A16 through A19 transparent latch,
EPROM, and memory card and video ram chip selects. When ALE is high,
address lines A16 through A19 are allowed to propagate to the outputs BRD
A16 through BRD A19. On the falling edge of ALE, these outputs are latched.
The processor S2 to BRD 10 signal functions the same way. These outputs are
tri-stated when the input signal, IBM, goes high. The EPROM, memory card
and video RAM chip selects are decoded from address lines A15 through A19.
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58Principles of operation
PAL U72 functions are data bus buffer direction control and I/O range select
generation and ready line conditioning. The I/O range selects are derived from
address lines BRD A4 through BRD A9. As was stated earlier, /ADDREQ line
will be active in the range of 260h to 26FH, and /ADDREQ1 will be active in the
range of 290h to 29FH. These ranges are further decoded by U61, U33, and
U71.
Bus interfaceThe backplane I/O bus interface is designed to be compatible with the IBM PC
I/O bus. U52 buffers the lower, address bus-lines, A0 through A7. The /IBM
signal is connected to the directional control of the buffer. When the board is in
the Master mode, this line is high and the address is transferred from the onboard local bus to the backplane bus. When in the Slave mode, this line is low
and the address from the backplane bus is transferred to the local board bus.
U65 buffers address lines A8 and A9, along with the control signals /BUS WR,
/BUS_RD, IBM AEN, BUS RST, AND BUS CLK. These lines are bidirectional
and their direction is controlled by the /IBM signal as the above A0 through A7
lines. The Backplane data bus is buffered by U57 and its direction is controlled
by the BUS DIR signal. When this signal is high, data is transferred from the
local data bus to the Backplane bus. When this signal is low, data is transferred
from the Backplane bus to the local data bus. The BUS DIR signal is generated
from PAL U36 and is described in the above section on PALS.
Memory
configuration
Interrupt
control
The memory consists of one EPROM (U74-512K), a 128K-byte SRAM (U79),
and a 32K byte NVRAM (U75), which includes a real-time clock and a memory
card interface (256K).
The 80C188XL has a built-in interrupt controller which handles four (4) external
interrupt sources. The highest priority interrupt INT0, on pin45 of U51, is the
air detector interrupt, which is generated by the I/O circuitry and is explained in
the I/O section. INTI on pin44 is the next highest and is the backplane interrupt.
INT3 on pin41 is the lowest priority interrupt which is connected to the 8256
(U55) interrupt line. The 8256 is a slave interrupt controller with its own interrupt
sources and priorities. A rising edge on any of these interrupt inputs causes the
80C188XL to service that interrupt. Along with these external interrupt sources,
the 80C188XL has internal interrupt sources that include three timers and two
DMA channels. The DMA channel interrupts are not used in this design. The
timers are configured as the system software clock and this interrupt is
enabled.
The 8256 has one external edge triggered interrupt source. It is a keyboard
interrupt from the display panel that indicates when a button is pressed. The
8256 also contains an integrated RS232 port controller which has internal send
buffer, empty, and input buffer full interrupt sources. The three times and their
interrupts are not used in this design. Signal-routing of the above interrupts will
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Principles of operation59
be discussed in the “Digital I/O” on page 59.
Digital I/OGeneral
The processor board contains a number of 8-bit input and output ports. Port
assignment is recorded in the CPU memory map.
The function assignments are shown in Table 15 and Table 16.
Table 15, Processor inputs
InputSource
U44All system interlocks, spill detector, and centrifuge’s
relay feedback
U30Pump-relay feedback, safe-relay feedback, and cover
switch
U45System air detectors
U31System temperature-switches
U50System air-latched status
U53System air
Table 16, Processor outputs
InputSource
U29System air-test commands and CPU Shdn command
U46Watchdog, watchdog enable, port write-protect, Dma
write-enable, and display enable
U54Air-signals latch command
U558256, which contains two 8-bit ports, an interrupt
controller, three times, and an RS232 controller
RS232 portThe 8256 (U55) is the serial RS232 data port. The baud-rate clock is derived
from a 5.12-MHz TTL clock (U48) which is connected to the 8256 clock input.
A clock divider on the 8256 can be programmed for all popular baud rates. The
data-input and data-output lines, SIN and SOUT, and six data-control lines,
DTR, RTS, RING, DSR, CARR, CTS, are buffered by U23 and then optically
isolated. U16, U17, U12, U11, and U8 are 4000-volt optical isolators, which are
powered from the 5V to 5V high isolation DC-to-DC converter U10. The
isolated side of the signals are connected to an RS232 driver/receiver interface
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60Principles of operation
IC (U43). It is also powered by the DC-to-DC converter U10. The interface IC
contains two DC-to-DC converters that drive the RS232 outputs to normal
RS232 levels. The isolated RS232 level signals are connected to a 9-pin, Dtype connector J104.
Display and
keyboard
Display interface
The advanced processor card uses SED1351 (U76), a high-duty, dot-matrix
display controller. This device has a chip select output pin for VRAM; this
makes it possible to directly connect two 256K SRAMs (U77 and U78).
The ready line is utilized and is processed by PAL (U71). All clocks and A0 are
buffered by 74ALS541 (U66). The output enable of this buffer is under CPU
control. Other interface signals are also buffered by 74ALS541 (U68). These
outputs are always enabled.
Keyboard interface
The keyboard data bus uses 74ALS645 (U64) for communications with the
CPU. A direction of data transfer is controlled by PAL (U71). All keyboard chip
selects along with read and write signals are buffered by 74ALS541 (U69).
Other featuresWatchdog
The watchdog signal and watchdog enable signal are connected to AND gate
U47 and output through R80. The output of the AND gate is pulled up by R76.
Buzzer control
The audible indicator has a programmable output level controlled by AD558K
(U40) and an enable command. Communication to the buzzer is accomplished
by PAL (U39).
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Principles of operation61
Analog section Analog input conditioning
The processor board can handle up to eleven analog inputs. Each input
conditioner is tailored for a specific input sensor. Table 17 describes the buffer
parameters.
Table 17, Buffer parameters
ChannelSignal nameInput ZRef #Input range*Overall
gain
0weigher #1>20 MEGU40 TO 12.5 mV4004 Hz
1weigher #2>20 MEGU30 TO 12.5 mV4004 Hz
2weigher #3>20 MEGU20 TO 12.5 mV4004 Hz
380% Test----ABSOLUTE1--
450% Test----ABSOLUTE1--
520% Test----ABSOLUTE1--
6CUFF PRES 36KU15A1.25 TO 7.5 V0.8220 Hz
7DNR PRES120KU15B-2.4 TO +2.4 V1.04100 Hz
8BOWL PRES120KU15C-2.4 TO +2.4 V1.04100 Hz
9EXR PRES120KU15D-2.4 TO +2.4 V1.04100 Hz
Bandwidth
10PLAT LINE
SEN
11RED LINE
SEN
12Y/G LINE SEN 20KU7C0 TO 10 V0.5 V>300 Hz
13BOWL
OPTICS
14GND REF----0 V----
*Overall Gain = Front End Gain X Programmable Gain
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20KU7A0 TO 10 V0.5 V>300 Hz
20KU7B0 TO 10 V0.5 V>300 Hz
200KU7D0 TO 10 V0.5 V32 Hz
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62Principles of operation
Table 17, Buffer parameters (Continued)
ChannelSignal nameInput ZRef #Input range*Overall
gain
0weigher #1>20 MEGU40 TO 12.5 mV4004 Hz
15GND REF----0 V----
*Overall Gain = Front End Gain X Programmable Gain
Except for the weigher channels, all inputs are single-ended and conditioned
by amplifiers from two OP-297 quad OP amps.
The weigher inputs are differential; each channel uses an AD620
instrumentation amplifier for conditioning. Additionally, a programmable tear
function is implemented (no tear, +500 uV RTI, or 2 mV RTI) by U18, U19, and
U25 (/ANA CS3 select). Also, individual, bridge-test terminating-resistors can
be switched in under software control — using U19, U20, and U26 (/ANA CS2
select).
The bowl-optics channel includes an offset trimming option. When E1 is
jumpered, potentiometer R2 (1 megohm) adjusts the offset voltage on the
bowl-optic buffer output.
Internal A/D testing is supported by U1 (a LH0070; an independent 10V voltage
reference) and the resistor divider chain are made up of R69, R72, R75, R77,
and R78.
Bandwidth
Analog
multiplexer and
test logic
Note: U1 also provides the precision +10 volt excitation voltage for the weigher
and cuff transducers.
Three reference taps of 80%, 50% and 20% at full scale (i.e., fixed voltages of
4V, 2.5V, and 1.0V) are sequentially available on channels 3, 4, and 5.
Each of the inputs is buffered and connected to a series resistor network (RN5,
RN7, or RN8 10K ohm SIPs) and then to the analog test connector J103. The
analog ground is also connected to the connector for easy analog
measurements.
The eleven inputs and threetest signals, mentioned above, are connected to a
sixteen-channel analog multiplexer, U22 (MUX). The two remaining MUX
inputs are grounded.
Channel selection is controlled by inputs A0 through A3, of U22. These lines
are latched outputs from U21. The on-board data-bus bits, BRD D7 through
BRD D4, define the channel selected. The latch-clock line is controlled by /ANA
CS1.
PRES HI TEST and PRES LO TEST are control lines (U25 outputs - /ANA CS3
select) that drive a bridge-loading circuit on the external donor and system
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Principles of operation63
pressure monitors. EXR PRES T LO and EXR PRES T HI are similarly defined
but are reserved for future expansion.
When these lines are activated, the bridge in the pressure transducer is loaded
and a known voltage is expected from that device. This enables testing of the
pressure transducer without having to apply an external pressure to the device.
Programmable
gain amplifier
The output from the 16-to-1 multiplexer, U22, is connected to the A input of a
programmable, gain-amplifier stage, U14. The gain is set in steps of 2, from 1
through
U22. These signals come from the remaining signals from U21 (/ANA CS1
select) and are set by the on-board data-bus bits BRD D2, BRD D1, and BRD
D0.
16. The control of this gain is provided by inputs to A0, A1, and A2, of
A/D converterThe output from the programmable gain stage, U14, is connected to the +VIN
input of the sample and hold amplifier U6. Its output is connected through a 1K
ohm resistor (R42) to input (AIN) of the A/D converter U13. The /BUSY output
from the A/D converter is connected to the /HOLD input of the sample and hold.
When the A/D converter starts a conversion, the /HOLD line goes low, which
puts the sample and hold amp in the Hold mode. This provides a stable input
voltage to the A/D converter. After conversion, this line goes high and the
sample-and-hold amp is set to the Sample mode. The /BUSY line is also
connected to the INTO interrupt input of the processor. Therefore, when this
line goes high after the end of a conversion cycle, the processor is interrupted
and the conversion data can be read from the A/D converter. The A/D
converter, U13, is a 12-bit successive-approximation type. Its output, 8-bit data
bus, is connected to the board-data bus through a bidirectional 8-bit buffer,
U27. The buffers’ outputs are enabled by analog-chip select, 0 (/ANA CS0).
The buffers’ data direction is controlled by the I/O read line (/IO RD), which is
connected to the DIR input. When /IO RD is low, data from the A/D is read onto
the board data bus. The ANA CSO line is also connected to the A/D converter,
which enables its data-bus buffer. The I/O read-and-write lines (/IO RD and /IO
WR) are connected to the A/D converter, along with BRD A0, which selects one
of two internal data registers.
To start a conversion, the /IO WR and /ANA CS0 lines, are set low. At that time,
the /BUSY line goes low and the conversion begins. When the conversion is
complete, the /BUSY line returns high and signals an interrupt to the processor.
The processor then issues an /IO RD command with BRD A0 low and the LSB
byte out of the A/D converter is read out. The MSB byte is then read out with a
second read cycle and with BRD A0 high. This completes a full conversion
cycle.
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64Principles of operation
Table 18 and Table 19 identify the pins on the CPU/backplane.
Table 18, CPU/backplane pin identification (J101)
PinSignalPinSignalPinSignal
1AWeigher 1 FDBK A12BCLAMP LINE
FDBK B
1BResv Level Sen
FDBK A
1CWeigher 1 FDBK B13A23CPres HI
2AWeigher 1
Reference
2BReservoir Level
Sensor FDBK B
2CWeigher 1 RTN14A#1 Air DET 24CSYSGND
3AANLG214B#2 Air DET25A
3BReservoir Level
Sensor Reference
3C15A25C
4AANLG115BSYSGND26A
4BReservoir Level
Sensor RTN
12C23B
13BTemp INLK124APres LO
13C24B
14C#3 Air DET25B
15C#1 Air Test26B
23A
Test
Test
4C16A26C
5APres SIG16B27A
5BSYSGND16C27B
5CPres INLK217ASpill DET #127C
6APres RTN17B28A
6BSYSGND17C28B
6C18A28C
7A18B#2 Air Test29A
7BTEMP INLK218C#3 Air Test29B
7C19A29C
8AY/G Line SEN19B30A
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Principles of operation67
Hardware components
Photoelectric
assembly
(sensor head)
Photoelectric
assembly
(power block)
An optical sensor is used inside the centrifuge well to monitor the level of fluid
in the spinning bowl. A light beam is transmitted to the bowl’s outer body/
contents and/or white core of the bowl (depending on optics configuration)
where it is reflected to the receiver in the optics. Table 20 lists specifications for
the sensor head.
Table 20, Photoelectric sensor head specifications
ParameterSpecification
Analog output0 to +10 VDC
BeamVisible red 650 nm modulated @ 1kHz
AdjustmentGain only
Operating temperature
range
Delay upon power-up200 ms max.
This power block supplies voltage to the photoelectric sensor head. Table 21
and Table 22 identify the function of the wiring to the photoelectric power block
and the power block specifications, respectively.
Table 21, Photoelectric power block wiring
-40° to +70° C
ColorFunction – power
Brown+ DC input
White-DC common
ColorFunction – signal
Black0 to 10 VDC output
Blue-DC common
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68Principles of operation
Table 22, Photoelectric power block specifications
ParameterSpecification
Pump motor
driver and
encoder
feedback
Input power
requirement
OutputRegulated to supply requirements of sensor
Operating temperature-40°to +70° C
The drive signals are generated on the motor driver card by U9 (MPM3003).
These MOSFET drivers are activated by U2 (PAL) and U11 (TC4469CPO),
which convert pulse-width modulated-magnitude and direction to a threephase switching sequence. Table 23 lists specifications.
Table 23, Pump motor specifications
SpecificationTol.UnitsValue
Maxoperating speedMaxRPM1000
Continuous torque (Stall) @49
(104oF)
Peak torqueNom.oz.-in.384
+15 to 30 VDC @400 mA
head
° C
AMB.
Nom.oz.-in.192
Current @ cont. torqueRatedamps5.25
Current @ peak torqueRatedamps10.52
Max terminal voltageMaxvolts100
DC resistance @ 25° C (77°F)± 12.5%ohms4.45
Inductance @ 1000HX± 30%MH.5.86
High-pressure
air compressor
P/N SM-CS5-01-EN, Manual revision: ABHaemonetics® Cell Saver® 5/5+ Service Manual
Specifications for this component are given in Table 24.
Table 24, High-pressure compressor specifications
ParameterSpecification
Voltage24V
Operating current0.2A
Page 69
Principles of operation69
Pumpplaten
position switch
This signal is returned to the valve driver card and referred to as PLATEN POS
SW. The signal is brought into U27 (74HC244, where it is octal-latched and is
readable by the CPU).
Table 25 provides specifications for this component.
Table 25, Pump platen position switch specifications
ParameterSpecification
Supply voltage5-30 VDC
Load current min/max.0-100 mA
Leakage current, max. 10 A
Voltage drop, max.1V
Current consumption, max. 10 mA
Repeatability, shielded± 1%
Repeatability, unshielded± 3%
Hysteresis3–15%
Proximity
sensor
(disposable
loadedsensor)
Sensing face materialPolyamide
Housing materialStainless alloy
Cable typePVC jacket
Cable wire gauge26 gauge
This signal is returned to the valve driver card and referred to as ANVIL POS
SW. The signal is brought into U27 (74HC244 where it is octal-latched and is
readable by the CPU).
Table 26 provides specifications for this component.
Table 26, Proximity sensor specifications
ParameterSpecification
Supply voltage4.5 –30 VDC max.
Voltage ripple max.10%
Leakage current10 A max.
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70Principles of operation
Table 26, Proximity sensor specifications
ParameterSpecification
Voltage drop, max. 1.5 VDC
Load current max. 50 mA (resistive)
Current consumption, max. 2 mA
Hysteresis5-15%
Repeatability± 1%
Temperature range- 10°to 65° (+14° to +149°)
Sealing IP67
Shock and vibrationIEC 68-2-6&68-2-27
Centrifuge
motor stator
Centrifuge motor driver signals are generated on the motor driver card by U8
(MPM3003). These MOSFETdrivers are activated by U1 (UDN5706A) and U7
(MC33035DW), which convert an analog voltage to a three-phase switching
sequence.
Table 27 provides specifications for this component.
Table 27, Centrifuge motor stator specifications
ParameterSpecification
Continuous torque80 oz-in
Peak torque480 oz-in
Back EMF (Ke)5.0V/KRPM
Torque sensitivity (Kt)6.75 oz-in/amp
Resistance (phase-to-phase)0.10 ohms
Inductance 0.120 Mh
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Principles of operation71
Load cell (waste
bag weigher)
Feedback from the load cell is sent back to the CPU. The signal name is
WEIGHER 1. This signal is brought into U4 (AD620BR, an instrumentation
amplifier), where it is conditioned and scaled.
Table 28 identifies the wire coding and Table 29 lists the specifications for the
waste-bag-weigher load cell.
Table 28, Load cell wiring color code
Color
InputBlack (-)
Green(+)
OutputRed (-)
White (+)
Table 29, Load cell specifications
ParameterSpecification
Compensated temperature range-18° C to 66
Temperature effect on rated output
(from 15o F to 115oF)
± 0.0008%/degree F of rated output
° C
(0° F to 150°F)
Temperature effect on zero balance
(from 15o F to 115oF)
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72Principles of operation
Reservoir level
sensor gauge
Feedback from the reservoir level sensor gauge is sent back to the CPU; the
signal name is RESV LEVEL SEN. This signal is brought into U3 (AD620BR,
an instrumentation amplifier), where it is conditioned and scaled.
Table 30 provides the specifications for this component;Table 31 identifies the
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Principles of operation73
Compression
loadcell
(clamped line
detector)
Feedback from the load cell is sent back to the CPU. The signal name is
CLAMP LINE. This signal is brought into U2 (AD620BR, an instrumentation
amplifier), where it is conditioned and scaled.
Table 32 provides the specifications for this component, and Table 33 identifies
the wire coding.
Table 32, Compression load cell specifications
ParameterSpecification
Overload w/o damage4X
Excitation 5 VDC
Output2± 0.5 mV/V
Zero balance± 20% (± 2 mV)
Overall accuracy0.25%
Repeatability± 0.05% F.S.
Temp. comp. Zero ± 0.05% Rdg/F
Span ± 0.05% Rdg/F
Resolution Infinite
Capacity0–5 lb
Max. allowable
deflection at full scale
Max. operating temp.-65° to +250° F
Table 33, Compression load cell wiring code
ColorFunction
Red+ Excitation
Black- Excitation
Green - Excitation
White+ Output
BlueShield
0.002’’
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74Principles of operation
Airdetector
sensor
assembly
This feedback is sent back to the CPU, the signal name is #1 AIR DET. This
signal is inverted by U45 (74HCT540DW, an octal inverting bus buffer) and
then presented to the data bus, upon chip selection, by U53 (74HCT541DW,
an octal non-inverting bus-buffer, with three-state outputs). Table 34 identifies
the wire coding for this component. Table 35 provides the specifications;
Table 36 lists the tubing types used with this component.
Table 35, Air detector sensor assembly specifications
ParameterSpecification
Yellow LEDFluid sensor
Supply voltage+12 to 16 VDC
Input TTL compatible
Sensitivitybubbles larger than 0.3 mL
Flow rates stationary to 1000 mL/min.
Fluid pressure-75mmHg to 300 mmHg
Output pulse width2 milliseconds
Response time to fluid to air and air
to fluid transitions
Storage temperature0–50°
Operating temperature0–50°
Storage humidity5–95%
50 milliseconds or less
C
C
Operating humidity10–95% (noncondensing)
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Principles of operation75
Table 36, Haemonetics tubing types (for use with air detector)
TypeP/NI.D. TOLO.D. TOL.MATDurometer
Assembly pinch
valve
CS5/
CS5+
The valves are driven by U9 (UCN5801A, an octal bimos latched driver).
This signal is sent to the fluid deck PCB and used to activate the pneumatic
solenoids.
This feedback signals are returned to the valve driver card and referred to as
valve 1, 2, or 3 FDBK. The signal is brought into U26 (74HC244, where it is
octal latched and is readable by the CPU).
Table 37 provides specifications for this component.
Table 37, Pinch valve assembly specifications
ParameterSpecification
Piston bore0.88 (0.56 effective area)
Spring force (min.) at full rod
extension
Spring force (max.) at full
stroke
6299.250 ±
0.005
0.375 ±
0.005
7.24 lb
8.75 lb
Clear
PVC
62/67 shore
A
Plunger sealViton O-ring 2-015
Plunger retractionwt 16 PSI to full stroke
Hard clear anodize Type III, Class 1, per Mil-A-8625(.001
± 0.0002 thk.)
Todd power
supply
Haemonetics® Cell Saver® 5/5+ Service ManualP/N SM-CS5-01-EN, Manual revision: AB
Specifications are provided in Table 38.
Table 38, Power supply (Todd) specifications
Parameter Specification
AC input80-132 VAC or 160-264 VAC 47-63 Hz
Inrush current (cold start)50 amp (max.)
Output V1+5.1V @ 10A/1.5A min. load
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76Principles of operation
Table 38, Power supply (Todd) specifications (Continued)
Parameter Specification
Output V2+15V @ 1.5A
Output V3-15V @ 0.5A
Output V4+28V @4A /6Apk & no minimum (peak- 1
second duration maximum; repetition rate
not to exceed a 10% duty cycle)
Output V5+48V @ 2A/4Apk (peak 10 second duration
maximum; repetition rate not to exceed a
10% duty cycle)
V1 centering (at 60% load)± 2% adjustable
V2 centering (at 60% load)± 2%
V3 centering (at 60% load)± 2%
V4 centering (at 60% load)± 5%
V5 centering (at 60% load)± 5%
Line-load regulation output 1± 2%
Line-load regulation output 2±2%
Line-load regulation output 3± 2%
Line load regulation output 4± 2%
Line load regulation output 5± 5% from 20 to 100% load change on
output with 60 +1-25% load on output 4
Ripple and noise± 1% or 100 mV, whichever is greater, 20
MHz BW
Efficiency80% typ. with 75% loading
Holdup time20 m second after nominal AC loss
Overvoltage protection5.1 V output (6.8V max.)
Temperature range
(operating)
0 to 50° C
Temperature range (storage)-25 to 95° C
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Principles of operation77
Table 38, Power supply (Todd) specifications (Continued)
Parameter Specification
Maximum combined output
power (convection cooling)
Maximum combined output
power (30 CFM air flow)
Maximum combined output
power (100 CFM air flow)
Leakage 50 μamp as measured per U.L. 544
ShockMil-Std 810-D method 516.3, Proc. III
VibrationMil-Std 810-D method 516.3, Cat. 1, Proc. I
Condor power
Specifications are provided in Table 39.
supply
Table 39, Power supply II (Condor) specifications
FactorSpecification
AC inputAutomatic selection
80 - 132 VAC or 160 - 264 VAC
47 - 63 Hz, single phase
Fuse type 250 VAC 1DA
150 Watts
200 Watts
300 Watts
Inrush current (cold start)16 A” sec
DC output#1. +5 1V @ 10 amps/1.5 amps minimum load
#2. +15V @ 1.5 amps
#3. -15V @ 0.5 amps
#4. +28.375V @ 4 amps/6 amps peak and no minimum
#5. +48.65DV @ 2 amps/4 amps peak and no minimum
Tolerance @ 25° C (all outputs at
60% load)
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Principles of operation79
Bowl optics - single lens (CS5 only)
Feedback from the sensor head is sent back to the CPU card into U7
(DP497GS, a quad operational amplifier), where it is scaled.
The signal from the bowl optics is sampled every 250 ms, and a moving
average of at least three samples is used.
When the Fill cycle starts, a base reading is taken at the bowl, 20 mL after the
begin of the Fill cycle.
If the Fill cycle is interrupted, a sample is taken after the recentrifuge delay, if
one occurs, but before the pump begins.
The bowl-optics signal must fall to 5/6 of the base reading.
Following the fall, a rise of one (1) volt is expected. If no fall or rise occurs within
305 mL of beginning Fill (or 150 mL for a low-volume bowl), the meniscus is
implied. This can happen in certain orthopedic procedures.
Trip to Wash
Following detection of a meniscus, the bowl optics is ignored for 30 mL
(approximately five (5) pump revolutions). This is the post-meniscus delay.
Following the delay, readings continue and the maximum reading is stored. In
Fill mode, a fall-off of 67% of the signal from the maximum is the signal for the
red blood cell (RBC) line. A fall-off of 33% indicates RBCs are in Concentrate.
This is the point that the CS5 advances to Wash.
Failsafe trip point
The CS5 will also trip automatically from Fill to Wash in Trip to Wash if the
optics level drops below 600 and the red line sensor is reading below 100. This
will prevent no-trips.
Bowl size recognition
70 mL bowl
The 70 mL bowl protocol utilizes the bowl optics to determine if the chuck
adaptor is installed. The optic signal is sampled once the START key is
pressed in the Load Disposable screen. For the single lens, a signal returned
that is between 100 A/D points and 1200 A/D points results in a bowl-size
determination, and the following screen asks the user to confirm the bowl
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80Principles of operation
!
status.
$8720$7,&
BOWL TYPE CONFIRMATION
The white, 70ml bowl adaptor has
been detected in the centrifuge
well.
Confirm using the choices below.
Press YES if you are using the white bowl adaptor
Press NO if you are NOT using the bowl adaptor
Figure 5, 70 mL bowl confirmation screen
Once the device enters Fill for the first time, the optic signal is sampled one last
time to confirm the correct bowl size is installed.
If the bowl size is a 70 mL blow-molded bowl, once the device enters Fill the
line sensor is used to transition between the Fill and Wash sequence and the
bowl optic sensor is no longer used. Once in Fill, the screen adds a symbol
inside the bowl icon to represent the bowl size. This symbol for the 70 mL blowmolded bowl is “M” (for mini volume, US software only). This symbol will remain
on the display (screen) until the device leaves the Fill sequence.
FILL BOWL
M
Press MODE to enter MANUAL
Figure 6, Bowl recognition icon screen
P/N SM-CS5-01-EN, Manual revision: ABHaemonetics® Cell Saver® 5/5+ Service Manual
AUTOMATIC
Processed Vol:
Wash Volume:
Reinfusion Vol:0 ml
Bowls Processed:
Pump Rate:125 ml/min
xx ml
0 ml
0
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Principles of operation81
125/225 mL bowl
If 70 mL bowl adaptor is not in place, the bowl volume is determined during the
first Fill cycle of a procedure. When the air-fluid meniscus passes the bowl
optics, the volume is read. If that volume is less than 165 mL, the bowl is 125
mL [indicated by L in the bowl icon, US software only]. Otherwise it is a 225 mL
Latham bowl [indicated by H in the bowl icon, US software only]. These icons
(shown below) remain on the screen until the device leaves the Fill sequence.
Table 40
L
H
125 mL bowl
225 mL bowl
Figure 7, Typical single lens optic signal output (cell salvage)
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82Principles of operation
Sequester
The following figure represents single lens optics sequestering-algorithm.
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Principles of operation83
Bowl optics - dual lens
Sampled every 100 msec
Moving average of last 3 samples
Detection of the supernatant level
At the beginning of the first Fill cycle, an optic reading is taken as a reference
on air. As the Fill cycle continues, the system waits for a measurable step (at
least 50 digits to ensure we are out of noise).This measurable step is
considered the trigger to the supernatant level (air supernatant interface).
Once the supernatant level is detected, the screen adds a symbol inside the
bowl icon to represent the detection of the supernatant and the bowl size
determination. If an “H” or “225 ML” appears, the supernatant has been
detected and the bowl size is a 225 mL bowl. If an “L” or “125 ML” appears, the
supernatant has been detected and the bowl size is a 125 mL bowl. If an “M”
or “70” appears, the optics have determined a 70 mL chuck adaptor is installed.
In the CS5, these symbols are displayed in the US software, only. They remain
on the screen until the device leaves the Fill sequence.
In the CS5+, these symbols will remain throughout the procedure. In addition,
once the meniscus is detected during the Fill sequence, an “m” will appear
inside the right arrow on the screen until the device leaves the Fill sequence.
Example screen:
Supernatant is detected and the bowl size = 125 mL in CS5+.
FILL BOWL
m
Press MODE twice to enter EMERGENCY option
125
ML
AUTOMATIC
Processed Vol:
Wash Volume:
Reinfusion Vol:0 ml
Bowls Processed:
Pump Rate:300 ml/min
xx ml
0 ml
0
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84Principles of operation
Trip to Wash
As the bowl is filling, a threshold (level 1) is detected at 1200 digits. Level 1 is
the point at which slope detection is activated. The bowl continues to fill as long
as the signal keeps rising (slope detection) and no air detection is encountered
until the signal reaches 1800 digits (level 2). This is the maximum RBC level or
Trip-to-Wash point in the algorithm. This way, the algorithm will always look for
the peak of the optic signal and thus adapt itself to the variation of reflectivity
of red cells depending on their condition.
Slope detection
When the optic signal returned reaches the threshold of 1200 digital counts
(level 1), the volume and bowl-optic signal, which is processed every 250
milliseconds, is stored in a table if processed volume has increased. The slope
is then calculated by the following formula:
if bowl optic > 0, 0 otherwise.
slope
BowlOptic
---------------------------------=
Volume
Slope detection algorithm:
Store the slope value when level 1 is reached: SSL
if (slope < SSL/RelTrigger1) or (slope < AbsTrigger2) then Trip-to-Wash
else if (bowl optic sample > level 2) then Trip-to-Wash
Failsafe trip point
If the red line sensor value is less than 50 digital counts and the bowl optics
value is greater than 700 digital counts, increment a continuous counter
(samples/10 sec). Otherwise, reset the continuous counter to zero. If the
continuous counter is greater than 20 and the centrifuge on time is greater than
50 seconds, trip to Wash.
Bowl size recognition
70 mL bowl
The 70 mL bowl-protocol utilizes the bowl optics to determine if the chuck
adaptor is installed. The optic signal is sampled once the START key is
1.
RelTrigger is a parameter used to set the sensitivity of the relative slope and
is set to 2. This value was determined by testing done in Europe.
2.
AbsTrigger is a parameter used to set the sensitivity of the absolute slope
and is set to 50. This value was determined by testing done in Europe.
The difference between the absolute trigger and relative trigger is that the relative trigger takes incoming hematocrit into account by adjusting the trigger
relative to the slope measured when level 1 was crossed.
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Principles of operation85
pressed in the Load Disposable screen. For the dual lens, a signal returned that
is greater than 100 A/D points results in a bowl-size determination-override (Fig
2-3). The CS5/CS5+ considers the chuck adaptor installed and thinks the
device will be running the 70 mL blow-molded bowl protocol. Once the device
enters Fill for the first time, the optic signal is sampled one last time to confirm
the correct bowl size is installed.
If the bowl size is a 70 mL blow-molded bowl, once the device enters Fill the
line sensor is used to transition between the Fill and Wash sequence and the
bowl-optic sensor is no longer used. Once in Fill, the screen adds a symbol
inside the bowl icon to represent the bowl size. This symbol for the 70 mL blowmolded bowl is “M” (for mini volume) or 70.
125/225 mL bowl
If 70 mL bowl is not detected, at the beginning of the first Fill cycle an optic
reading is taken as a reference on air. As the Fill cycle continues, the system
waits for a measurable step (at least 50 digits to ensure we are out of noise).
The volume at which the step occurs will determine the bowl size [< 165 mL:
125 mL bowl (indicated by “L” or “125 ML” in bowl icon); > 165 mL: 250 mL bowl
(indicated by “H” or “225 ML” in bowl icon)]. In parallel, the line sensors would
be scanned for a 200 digital-count change from a clear-tubing installation
reference, as a backup for the bowl optics.
Note: For 70/125/225 mL bowls, in the CS5+ the symbols inside the bowl icons
remain on the screen throughout the procedure. In the CS5, the symbols
remain on the screen until the device leaves the Fill or Conc sequence.
In the CS5, the symbols are displayed inside the bowl icons in the US software,
only.
Recentrifuge delay in Fill
If the bowl optic signal returned is greater than level 2 or the slope detection
determines a Trip-to-Wash, but the centrifuge has not been running for 50
seconds the pumps slow to 25 mL/min and a recentrifuge delay occurs to
ensure that the centrifuge had ample time to pack the cells. The recentrifuge
delay is determined by a timer started at the beginning of the Fill sequence. As
an example, if the Trip-to-Wash signal was sent to the computer and the
centrifuge had been running for 30 seconds, the recentrifuge time would be the
remaining time to reach 50 seconds. In this case, it would be 20 seconds. This
feature is only used in the Automatic mode and is not used in the Emergency
mode. Once the time-out finishes, the pump returns back to its programmed
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86Principles of operation
speed and continues filling the bowl until another Trip-to-Wash signal is
sensed.
Figure 9, Typical dual-lens-optic signal output (cell salvage)
Sequester
The following figure represents a dual-lens optics sequestering algorithm.
Figure 10, Typical dual-lens optic signal output (sequester)
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Principles of operation87
Line sensors
TurbidityThe full range of the A/D converter is 5 volts and 4096 counts (12-bit A/D).
Power-on self
test (POST)
During the power-on self test (POST), the red and yellow/green (Y/G) line
sensor values are read and tested for calibration limits of 300 from their
prescribed calibration point of 3050 A/D counts. If either line sensor reading is
outside the limits an error message is generated and displayed on the screen.
Line sensor compensation
This is a reading of the current value of the red and yellow/green (Y/G) linesensors and if they fall within the prescribed calibration limits as stated above
a determination is made to reset the dynamic range to 3050. This will happen
one time only and occurs during the power-on self test (POST).
Line sensor compensation criteria
The centrifuge cover must be closed.
The bowl-optics value must be below 100 A/D counts (no bowl is installed)
for a singles-lens-optic system and defaults as < 100 for dual lens optics
system.
No manifold sensed (no disposable is loaded).
If all of the criteria above are met:
Get the current line sensor’s red and Y/G reading:
Ten samples are read from the A/D line for the red and Y/G line sensor.
These samples are averaged to determine a current A/D reading.
Determine the line-sensor offset value:
3050 is subtracted from each line-sensor’s A/D value. This new value is
the offset value and is stored in NVRAM.
Determine the compensated line sensor value for the red and Y/G line
sensor. See “Formula” on page 87.
Formula
(Current line sensor is ready * 3050) / (3050 + line sensor offset value)
If any of the criteria is not met the line-sensor compensation is not performed
and the current value stored in NVRAM will be used as the red and yellow/
green
(Y/G) line sensor offset.
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88Principles of operation
FillEffluent quality (cell salvage)
The red line-sensor determines effluent quality during Fill. There are five levels
of bowl-effluent quality. These levels are seen by the microprocessor, as
counts from the A/D converter, which provide the following limits:
1500 and above (best quality)
1100
750
500 or below (worst quality)
These rates were determined by studies in the blood lab and by observers in
our clinical units. Another factor, hysteresis, is incorporated. Exceeding the
bounds of any range (advancing into another) causes the limit to shift by 35
counts to make it more difficult to cross back the other way.
Pump rates
The 5 levels of effluent quality are associated with 5 pump rates in Fill and
Concentrate sequence, and 5 rates per bowl size as shown in Table 41.
This will affect the pump rates in the Automatic mode only. Pump rates are not
by effluent quality in the Manual and Emergency modes of operation..
Table 41, Effluent quality as it affects pump rates in mL/min
Pump rates in mL/min
Blood quality FillGreatGoodFairAveragePoor
225 mL standard bowl600500400350300
125 mL low volume bowl300275250225200
70 mL blow-molded bowlNot Monitored
Concentrate
225 mL standard bowl500450400300200
125 mL low-volume bowl250225200175100
70 mL blow-molded bowlNot Monitored
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Principles of operation89
Wash (70 mL
bowl)
The flow chart, below, demonstrates the algorithm for Trip-to-Wash using the
70 mL bowl.
Figure 11, 70 mL bowl line sensor Trip-to-Wash
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90Principles of operation
Minimum Wash (125/225 mL bowl)
The best effluent quality seen by the red line-sensor during Fill is used to
determine Wash volume. Readings during Fill, above 1100, cause Wash
volumes of 1000 mL to be used for the standard bowl and 750 mL to be used
for the low-volume bowl. Reading below 1100 cause volumes of 1500 mL and
1000 mL in the standard and low-volume bowls, respectively.
Pump speed
70 mL bowl
For the 70 mL bowl, the pump rate in Wash ranges from 75 to 100 mL/min.
Pump rates in Wash are adjusted from 100 mL/min to 75 mL/min when 5/6 of
the programmed minimum Wash has been completed.
125/225 mL bowl
For a standard size bowl, the pump rate in Wash ranges from 250 to 500 mL/
min. A low-volume bowl washes in the range of 200-300 mL/min. Pump rates
in Wash are adjusted every second if the rate is decreasing, every 6 seconds
if it is increasing. The rate will fall by 50 mL/min if the slope of the signal from
the red line sensor is negative. If the slope is positive, the rate will increase by
50 mL/min.
Red cell spillage
70 mL bowl
A spill is seen as a fall below 490 counts. Within 1 (1) second (worst case), the
pump rate will drop to 75 mL/min.
125/225 mL bowl
A spill is seen as a fall below 490 counts. Within 1 (1) second (worst case), the
pump rate will drop to 50 mL/min. Adjustments will proceed normally following
a spill; however, the maximum rate will be decreased to 50 mL/min less than
the rate at which the spill occurred (this prevents a saw-tooth effect in which
the pump rates oscillate between 50 and 500).
Free hemoglobin
The yellow/green (Y/G) line sensor is used to measure free Hgb in the bowl
effluent. If, at the end of Wash, the measured free Hgb is more than 50 mgdL
(noncalibrated reading, based on laboratory studies), the volume of saline used
will be increased by 250 mL for the 125/225 mL bowl protocol and 75 mL for
the 70 mL bowl protocol. This will continue 2 times or until the reading shows
free Hgb levels below 50 mg/dl.
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Principles of operation91
SequesterEffluent quality
The red line sensor is used to determine the quality of cells during the collection
of PRP in the Assisted mode of sequester only. While the optic algorithm
determines the time when PRP is to be collected, the red line-sensor is
providing A/D counts to the microprocessor to determine when the bowl is full
and when the red cells are leaving the bowl. The red line-sensor A/D counts
are updated every time the optic algorithm is run and is used to determine slope
for filtering purposes.
Full bowl determination
When the Fill or Conc sequence begins, a red line sensor reading is taken after
20 mLs have been processing in the bowl. This value is stored and used as the
starting value of a clear line sensor with no fluid passing through it. Once the
bowl is full, a mixture of air and plasma cross the face of the sensor and create
a diffused reflection response, and the reading will be erratic until the sensor
sees fluid only. At the time the sensor sees this air and plasma (foam), the
device considers the bowl full and evaluates the variable set for air
management. If the operator selected no for the prompt “PPP Bag for Air?”, the
pump is stopped to allow the operator the change the clamps. If the operator
selected yes, processing continues uninterrupted and only the screen is
updated.
Logic formula
If red line sensor reading > (ref value + 600 A/D counts)
OR
If red line sensor reading < (ref value - 600 A/D counts)
THEN
The bowl is full.
Red cell detection
After the bowl is full, the device is collecting PPP. During this period, a circular
buffer is storing the last two mLs of red line sensor readings. A rate of change
or slope is calculated from the circular buffer and stored from this buffer every
time the optic algorithm is run. When the optic algorithm determines the start
of PRP collection a 10 mL RBC detection delay starts counting mL processed.
Once 10 mL of platelets have been collected the red line-sensor is enabled. As
red cells cross the face of the red line-sensor, the reflective signal decreases
causing the calculated slope to decrease. When the slope is less than –99 for
25 consecutive readings, the algorithm considers that red cells are leaving the
bowl. At this time, the extended PRP collection starts and continues until the
programmed volume has been processed. A red line-sensor reading of 500 A/
D counts or less for 6 consecutive readings is used as a backup for detection
red cells.
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92Principles of operation
Logic formula
If the slope of the red line sensor readings < –99 (for 25 consecutive readings)
and 10 mL of platelets have been collected.
OR
If red line sensor reading <= failsafe of 500 AD (for 6 consecutive readings) and
10 mL of platelets have been collected.
THEN
Red cells detected – start extended PRP collection volume.
Figure 12, Typical red line sensor signal output (sequester)
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Principles of operation93
Table 43,
Sequence70 mL bowl
AutomaticManual
Fill125125
Wash
From Fill100100
From Conc7575
Empty/Return100100
Concentrate125125
Sequester
Table 44, Sequester
Sequence225 mL bowl125 mL bowl
Manual/assistedManual/assisted
Fill6060
Empty400/250/200400/250/200
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94Principles of operation
Air detector
The air detector, on the CS5/CS5+, is sampled every 100 msec, while the
pump is turning. Based on the rate of the pump, the volume pumped over the
last 100 msec is considered to be either air or fluid, depending on the value at
the sensor. A sliding window, 12 mL wide, is continuously updated. Any time a
total of 9 mL is seen within a 12 mL window for a 125/225 mL bowl and a total of
4.5 mL is seen within a 12 mL window for a 70 mL bowl, the software reports
this event as an air detect. Each cycle has a priming volume in which air detects
are not reported. These are shown in Table 45 and Table 46.
Table 45, 225/125 mL bowl priming volumes
Priming volume (mL)Air volume in 12 mL
Fill459
Concentrate559
Wash509
Empty159
Return159
Table 46, 70 mL bowl priming volumes
Priming volume
(mL)
Fill454.5
Concentrate554.5
Wash504.5
Empty54.5
Return54.5
In addition, a secondary air detector window is functioning during the Wash
cycle. In some real-world cases, a column of saline can become suspended
between the pump and bowl and cause the Wash cycle to progress without
actually pumping any fluid into the bowl. The secondary air detector window
looks for at least 12 mL of air in a 48 mL moving window. If this secondary
check is found to be true, the CS5/CS5+ will give the operator the option of
restarting the Wash cycle from the beginning.
Air volume in 12 mL
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Principles of operation95
Reservoir levelsensor
The reservoir level sensor is sampled every 1000 msec. The level detected
must be above the requested level (either start for an empty bowl or resume for
a bowl, which has been partially filled with red cells) for four consecutive
readings to begin the Fill cycle. The level sensor is tared in the Fill cycle if air
is detected and the volume pumped since the trip is more than 100 mL (thus
preventing inadvertent taring if the line from the reservoir is clamped).
In addition, no increase in tare can exceed the weight of 400 mL. This prevents
taring with excessive weight (some foreign object) on the reservoir.
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96Principles of operation
Clamped linesensor
The clamped line sensor (CLS) is sampled every 400 msec during Empty and
Return cycles. If 8 consecutive readings average 8 PSI (at 31 A/D counts per
PSI) or more, a clamped line is reported. The CLS is tared at instrument powerup, and at the beginning and end of each successful Empty cycle (in case the
disposable has relaxed since the initial tare) except after filling the bowl in the
Concentrate mode. Once the operator presses the START key, at the CLS
message, the device assumes the operator has relieved the pressure in the
line. If a decrease of 2 PSI or greater is detected upon resuming, a re-tare of
the sensor is initiated. During the empty or return cycle, the number of clamped
line sensor messages are accumulated. If that number accumulates to greater
than three, a re-tare of the sensor is forced at this point. Once the cycle ends,
the accumulated value is reset to zero and the CLS is tested for a 2 PSI
decrease for re-taring.
This feedback is sent back to the CPU; the signal name is CLAMP LINE. This
signal is brought into U2 (AD620BR, an instrumentation amplifier), where it is
conditioned and scaled.
P/N SM-CS5-01-EN, Manual revision: ABHaemonetics® Cell Saver® 5/5+ Service Manual
Page 97
Principles of operation97
CRC16 and checksum
A CRC16 and Checksum can be performed to check the integrity of the
EPROM. This is performed within the DIAGNOSTICS.
Moving the highlighted cursor to the CRC16 value and pressing the YES
key will allow the calculation of the ROM-cycle redundancy-check value
over 16-bit and display it in hexadecimal format. This operation takes
approximately 31 seconds.
Moving the highlighted cursor to the CHKSUM value and pressing the
YES key will allow the calculation of the ROM checksum and display it in
hexadecimal format. This operation takes approximately 28 seconds.
Haemonetics® Cell Saver® 5/5+ Service ManualP/N SM-CS5-01-EN, Manual revision: AB
Page 98
98Principles of operation
Data acquisition card (european software only)
The data card is an optional device for the Cell Saver 5/5+. It consists of a
combination of hardware and software that allows the transfer of serial data in
a safe manner according to medical device standards, in and out of the
devices, from and to a peripheral device.
The data card monitors software commands sent out by the unit on the serial
port, to command the board functionality such as switching between barcode
scanner and RS232 port, peripheral power supply selection, and disabling of
data transmission.
The data card is compatible with earlier released software protocol revisions
supporting data transmission. The HaemoData is an optional device that allows
printing Cell Saver 5/5+ procedure data to a printer.
The various components of the system are the following:
The data card (86198-01) is mounted on the inside of the Cell Saver 5/5+
rear panel and has one external RS232 port, accessible on the back of the
Cell Saver 5/5+ device. The data port (DB9), dedicated to an RS232
connection, includes a DC power-supply pin.
General
features
CS5/CS5+ CPU interface
The data card is connected to the CS5/5+ CPU through the RS232 port
(J104 of the CPU board).
Printer connection
It is possible to connect an external serial printer to the DB9 port with DC
power. This external device is powered from the DB9 port. 2 printers are
available: thermal printer and non-thermal printer.