GSI TECHNOLOGY GS882ZV18, GS882ZV36BB Service Manual
GS882ZV18/36BB/D-333/300/250/200
119-bump and 165-bump BGA
9Mb Pipelined and Flow Through
Commercial Temp
Industrial Temp
Synchronous NBT SRAM
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high
/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip parity encoding and error detection
• LBO
pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-bump BGA and 165-bump FPBGA
packages
• Pb-Free 119-bump and 165-bump BGA packages available
Functional Description
The GS882ZV18/36B is a 9Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Paramter Synopsis
t
KQ
Pipeline
3-1-1-1
Flow Through
2-1-1-1
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
333 MHz–200 MHz
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS882ZV18/36B may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS882ZV18/36B is implemented with GSI's high
performance CMOS technology and is available in JEDECstandard 119-bump BGA and 165-bump FPBGA packages.
-333 -300 -250 -200 Unit
2.5
3.0
245
275
4.5
4.5
195
220
2.5
3.3
225
250
5.0
5.0
180
200
2.5
4.0
195
220
5.5
5.5
155
175
3.0
5.0
165
185
6.5
6.5
140
155
) must be tied to a power
ns
ns
mA
mA
ns
ns
mA
mA
1.8 V V
1.8 V I/O
DD
Rev: 1.03 3/2005 1/33 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS882ZV18/36BB/D-333/300/250/200
GS882ZV36B Pad Out—119-Bump BGA—Top View (Package B)
1234567
A V
DDQ
AANCAAV
DDQ
B NC E2 AADVA E3 NC
C NC A A V
D DQ
E DQC DQC V
F V
C DQPC V
DDQ
DQC V
SS
SS
SS
DD
ZQ V
E1 V
G V
AANC
DQPB DQB
SS
DQB DQB
SS
DQB V
SS
DDQ
G DQC DQC BC ABB DQB DQB
H DQC DQC V
J V
DDQ
V
DD
K DQD DQD V
SS
NC V
SS
W V
DD
CK V
SS
NC V
SS
DQB DQB
V
DD
DDQ
DQA DQA
L DQD DQD BD NC BA DQA DQA
M V
DDQ
N DQD DQD V
P DQD DQPD V
R NC A LBO V
DQD V
SS
SS
SS
CKE V
A1 V
A0 V
DD
DQA V
SS
SS
SS
DQA DQA
DQPA DQA
DDQ
FT APE
T NC NC A A A NC ZZ
U V
DDQ
TMS TDI TCK TDO NC V
DDQ
Rev: 1.03 3/2005 2/33 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS882ZV18/36BB/D-333/300/250/200
GS882ZV18B Pad Out—119-Bump BGA—Top View (Package B)
1234567
A V
DDQ
AANCAAV
DDQ
B NC E2 AADVA E3 NC
C NC A A V
D DQ
E NC DQ
F V
B NC V
B V
DDQ
NC V
SS
SS
SS
DD
ZQ V
E1 V
G V
AANC
DQPA NC
SS
SS
SS
NC DQA
DQA V
DDQ
G NC DQB BB ANCNCDQA
H DQB NC V
J V
DDQ
V
DD
K NC DQB V
SS
NC V
SS
W V
DD
CK V
SS
NC V
SS
DQA NC
V
DD
DDQ
NC DQA
L DQB NC NC NC BA DQA NC
M V
DDQ
DQB V
N DQB NC V
P NC DQP
B V
R NC A LBO V
SS
SS
SS
CKE V
A1 V
A0 V
DD
SS
SS
SS
NC V
DDQ
DQA NC
NC DQA
FT APE
T NC A A NC A A ZZ
U V
DDQ
TMS TDI TCK TDO NC V
DDQ
Rev: 1.03 3/2005 3/33 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS882ZV18/36BB/D-333/300/250/200
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1234567891011
ANC
BNC
CNCNC
DNC
ENC
FNC
GNC
HFT
J
K
L
DQB NC V
DQB NC V
DQB NC V
AE1BB NC E3 CKE ADV A17 A A18 A
AE2NCBACK W G NC ANC B
V
DQB V
DQB V
DQB V
DQB V
MCH NC V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC DQA C
NC DQA D
NC DQA E
NC DQA F
NC DQA G
NC ZQ ZZ H
V
V
V
DDQ
DDQ
DDQ
DQA NC J
DQA NC K
DQA NC L
M
N
DQB NC V
DQB DNU V
PNCNC
RLBO
NC A ATMSA0 TCK A A A AR
DDQ
DDQ
A ATDIA1 TDO A A ANC P
V
DD
V
SS
V
SS
V
SS
V
SS
NC NC NC V
V
DD
SS
V
V
DDQ
DDQ
DQA NC M
NC NC N
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03 3/2005 4/33 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS882ZV18/36BB/D-333/300/250/200
165 Bump BGA—x36 Common I/O—Top View (Package D)
1234567891011
ANC
BNC
C
D
E
F
G
HFT
J
K
L
DQC NC V
DQC DQC V
DQC DQC V
DQC DQC V
DQC DQC V
MCH NC V
DQD DQD V
DQD DQD V
DQD DQD V
AE1BC BB E3 CKE ADV A17 ANC A
AE2BDBA CK W G NC ANC B
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC DQB C
DQB DQB D
DQB DQB E
DQB DQB F
DQB DQB G
NC ZQ ZZ H
V
V
V
DDQ
DDQ
DDQ
DQA DQA J
DQA DQA K
DQA DQA L
M
N
DQD DQD V
DQD DNU V
PNCNC
RLBO
NC A ATMSA0 TCK A A A AR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
DDQ
DDQ
V
DD
V
SS
V
SS
V
SS
V
SS
NC NC NC V
V
DD
SS
V
V
DDQ
DDQ
DQA DQA M
NC DQA N
A ATDIA1 TDO A A ANC P
Rev: 1.03 3/2005 5/33 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS882ZV18/36BB/D-333/300/250/200
GS882ZV18/36B BGA Pin Description
Symbol Type Description
A0, A1 I Address field LSBs and Address Counter Preset Inputs
A I Address Inputs
DQ
A
DQB
DQC
DQD
B
A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC — No Connect
CK I Clock Input Signal; active high
CKE
W
E
1 I Chip Enable; active low
E
3 I Chip Enable; active low
E
2 I Chip Enable; active high
G
ADV I Burst address counter advance enable; active high
ZZ I Sleep mode control; active high
FT
LBO
PE
ZQ I
TMS
TDI
TDO
TCK
MCH
DNU
V
DD
V
SS
V
DDQ
I/O Data Input and Output pins
I Clock Enable; active low
I Write Enable; active low
I Output Enable; active low
I Flow Through or Pipeline mode; active low
I Linear Burst Order mode; active low
I 9th Bit Enable; active low (119-bump BGA only)
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
I Scan Test Mode Select
I Scan Test Data In
O Scan Test Data Out
I Scan Test Clock
— Must Connect High
—Do Not Use
I Core power supply
I I/O and Core Ground
I Output driver power supply
Rev: 1.03 3/2005 6/33 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS882ZV18/36BB/D-333/300/250/200
Functional Details
Clocking
Deassertion of the Clock Enable (CKE
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load
activation is accomplished by asserting all three of the Chip Enable inputs (E
inputs will deactivate the device.
) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
pin (ADV) held low, in order to load the new address. Device
1, E2, and E3). Deassertion of any one of the Enable
Function W
BA BB BC BD
Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L
Write all Bytes L L L L L
Write Abort/NOP L H H H H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE
chip enables (E
1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
is asserted low, all three
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B
A, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.03 3/2005 7/33 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Synchronous Truth Table
GS882ZV18/36BB/D-333/300/250/200
Operation Type Address CK CKE
Read Cycle, Begin Burst R External L-H L L H X L H L L L Q
Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10
NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2
Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10
Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3
Write Cycle, Continue Burst B Next L-H L H X L X X X X L D 1,3,10
Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10
Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z
Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z
Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z
Deselect Cycle D None L-H L L L H L H L X L High-Z
Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z 1
Sleep Mode None X X X X X X X X X H High-Z
Clock Edge Ignore, Stall Current L-H H X X X X X X X L - 4
ADV W Bx E1 E2 E3 G ZZ DQ Notes
1
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G
can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx
6. All inputs, except G
7. Wait states can be inserted by setting CKE
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
= High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
and ZZ must meet setup and hold times of rising clock edge.
high.
Rev: 1.03 3/2005 8/33 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS882ZV18/36BB/D-333/300/250/200
Pipelined and Flow Through Read Write Control State Diagram
D
B
Deselect
R
D
W
New Read New Write
R
B
R
W
W
R
R
Burst Read Burst Write
B
Key Notes
ƒ
Current State (n)
Input Command Code
Transition
Next State (n+1)
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
D
W
B
W
B
DD
n n+1 n+2 n+3
Clock (CK)
Command
Current State Next State
ƒ
ƒƒƒ
Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram
Rev: 1.03 3/2005 9/33 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS882ZV18/36BB/D-333/300/250/200
Pipeline Mode Data I/O State Diagram
Intermediate Intermediate
Key
ƒ
Transition
Current State (n) Next State (n+2)
W
B
High Z
(Data In)
Input Command Code
R
D
Intermediate
Transition
Intermediate State (N+1)
Intermediate
W
High Z
B
D
Intermediate
R
B
Data Out
W
(Q Valid)
Intermediate
R
D
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
n n+1 n+2 n+3
Clock (CK)
Command
Current State
ƒ
ƒƒƒ
Intermediate
Next State
State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.03 3/2005 10/33 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Loading...