GSI TECHNOLOGY GS88237BB-333, GS88237BB-300, GS88237BB-250, GS88237BB-200, GS88237BB-333I Service Manual
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GS88237BB/D-333/300/250/200
119- & 165-Bump BGA
256K x 36
Commercial Temp
Industrial Temp
9Mb SCD/DCD Sync Burst SRAM
Features
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO
pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-bump and 165-bump BGA packages
• Pb-Free 119-bump and 165-bump BGA packages available
) and/or Global Write (GW) operation
/low output drive
Functional Description
Applications
The GS88237BB/D is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1
inputs (ADSP
BW
, GW) are synchronous and are controlled by a positiveedge-triggered clock input (CK). Output enable (G
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP
subsequent burst addresses are generated internally and are
controlled by ADV
configured to count in either linear or interleave order with the
Linear Burst Order (LBO
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
, ADSC, ADV), and write control inputs (Bx,
or ADSC inputs. In Burst mode,
. The burst address counter may be
) input. The Burst function need not
), address burst control
) and power
333 MHz–200 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
SCD and DCD Pipelined Reads
The GS88237BB/D is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM.
DCD SRAMs pipeline disable commands to the same degree
as read commands. SCD SRAMs pipeline deselect commands
one stage less than read commands. SCD RAMs begin turning
off their outputs immediately after the deselect command has
been captured in the input registers. DCD RAMs hold the
deselect command for one full cycle and then begin turning off
their outputs just after the second rising edge of clock. The user
may configure this SRAM for either mode of operation using
the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW
) input combined with one or more individual byte write
signals (Bx
writing all bytes at one time, regardless of the Byte Write
control inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88237BB/D operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output
power (V
internal circuits and are 3.3 V and 2.5 V compatible.
). In addition, Global Write (GW) is available for
) pins are used to decouple output noise from the
DDQ
Parameter Synopsis
-333 -300 -250 -200 Unit
2.0
2.2
2.3
4.0
2.7
5.0nsns
Pipeline
3-1-1-1
3.3 V Curr
2.5 V Curr
Rev: 1.04 3/2005 1/29 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
t
KQ
tCycle
(x36) 435 395 330 270 mA
(x36) 435 395 330 270 mA
3.0
3.3
GS88237BB/D-333/300/250/200
GS88237B Pad Out—119-Bump BGA—Top View (Package B)
1234567
A
B
C
D
E
F
G
H
J
K
L
V
DDQ
NC NC A4 ADSC A15 A17 NC
NC A5 A3 V
DQC4 DQC9 V
DQC3 DQC8 V
V
DDQ
DQC2 DQC6 BC ADV BB DQB6 DQB2
DQC1 DQC5 V
V
DDQ
DQD1 DQD5 V
DQD2 DQD6 BD SCD BA DQA6 DQA2
A6 A7 ADSP A8 A9 V
A14 A16 NC
DQB9 DQB4
SS
DQB8 DQB3
SS
DQB7 V
SS
DQB5 DQB1
SS
NC V
SS
DD
DQA5 DQA1
DQC7 V
V
DD
SS
SS
SS
SS
NC V
SS
DD
ZQ V
E1 V
G V
GW V
DD
CK V
V
DDQ
DDQ
DDQ
M
N
P
R
T
U
V
DDQ
DQD3 DQD8 V
DQD4 DQD9 V
NC A2 LBO V
NC NC A10 A11 A12 NC ZZ
V
DDQ
DQD7 V
SS
SS
SS
BW V
A1 V
A0 V
V
DD
SS
SS
SS
DDQ
DNU
DQA7 V
DQA8 DQA3
DQA9 DQA4
/
A
13 PE
TMS TDI TCK TDO NC V
DDQ
DDQ
Rev: 1.04 3/2005 2/29 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237BB/D-333/300/250/200
165 Bump BGA—x36 Common I/O—Top View (Package D)
1234567891011
ANC
BNC
C
D
E
F
G
HV
J
K
DQC NC V
DQC DQC V
DQC DQC V
DQC DQC V
DQC DQC V
/NCMCL NC V
DDQ
DQD DQD V
DQD DQD V
AE1BC BB E3 BW ADSC ADV ANC A
AE2BDBA CK GW G ADSP ANC B
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC DQB C
DQB DQB D
DQB DQB E
DQB DQB F
DQB DQB G
NC ZQ ZZ H
V
V
DDQ
DDQ
DQA DQA J
DQA DQA K
L
M
N
DQD DQD V
DQD DQD V
DQD SCD V
PNCNC
RLBO
NC A ATMSA0 TCK A A A AR
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
DDQ
DDQ
DDQ
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC NC NC V
V
V
DD
DD
SS
V
V
V
DDQ
DDQ
DDQ
DQA DQA L
DQA DQA M
NC DQA N
A ATDIA1 TDO A A A A17 P
Rev: 1.04 3/2005 3/29 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237BB/D-333/300/250/200
GS882V37 BGA Pin Description
Symbol Type Description
A0, A1 I Address field LSBs and Address Counter Preset Inputs
A I Address Inputs
DQ
A
DQB
DQC
DQD
B
A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC — No Connect
NC — No Connect
CK I Clock Input Signal; active high
BW
GW
E
1 I Chip Enable; active low
E
3 I Chip Enable; active low
E
2 I Chip Enable; active high
G
ADV
ADSC
, ADSP I Address Strobe (Processor, Cache Controller); active low
ZZ I Sleep mode control; active high
LBO
PE
ZQ I
TMS
TDI
TDO
TCK
MCL
SCD
V
DD
V
SS
V
DDQ
I/O Data Input and Output pins
I Byte Write—Writes all enabled bytes; active low
I Global Write Enable—Writes all bytes; active low
I Output Enable; active low
I Burst address counter advance enable; active l0w
I Linear Burst Order mode; active low
I 9th Bit Enable; active low (only on 119-bump BGA)
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
I Scan Test Mode Select
I Scan Test Data In
O Scan Test Data Out
I Scan Test Clock
— Must Connect Low
— Single Cycle Deselect/Dual Cyle Deselect Mode Control
I Core power supply
I I/O and Core Ground
I Output driver power supply
Rev: 1.04 3/2005 4/29 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237B Block Diagram
GS88237BB/D-333/300/250/200
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
Register
DQ
A0
A1
D0
D1
Counter
Load
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Q0
Q1
A0
A1
A
Memory
Array
QD
36
4
DQ
Register
36
Register
DQ
E1
E2
E3
G
ZZ
Note: Only x36 version shown for simplicity.
Power Down
Control
Register
DQ
Register
DQ
Register
DQ
DQx1–DQx9
Rev: 1.04 3/2005 5/29 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237BB/D-333/300/250/200
Mode Pin Functions
Mode Name Pin Name State Function
Burst Order Control LBO
Power Down Control ZZ
Single/Dual Cycle Deselect Control SCD
FLXDrive Output Impedance Control ZQ
9th Bit Enable PE
Note:
There are pull-up devices onthe ZQ, SCD pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
L Linear Burst
H Interleaved Burst
L or NC Active
H
L Dual Cycle Deselect
H or NC Single Cycle Deselect
L High Drive (Low Impedance)
H or NC Low Drive (High Impedance)
L Activate DQPx I/Os (x18/x36 mode)
H or NC Deactivate DQPx I/Os (x16/x32 mode)
Standby, I
DD
= I
SB
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.04 3/2005 6/29 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237BB/D-333/300/250/200
Byte Write Truth Table
Function GW BW BA BB BC BD Notes
Read H H X X X X 1
Read HL HHHH1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4
Write all bytesHLLLLL2, 3, 4
Write all bytesLXXXXX
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “
C” and “D” are only available on the x36 version.
A, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
Rev: 1.04 3/2005 7/29 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Simplified State Diagram
X
Deselect
WR
GS88237BB/D-333/300/250/200
Simple Synchronous OperationSimple Burst Synchronous Operation
W
X
First Write
WR
Burst Write
CW CR
R
CR
R
CR
R
First Read
Burst Read
X
CRCW
XX
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G
2. The upper portion of the diagram assumes active use of only the Enable (E1
that ADSP
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC
assumes ADSP
Rev: 1.04 3/2005 8/29 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
is tied high and ADSC is tied low.
is tied high and ADV is tied low.
) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
is tied low.
control inputs and
Simplified State Diagram with G
X
Deselect
WR
GS88237BB/D-333/300/250/200
W
X
First Write
W
X
Burst Write
CW CR
R
CR
R
CR
W
CW
W
CW
R
First Read
R
Burst Read
X
CRCW
X
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G
2. Use of “Dummy Reads” (Read Cycles with G
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in grey tone assume G
Data Input Set Up Time.
Rev: 1.04 3/2005 9/29 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
High) may be used to make the transition from read cycles to write cycles without passing
has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
.
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