GSI TECHNOLOGY GS88237BB-250V, GS88237BB-200V, GS88237BB-250IV, GS88237BB-200IV, GS88237BD-250V Service Manual
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GS88237BB/D-xxxV
119- & 165-Bump BGA
256K x 36
Commercial Temp
Industrial Temp
9Mb SCD/DCD Sync Burst SRAM
Features
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-bump and 165-bump BGA packages
• RoHS-compliant 119-bump and 165-bump BGA packages
available
Functional Description
Applications
The GS88237BB/D-xxxV is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
ADSP, ADSC, ADV), and write control inputs (Bx, BW,
inputs (
GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
ADSP or ADSC inputs. In Burst mode, subsequent
G) and power down
250 MHz–200 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
either linear or interleave order with the Linear Burst Order (
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
SCD and DCD Pipelined Reads
The GS88237BB/D-xxxV is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(
BW) input combined with one or more individual byte write
signals (
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS88237BB/D-xxxV operates on a 1.8 V or 2.5 V power
supply. All inputs are 1.8 V or 2.5 V compatible. Separate output
power (V
internal circuits and are 1.8 V or 2.5 V compatible.
Bx). In addition, Global Write (GW) is available for
) pins are used to decouple output noise from the
DDQ
LBO)
Parameter Synopsis
-250 -200 Unit
t
Pipeline
3-1-1-1
Rev: 1.04 6/2006 1/28 © 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
KQ
tCycle
Curr (x36) 330 270 mA
2.5
4.0
2.5
5.0
ns
ns
GS88237BB/D-xxxV
GS88237B-xxxV Pad Out—119-Bump BGA—Top View (Package B)
1234567
A
B
C
D
E
F
G
H
J
K
L
V
DDQ
NC NC A ADSC AANC
NC A A V
DQC DQPC V
DQC DQC V
V
DDQ
DQC DQC BC ADV BB DQB DQB
DQC DQC V
V
DDQ
DQD DQD V
DQD DQD BD SCD BA DQA DQA
A A ADSP AAV
AANC
DQPB DQB
SS
SS
SS
SS
NC V
SS
DQB DQB
DQB V
DQB DQB
DD
DQA DQA
DQC V
V
DD
SS
SS
SS
SS
NC V
SS
DD
ZQ V
E1 V
G V
GW V
DD
CK V
V
DDQ
DDQ
DDQ
M
N
P
R
T
U
V
DDQ
DQD3 DQD V
DQD DQPD V
NC A LBO V
NC NC A A A NC ZZ
V
DDQ
DQD V
SS
SS
SS
BW V
A1 V
A0 V
V
DD
SS
SS
SS
DDQ
DNU
DQA V
DQA DQA
DQPA DQA
/
APE
TMS TDI TCK TDO NC V
DDQ
DDQ
Rev: 1.04 6/2006 2/28 © 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237BB/D-xxxV
165 Bump BGA—x36 Common I/O—Top View
(Package D)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BC BB E3 BW ADSC ADV A NC A
B NC A E2 BD BA CK GW G ADSP A NC B
C DQC NC V
D DQC DQC V
E DQC DQC V
F DQC DQC V
G DQC DQC V
H V
/NCMCL NC V
DDQ
J DQD DQD V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC DQB C
DQB DQB D
DQB DQB E
DQB DQB F
DQB DQB G
NC ZQ ZZ H
V
DDQ
DQA DQA J
K DQD DQD V
L DQD DQD V
M DQD DQD V
N DQD SCD V
DDQ
DDQ
DDQ
DDQ
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC NC NC V
V
V
V
DD
DD
DD
SS
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DQA DQA K
DQA DQA L
DQA DQA M
NC DQA N
P NC NC A A TDI A1 TDO A A A A17 P
R LBO NC A A TMS A0 TCK A A A A R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.04 6/2006 3/28 © 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237BB/D-xxxV BGA Pin Description
Symbol Type Description
A0, A1 I Address field LSBs and Address Counter Preset Inputs
A I Address Inputs
DQA
DQB
DQC
DQD
BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC — No Connect
NC — No Connect
CK I Clock Input Signal; active high
BW I Byte Write—Writes all enabled bytes; active low
GW I Global Write Enable—Writes all bytes; active low
E1 I Chip Enable; active low
E3 I Chip Enable; active low
E2 I Chip Enable; active high
G I Output Enable; active low
ADV I Burst address counter advance enable; active l0w
ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low
ZZ I Sleep mode control; active high
FT I Flow Through or Pipeline mode; active low
LBO I Linear Burst Order mode; active low
PE I 9th Bit Enable; active low (119-bump BGA only)
ZQ I
TMS
TDI
TDO
TCK
MCL
SCD
V
DD
V
SS
V
DDQ
I/O Data Input and Output pins
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
I Scan Test Mode Select
I Scan Test Data In
O Scan Test Data Out
I Scan Test Clock
— Must Connect Low
— Single Cycle Deselect/Dual Cyle Deselect Mode Control
I Core power supply
I I/O and Core Ground
I Output driver power supply
GS88237BB/D-xxxV
Rev: 1.04 6/2006 4/28 © 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237BB/D-xxxV Block Diagram
GS88237BB/D-xxxV
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
Register
DQ
A0
A1
D0
D1
Counter
Load
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Q0
Q1
A0
A1
A
Memory
Array
QD
36
4
DQ
Register
36
Register
DQ
E1
E2
E3
NC
G
ZZ
Note: Only x36 version shown for simplicity.
Power Down
Control
Register
DQ
Register
DQ
Register
DQ
0
DQx1–DQx9
Rev: 1.04 6/2006 5/28 © 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237BB/D-xxxV
Mode Pin Functions
Mode Name Pin Name State Function
Burst Order Control LBO
Power Down Control ZZ
Single/Dual Cycle Deselect Control SCD
FLXDrive Output Impedance Control ZQ
Note:
There are pull-up devices on the ZQ and SCD pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Burst Counter Sequences
L Linear Burst
H Interleaved Burst
L or NC Active
H
L Dual Cycle Deselect
H or NC Single Cycle Deselect
L High Drive (Low Impedance)
H or NC Low Drive (High Impedance)
Standby, IDD = I
SB
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.04 6/2006 6/28 © 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237BB/D-xxxV
Byte Write Truth Table
Function GW BW BA BB BC BD Notes
Read H H X X X X 1
Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3
Write byte d H L H H H L 2, 3
Write all bytes H L L L L L 2, 3
Write all bytes L X X X X X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.04 6/2006 7/28 © 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237BB/D-xxxV
Synchronous Truth Table
State
Operation Address Used
Deselect Cycle, Power Down None X H X L X X High-Z
Read Cycle, Begin Burst External R L L X X X Q
Read Cycle, Begin Burst External R L H L X F Q
Write Cycle, Begin Burst External W L H L X T D
Read Cycle, Continue Burst Next CR X H H L F Q
Read Cycle, Continue Burst Next CR H X H L F Q
Write Cycle, Continue Burst Next CW X H H L T D
Write Cycle, Continue Burst Next CW H X H L T D
Read Cycle, Suspend Burst Current X H H H F Q
Read Cycle, Suspend Burst Current H X H H F Q
Diagram
5
Key
E1 ADSP ADSC ADV
W
3
DQ
4
Write Cycle, Suspend Burst Current X H H H T D
Write Cycle, Suspend Burst Current H X H H T D
Notes:
1. X = Don’t Care, H = High, L = Low
2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.04 6/2006 8/28 © 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Simplified State Diagram
X
Deselect
WR
GS88237BB/D-xxxV
Simple Synchronous OperationSimple Burst Synchronous Operation
W
X
First Write
WR
Burst Write
CW CR
R
CR
R
CR
R
First Read
Burst Read
X
CRCW
XX
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G
2. The upper portion of the diagram assumes active use of only the Enable (E1
that ADSP
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC
assumes ADSP
Rev: 1.04 6/2006 9/28 © 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
is tied high and ADSC is tied low.
is tied high and ADV is tied low.
) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
is tied low.
control inputs and
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