GSI TECHNOLOGY GS881Z18BT-333, GS881Z18BT-300, GS881Z18BT-250, GS881Z18BT-200, GS881Z18BT-150 Service Manual
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GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
100-Pin TQFP & 165-Bump BGA
9Mb Pipelined and Flow Through
Commercial Temp
Industrial Temp
Synchronous NBT SRAM
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO
pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages
• Pb-Free 100-lead TQFP package available
Functional Description
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
like ZBT, NtRAM, NoBL or other pipelined read/double late
write or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
333 MHz–150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
is implemented with GSI's high performance CMOS
technology and is available in a JEDEC-standard 100-pin
TQFP package.
) must be tied to a power
Paramter Synopsis
-333 -300 -250 -200 -150 Unit
t
KQ
Pipeline
3-1-1-1
Flow Through
2-1-1-1
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
Rev: 1.04 10/2004 1/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2.5
3.0
250
290
4.5
4.5
200
230
2.5
3.3
230
265
5.0
5.0
185
210
2.5
4.0
200
230
5.5
5.5
160
185
3.0
5.0
170
195
6.5
6.5
140
160
3.8
6.7
140
160
7.5
7.5
128
145
ns
ns
mA
mA
ns
ns
mA
mA
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
GS881Z18BT 100-Pin TQFP Pinout (Package T)
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQB
DQB
V
SS
V
DDQ
DQB
DQB
FT
V
DD
NC
V
SS
DQB
DQB6
V
DD
V
SS
DQB
DQB
DQPB
NC
V
SS
V
DDQ
NC
NC
NC
NC
B
B
BA
NC
512K x 18
Top View
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DD
E3
SS
V
V
CK
W
CKE
G
ADV
NC
A
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQPA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
V
SS
NC
V
DD
ZZ
DQ
A
DQA
V
DDQ
V
SS
DQA
DQA
NC
NC
V
SS
V
DDQ
NC
NC
NC
LBO
SS
A
A
A
A
A1A0
TDI
TMS
DD
V
V
A A A A A
TDO
TCK
A
1
A
Rev: 1.04 10/2004 2/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
GS881Z32BT 100-Pin TQFP Pinout (Package T)
NC
DQC
DQ
V
DDQ
V
SS
DQC
DQ
DQC
DQC
V
SS
V
DDQ
DQC
DQC
FT
V
DD
NC
V
SS
DQD
DQD2
V
DDQ
V
DQD
DQD
DQD
DQD
V
V
DDQ
DQD
DQD
NC
SS
SS
1
A
A
10099989796959493929190898887868584838281
1
2
C
C
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D
E
E2
BB
BA
BC
B
256K x 32
Top View
DD
E3
SS
V
V
CK
W
CKE
G
ADV
NC
A
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQ
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
NC
B
A
SS
LBO
A
A
A
A
A1A0
TDI
TMS
DD
V
V
A A A A A
TCK
TDO
A
A
Rev: 1.04 10/2004 3/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
GS881Z36BT 100-Pin TQFP Pinout (Package T)
DQPC
DQC
DQC
V
DDQ
V
SS
DQC
DQC
DQC
DQC
V
SS
V
DDQ
DQC
DQC
FT
V
DD
NC
V
SS
DQD
DQD2
V
DDQ
V
SS
DQD
DQD
DQD
DQD
V
SS
V
DDQ
DQD
DQD
DQPD
1
A
A
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D
E
E2
BB
BA
BC
B
256K x 36
Top View
DD
E3
SS
V
V
CK
W
CKE
G
ADV
NC
A
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
A
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
DQPA
SS
LBO
A
A
A
A
A1A0
TDI
TMS
DD
V
V
A A A A A
TCK
TDO
A
A
Rev: 1.04 10/2004 4/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
100-Pin TQFP Pin Descriptions
Symbol Type Description
A0, A1 In Burst Address Inputs; Preload the burst counter
A In Address Inputs
CK In Clock Input Signal
B
A In Byte Write signal for data inputs DQA1–DQA9; active low
B
B In Byte Write signal for data inputs DQB1–DQB9; active low
B
C In Byte Write signal for data inputs DQC1–DQC9; active low
B
D In Byte Write signal for data inputs DQD1–DQD9; active low
W
E
1 In Chip Enable; active low
E
2 In Chip Enable—Active High. For self decoded depth expansion
E
3 In Chip Enable—Active Low. For self decoded depth expansion
G
ADV In Advance/Load
CKE
NC — No Connect
DQ
A I/O Byte A Data Input and Output pins
DQ
B I/O Byte B Data Input and Output pins
DQ
C I/O Byte C Data Input and Output pins
DQ
D I/O Byte D Data Input and Output pins
ZZ In Power down control; active high
FT
LBO
V
DD
V
SS
V
DDQ
In Write Enable; active low
In Output Enable; active low
; Burst address counter control pin
In Clock Input Buffer Enable; active low
In Pipeline/Flow Through Mode Control; active low
In Linear Burst Order; active low.
In Core power supply
In Ground
In Output driver power supply
Rev: 1.04 10/2004 5/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1234567891011
ANC
BNC
CNCNC
DNC
ENC
FNC
GNC
HFT
J
K
L
DQB NC V
DQB NC V
DQB NC V
AE1BB NC E3 CKE ADV A17 A AA
AE2NCBACK W G ANC B
V
DQB V
DQB V
DQB V
DQB V
MCH NC V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC DQA C
NC DQA D
NC DQA E
NC DQA F
NC DQA G
NC NC ZZ H
V
V
V
DDQ
DDQ
DDQ
DQA NC J
DQA NC K
DQA NC L
M
N
DQB NC V
DQB NC V
PNCNC
RLBO
NC A ATMSA0 TCK A A A AR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
DDQ
DDQ
V
V
DD
SS
V
SS
V
SS
V
SS
NC NC NC V
V
DD
SS
V
V
DDQ
DDQ
DQA NC M
NC NC N
A ATDIA1 TDO A A ANC P
Rev: 1.04 10/2004 6/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
165 Bump BGA—x32 Common I/O—Top View (Package D)
1234567891011
ANC
BNC
CNCNC
D
E
F
G
DQC DQC V
DQC DQC V
DQC DQC V
DQC DQC V
HFT
J
K
L
DQD DQD V
DQD DQD V
DQD DQD V
AE1BC BB E3 CKE ADV A17 ANC A
AE2BDBA CK W G ANC B
V
MCH NC V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC NC C
DQB DQB D
DQB DQB E
DQB DQB F
DQB DQB G
NC NC ZZ H
V
V
V
DDQ
DDQ
DDQ
DQA DQA J
DQA DQA K
DQA DQA L
M
NNCNC
DQD DQD V
V
PNCNC
RLBO
NC A ATMSA0 TCK A A A AR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
DDQ
DDQ
V
V
DD
SS
V
SS
V
SS
V
SS
NC NC NC V
V
DD
SS
V
V
DDQ
DDQ
DQA DQA M
NC NC N
A ATDIA1 TDO A A ANC P
Rev: 1.04 10/2004 7/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
165 Bump BGA—x36 Common I/O—Top View (Package D)
1234567891011
ANC
BNC
C
D
E
F
G
HFT
K
L
DQPC NC V
DQC DQC V
DQC DQC V
DQC DQC V
DQC DQC V
J
DQD DQD V
DQD DQD V
DQD DQD V
MCH NC V
AE1BC BB E3 CKE ADV A ANC A
AE2BDBA CK W G ANC B
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC DQPB C
DQB DQB D
DQB DQB E
DQB DQB F
DQB DQB G
NC NC ZZ H
V
V
V
DDQ
DDQ
DDQ
DQA DQA J
DQA DQA K
DQA DQA L
M
N
DQD DQD V
DQPD NC V
PNCNC
RLBO
NC A ATMSA0 TCK A A A AR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
DDQ
DDQ
V
V
DD
SS
V
SS
V
SS
V
SS
NC NC NC V
V
DD
SS
V
V
DDQ
DDQ
DQA DQA M
NC DQPA N
A ATDIA1 TDO A A ANC P
Rev: 1.04 10/2004 8/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
GS81Z18/32/36D 165-Bump BGA Pin Description
Symbol Type Description
A0, A1 I Address field LSBs and Address Counter Preset Inputs
A I Address Inputs
DQ
A
DQB
DQC
DQD
B
A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC — No Connect
CK I Clock Input Signal; active high
CKE
W
E
1 I Chip Enable; active low
E
3 I Chip Enable; active low
E
2 I Chip Enable; active high
G
ADV I Burst address counter advance enable; active high
ZZ I Sleep mode control; active high
FT
LBO
TMS
TDI
TDO
TCK
MCH
DNU
V
DD
V
SS
V
DDQ
I/O Data Input and Output pins
I Clock Enable; active low
I Write Enable; active low
I Output Enable; active low
I Flow Through or Pipeline mode; active low
I Linear Burst Order mode; active low
I Scan Test Mode Select
I Scan Test Data In
O Scan Test Data Out
I Scan Test Clock
— Must Connect High
—Do Not Use
I Core power supply
I I/O and Core Ground
I Output driver power supply
Rev: 1.04 10/2004 9/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
GS881Z18/32/36B NBT SRAM Functional Block Diagram
NC
NC
DQa–DQn
Parity
Check
SA1’
SA0’
Burst
Counter
18
FT
Write Address
Register 2
K
D Q
K
D Q
Register 1
K
Write Data
K
Sense Amps
Register 2
Write Data
Array
Memory
Write Drivers
FT
K
K
ADV
K
LBO
Write Address
Register 1
Match
Read, Write and
K
W
BA
Control Logic
Data Coherency
K
3
E2
BB
BC
E1
BD
E
CK
G
CKE
SA1
SA0
D Q
A0–An
Rev: 1.04 10/2004 10/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
Functional Details
Clocking
Deassertion of the Clock Enable (CKE
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load
activation is accomplished by asserting all three of the Chip Enable inputs (E
inputs will deactivate the device.
) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
pin (ADV) held low, in order to load the new address. Device
1, E2 and E3). Deassertion of any one of the Enable
Function W
BA BB BC BD
Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L
Write all Bytes L L L L L
Write Abort/NOP L H H H H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE
chip enables (E
1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
is asserted low, all three
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (B
A, BB, BC & BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.04 10/2004 11/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Synchronous Truth Table
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
Operation Type Address CK CKE
Read Cycle, Begin Burst R External L-H L L H X L H L L L Q
Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10
NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2
Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10
Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3
Write Cycle, Continue Burst B Next L-H L H X L X X X X L D 1,3,10
Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10
Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z
Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z
Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z
Deselect Cycle D None L-H L L L H L H L X L High-Z
Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z 1
Sleep Mode None X X X X X X X X X H High-Z
Clock Edge Ignore, Stall Current L-H H X X X X X X X L - 4
ADV W Bx E1 E2 E3 G ZZ DQ Notes
1
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G
can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx
6. All inputs, except G
7. Wait states can be inserted by setting CKE
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
= High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
and ZZ must meet setup and hold times of rising clock edge.
high.
Rev: 1.04 10/2004 12/39 © 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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