Product Preview
GS8640ZV18/36T-300/250/200/167
100-Pin TQFP
72Mb Pipelined and Flow Through
Commercial Temp
Industrial Temp
Synchronous NBT SRAM
Features
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO
pin for Linear or Interleave Burst mode
• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
The GS8640ZV18/36T is a 72Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
300 MHz–167 MHz
1.8 V V
DD
1.8 V I/O
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8640ZV18/36T may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS8640ZV18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDECstandard 100-pin TQFP package.
) must be tied to a power
-300 -250 -200 -167 Unit
t
KQ
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.00 9/2004 1/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
tCycle
Curr
(x18)
Curr (x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr (x32/x36)
2.3
3.3
400
480
5.5
5.5
285
330
2.5
4.0
340
410
6.5
6.5
245
280
3.0
5.0
290
350
7.5
7.5
220
250
3.5
6.0
260
305mAmA
8.0
8.0
210
240mAmA
ns
ns
ns
ns
GS8640ZV18T Pinout
Product Preview
GS8640ZV18/36T-300/250/200/167
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQB
DQB
V
SS
V
DDQ
DQB
DQB
FT
V
DD
V
DD
V
SS
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQPB
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
B
B
BA
Top View
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DD
E3
SS
V
V
2M x 18
CK
W
CKE
A
A
A
A
G
ADV
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQPA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
V
SS
NC
V
DD
ZZ
DQ
A
DQA
V
DDQ
V
SS
DQA
DQA
NC
NC
V
SS
V
DDQ
NC
NC
NC
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
A
A
V
V
A A A A A
A
A
Rev: 1.00 9/2004 2/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8640ZV36T Pinout
Product Preview
GS8640ZV18/36T-300/250/200/167
DQPC
DQC
DQC
V
DDQ
V
SS
DQC
DQC
DQC
DQC
V
SS
V
DDQ
DQC
DQC
FT
V
DD
V
DD
V
SS
DQD
DQD
V
DDQ
V
SS
DQD
DQD
DQD
DQD
V
SS
V
DDQ
DQD
DQD
DQPD
1
A
A
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D
E
E2
BB
BA
BC
B
Top View
DD
E3
SS
V
V
1M x 36
CK
W
CKE
A
A
A
A
G
ADV
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
A
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
DQPA
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
A
V
A
V
A A A A A
A
A
Rev: 1.00 9/2004 3/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8640ZV18/36T-300/250/200/167
TQFP Pin Descriptions
Symbol Type Description
A0, A1 In Burst Address Inputs; Preload the burst counter
A In Address Inputs
CK In Clock Input Signal
B
A In Byte Write signal for data inputs DQA1-DQA9; active low
B
B In Byte Write signal for data inputs DQB1-DQB9; active low
B
C In Byte Write signal for data inputs DQC1-DQC9; active low
B
D In Byte Write signal for data inputs DQD1-DQD9; active low
W
E
1 In Chip Enable; active low
E
2 In Chip Enable; Active High. For self decoded depth expansion
E
3 In Chip Enable; Active Low. For self decoded depth expansion
G
ADV In Advance/Load
CKE
DQ
A I/O Byte A Data Input and Output pins
DQ
B I/O Byte B Data Input and Output pins
DQ
C I/O Byte C Data Input and Output pins
DQ
D I/O Byte D Data Input and Output pins
ZZ In Power down control; active high
FT
LBO
V
DD
V
SS
V
DDQ
NC — No Connect
In Write Enable; active low
In Output Enable; active low
; Burst address counter control pin
In Clock Input Buffer Enable; active low
In Pipeline/Flow Through Mode Control; active low
In Linear Burst Order; active low
In Core power supply
In Ground
In Output driver power supply
Product Preview
Rev: 1.00 9/2004 4/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8640ZV18/36T-300/250/200/167
GS8640ZV18/36 NBT SRAM Functional Block Diagram
Product Preview
DQa–DQn
SA1’
SA0’
Burst
Counter
FT
Write Address
K
D Q
Register 1
K
Write Data
K
Sense Amps
Register 2
Write Data
Array
Memory
Write Drivers
FT
Register 2
K
K
ADV
K
LBO
Write Address
Register 1
Match
Read, Write and
K
W
BA
Control Logic
Data Coherency
BB
BC
K
BD
CK
E3
E2
E1
G
CKE
SA1
SA0
D Q
A0–An
Rev: 1.00 9/2004 5/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
GS8640ZV18/36T-300/250/200/167
Functional Details
Clocking
Deassertion of the Clock Enable (CKE
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load
activation is accomplished by asserting all three of the Chip Enable inputs (E
inputs will deactivate the device.
) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
pin (ADV) held low, in order to load the new address. Device
1, E2 and E3). Deassertion of any one of the Enable
Function W
Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L
Write all Bytes L L L L L
Write Abort/NOP L H H H H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE
chip enables (E
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
BA BB BC BD
is asserted Low, all three
A, BB, BC, & BD) determine which bytes will be written. All or none may be activated. A write
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.00 9/2004 6/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Synchronous Truth Table
Product Preview
GS8640ZV18/36T-300/250/200/167
Operation Type Address CK CKE
Read Cycle, Begin Burst R External L-H L L H X L H L L L Q
Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10
NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2
Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10
Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3
Write Cycle, Continue Burst B Next L-H L H X L X X X X L D 1,3,10
Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10
Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z
Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z
Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z
Deselect Cycle D None L-H L L L H L H L X L High-Z
Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z 1
Sleep Mode None X X X X X X X X X H High-Z
Clock Edge Ignore, Stall Current L-H H X X X X X X X L - 4
ADV W Bx E1 E2 E3 G ZZ DQ Notes
1
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G
can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx
6. All inputs, except G
7. Wait states can be inserted by setting CKE
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
= High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
and ZZ must meet setup and hold times of rising clock edge.
high.
Rev: 1.00 9/2004 7/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8640ZV18/36T-300/250/200/167
Pipeline and Flow Through Read Write Control State Diagram
Product Preview
D
B
Deselect
R
D
W
New Read New Write
R
B
R
W
W
D
R
R
Burst Read Burst Write
B
Key Notes:
ƒ
Current State (n)
Input Command Code
Transition
Next State (n+1)
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B and D represent input command
codes ,as indicated in the Synchronous Truth Table.
W
B
W
B
DD
n n+1 n+2 n+3
Clock (CK)
Command
Current State Next State
ƒ
ƒƒƒ
Current State and Next State Definition for Pipeline and Flow Through Read/Write Control State Diagram
Rev: 1.00 9/2004 8/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8640ZV18/36T-300/250/200/167
Pipeline Mode Data I/O State Diagram
Product Preview
Intermediate Intermediate
Key
ƒ
Transition
Current State (n) Next State (n+2)
W
B
High Z
(Data In)
Input Command Code
Intermediate State (N+1)
D
R
Intermediate
Transition
Intermediate
W
High Z
B
D
Intermediate
R
B
Data Out
W
(Q Valid)
Intermediate
R
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
D
n n+1 n+2 n+3
Clock (CK)
Command
Current State
ƒ
ƒƒƒ
Intermediate
State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.00 9/2004 9/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8640ZV18/36T-300/250/200/167
Flow Through Mode Data I/O State Diagram
Product Preview
W
B
High Z
(Data In)
Key Notes
ƒ
Current State (n)
Input Command Code
Transition
R
D
Next State (n+1)
W
R
High Z
B
D
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B and D represent input command
codes as indicated in the Truth Tables.
R
B
Data Out
W
(Q Valid)
D
n n+1 n+2 n+3
Clock (CK)
Command
Current State Next State
ƒ
ƒƒƒ
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.00 9/2004 10/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
GS8640ZV18/36T-300/250/200/167
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name Pin Name State Function
Burst Order Control LBO
Output Register Control FT
Power Down Control ZZ
Note:
There is a pull-up device FT
default states as specified in the above tables.
pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the
L Linear Burst
H Interleaved Burst
L Flow Through
H or NC Pipeline
L or NC Active
H
). When this pin is low, a linear burst
Standby, I
DD
= I
SB
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00 9/2004 11/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
GS8640ZV18/36T-300/250/200/167
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKHtKH
tKCtKC
CK
ZZ
tKLtKL
tZZR
tZZHtZZS
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT
found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V
DD
or V
on pipelined parts and VSS on flow
DDQ
signal
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.00 9/2004 12/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
GS8640ZV18/36T-300/250/200/167
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
V
DD
V
DDQ
V
I/O
V
IN
I
IN
I
OUT
P
D
T
STG
T
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Voltage on VDD Pins
Voltage in V
DDQ
Pins
Voltage on I/O Pins
Voltage on Other Input Pins
–0.5 to V
–0.5 to V
–0.5 to 3.6 V
–0.5 to 3.6 V
+0.5 (≤ 3.6 V max.)
DDQ
+0.5 (≤ 3.6 V max.)
DD
V
V
Input Current on Any Pin +/–20 mA
Output Current on Any I/O Pin +/–20 mA
Package Power Dissipation 1.5 W
Storage Temperature –55 to 125
Temperature Under Bias –55 to 125
o
o
C
C
Power Supply Voltage Ranges
Parameter Symbol Min. Typ. Max. Unit Notes
1.8 V Supply Voltage
1.8 V V
I/O Supply Voltage V
DDQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
V
DD1
DDQ1
+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
1.6 1.8 2.0 V
1.6 1.8 2.0 V
Rev: 1.00 9/2004 13/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Logic Levels
Product Preview
GS8640ZV18/36T-300/250/200/167
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage V
Input Low Voltage V
V
DD
I/O Input High Voltage V
V
DDQ
I/O Input Low Voltage V
V
DDQ
IH
IL
IHQ
ILQ
0.6*V
DD
–0.3 —
0.6*V
DD
–0.3 —
—
—
V
0.3*V
V
DDQ
0.3*V
DD
+ 0.3
DD
+ 0.3
DD
V1
V1
V1,3
V1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
3. V
(max) is voltage on V
IHQ
pins plus 0.3 V.
DDQ
+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Undershoot Measurement and Timing Overshoot Measurement and Timing
V
SS
V
50%
– 2.0 V
IH
+ 2.0 V
V
DD
SS
20% tKC
50%
V
DD
V
IL
20% tKC
Capacitance
(TA = 25oC, f = 1 MHZ, V
DD
= 2.5 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance
Input/Output Capacitance
C
IN
C
I/O
Note:
These parameters are sample tested.
Rev: 1.00 9/2004 14/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
V
V
OUT
IN
= 0 V
= 0 V
45pF
67pF
AC Test Conditions
Parameter Conditions
V
DQ
– 0.2 V
DD
V
DD
V
DDQ
/2
/2
Output Load 1
Input high level
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level
Output reference level
Output load Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Product Preview
GS8640ZV18/36T-300/250/200/167
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins)
ZZ Input Current
FT
Input Current
Output Leakage Current
Output High Voltage
Output Low Voltage
V
* Distributed Test Jig Capacitance
I
IL
I
IN1
I
IN2
I
OL
V
OH1
V
OL1
50Ω
DDQ/2
V
IN
V
DD ≥ VIN ≥ VIH
0 V ≤ V
V
DD ≥ VIN ≥ VIL
0 V ≤ V
Output Disable, V
I
= –4 mA, V
OH
I
= 4 mA, V
OL
30pF
= 0 to V
IN
IN
OUT
DDQ
DD
*
DD
≤ V
IH
≤ V
IL
= 0 to V
DD
= 1.6 V V
= 1.6 V
–1 uA 1 uA
–1 uA
–1 uA
–100 uA
–1 uA
–1 uA 1 uA
– 0.4 V
DDQ
— 0.4 V
1 uA
100 uA
1 uA
1 uA
—
Rev: 1.00 9/2004 15/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Operating Currents
Parameter Test Conditions Mode Symbol
I
(x32/
Pipeline
x36)
Through
IL
Pipeline
Operating
Current
Device Selected;
All other inputs
≥V
or ≤ V
IH
Output open
(x18)
Through
Standby
Current
ZZ ≥ V
DD
– 0.2 V
Pipeline
—
Through
Deselect
Current
Device Deselected;
All other inputs
≥ V
or ≤ V
IH
IL
Pipeline
—
Through
Notes:
1. I
DD
and I
apply to any combination of VDD and V
DDQ
2. All parameters listed are worst case scenario.
Flow
Flow
Flow
Flow
I
I
I
I
operation.
DDQ
DD
DDQ
I
DD
DDQ
I
DD
DDQ
I
DD
DDQ
I
I
I
DD
I
DD
SB
SB
Product Preview
GS8640ZV18/36T-300/250/200/167
-300 -250 -200 -167
0
–40
to
to
70°C
85°C
42060440603605038050310403304027035290
30030320302552527525230202502022020240
37030390303152533525270202902024020260
27015290152301525015205152251519515215
100 120 100 120 100 120 100 120
100 120 100 120 100 120 100 120
150 165 140 155 130 146 125 140
135 150 125 140 120 135 120 135
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
85°C
–40
to
35
20
20
15
Unit
mA
mA
mA
mA
mA
mA
mA
mA
Rev: 1.00 9/2004 16/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
AC Electrical Characteristics
Product Preview
GS8640ZV18/36T-300/250/200/167
Parameter Symbol
Unit
Min Max Min Max Min Max Min Max
Clock Cycle Time tKC 3.3 — 4.0 — 5.0 — 6.0 — ns
Clock to Output Valid tKQ — 2.3 — 2.5 — 3.0 — 3.5 ns
Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — ns
-300 -250 -200 -167
Pipeline
Clock to Output in Low-Z
tLZ
1
1.5 — 1.5 — 1.5 — 1.5 — ns
Setup time tS 1.1 — 1.2 — 1.4 — 1.5 — ns
Hold time tH 0.1 — 0.2 — 0.4 — 0.5 — ns
Clock Cycle Time tKC 5.5 — 6.5 — 7.5 — 8.0 — ns
Clock to Output Valid tKQ — 5.5 — 6.5 — 7.5 — 8.0 ns
Flow
Through
Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — ns
Clock to Output in Low-Z
tLZ
1
3.0 — 3.0 — 3.0 — 3.0 — ns
Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — ns
Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — ns
Clock HIGH Time tKH 1.0 — 1.3 — 1.3 — 1.3 — ns
Clock LOW Time tKL 1.2 — 1.5 — 1.5 — 1.5 — ns
Clock to Output in
High-Z
G
to Output Valid tOE — 2.3 — 2.5 — 3.0 — 3.5 ns
to output in Low-Z
G
to output in High-Z
G
ZZ setup time
ZZ hold time
tHZ
tOLZ
tOHZ
tZZS
tZZH
1
1
2
2
1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.0 ns
0 — 0 — 0 — 0 — ns
1
— 2.3 — 2.5 — 3.0 — 3.0 ns
5 — 5 — 5 — 5 — ns
1 — 1 — 1 — 1 — ns
ZZ recovery tZZR 20 — 20 — 20 — 20 — ns
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.00 9/2004 17/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
CK
ADSP
ADSC
ADV
A0–An
GW
Product Preview
GS8640ZV18/36T-300/250/200/167
Pipeline Mode Timing (NBT)
Begin Read A Cont Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect
Burst ReadBurst ReadSingle Write
tKH
tKH
Single WriteSingle Read
tKLtKL
tKCtKC
ADSC initiated read
Single Read
tS
tH
tHtS
tS
tH
ABC
tS
BW
Ba–Bd
E1
E2
E3
DQa–DQd
tHtS
tH
tS
tS
tS
tH
tS
tH
G
tH
E2 and E3 only sampled with ADSP and ADSC
tS
tOHZtOE
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)
E1 masks ADSP
tLZtH
Deselected with E1
tKQXtKQ
tHZ
Rev: 1.00 9/2004 18/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
GS8640ZV18/36T-300/250/200/167
Flow Through Mode Timing (NBT)
Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect
tKLtKL
tKHtKH
CK
tKCtKC
ADSP
ADSC
ADV
A0–An
GW
BW
Ba–Bd
E1
Fixed High
tS
tH
tS
tH
tS
tH
ABC
tS
tH
tS
tH
tS
tH
ADSC initiated read
tS
tH
tS
tH
Deselected with E1
tS
tH
E2
tS
tH
E3
G
DQa–DQd
E2 and E3 only sampled with ADSC
tH
tS
tOHZtOE
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
tKQ
tLZ
tHZ
tKQX
Rev: 1.00 9/2004 19/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
TQFP Package Drawing (Package T)
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
b Lead Width 0.20 0.30 0.40
L1
Product Preview
GS8640ZV18/36T-300/250/200/167
θ
L
c
Pin 1
c Lead Thickness 0.09 — 0.20
D Terminal Dimension 21.9 22.0 22.1
D1 Package Body 19.9 20.0 20.1
E Terminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
e Lead Pitch — 0.65 —
L Foot Length 0.45 0.60 0.75
L1 Lead Length — 1.00 —
Y Coplanarity 0.10
θ Lead Angle 0° — 7°
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
A1
D1
D
e
b
A2
Y
E1
E
Rev: 1.00 9/2004 20/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Ordering Information—GSI NBT Synchronous SRAM
Product Preview
GS8640ZV18/36T-300/250/200/167
Org
4M x 18 GS8640ZV18T-300 NBT Pipeline/Flow Through TQFP 300/5.5 C
4M x 18 GS8640ZV18T-250 NBT Pipeline/Flow Through TQFP 250/6.5 C
4M x 18 GS8640ZV18T-200 NBT Pipeline/Flow Through TQFP 200/7.5 C
4M x 18 GS8640ZV18T-167 NBT Pipeline/Flow Through TQFP 167/8 C
2M x 36 GS8640ZV36T-300 NBT Pipeline/Flow Through TQFP 300/5.5 C
2M x 36 GS8640ZV36T-250 NBT Pipeline/Flow Through TQFP 250/6.5 C
2M x 36 GS8640ZV36T-200 NBT Pipeline/Flow Through TQFP 200/7.5 C
2M x 36 GS8640ZV36T-167 NBT Pipeline/Flow Through TQFP 167/8 C
4M x 18 GS8640ZV18T-300I NBT Pipeline/Flow Through TQFP 300/5.5 I
4M x 18 GS8640ZV18T-250I NBT Pipeline/Flow Through TQFP 250/6.5 I
4M x 18 GS8640ZV18T-200I NBT Pipeline/Flow Through TQFP 200/7.5 I
4M x 18 GS8640ZV18T-167I NBT Pipeline/Flow Through TQFP 167/8 I
2M x 36 GS8640ZV36T-300I NBT Pipeline/Flow Through TQFP 300/5.5 I
2M x 36 GS8640ZV36T-250I NBT Pipeline/Flow Through TQFP 250/6.5 I
2M x 36 GS8640ZV36T-200I NBT Pipeline/Flow Through TQFP 200/7.5 I
2M x 36 GS8640ZV36T-167I NBT Pipeline/Flow Through TQFP 167/8 I
4M x 18 GS8640ZV18GT-300 NBT Pipeline/Flow Through Pb-Free TQFP 300/5.5 C
4M x 18 GS8640ZV18GT-250 NBT Pipeline/Flow Through Pb-Free TQFP 250/6.5 C
4M x 18 GS8640ZV18GT-200 NBT Pipeline/Flow Through Pb-Free TQFP 200/7.5 C
4M x 18 GS8640ZV18GT-167 NBT Pipeline/Flow Through Pb-Free TQFP 167/8 C
2M x 36 GS8640ZV36GT-300 NBT Pipeline/Flow Through Pb-Free TQFP 300/5.5 C
2M x 36 GS8640ZV36GT-250 NBT Pipeline/Flow Through Pb-Free TQFP 250/6.5 C
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640ZV36T-167IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T
= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com
Part Number
1
Type Package
) for a complete listing of current offerings
Speed
(MHz/ns)
2
3
T
A
Status
Rev: 1.00 9/2004 21/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Ordering Information—GSI NBT Synchronous SRAM
Product Preview
GS8640ZV18/36T-300/250/200/167
Org
2M x 36 GS8640ZV36GT-200 NBT Pipeline/Flow Through Pb-Free TQFP 200/7.5 C
2M x 36 GS8640ZV36GT-167 NBT Pipeline/Flow Through Pb-Free TQFP 167/8 C
4M x 18 GS8640ZV18GT-300I NBT Pipeline/Flow Through Pb-Free TQFP 300/5.5 I
4M x 18 GS8640ZV18GT-250I NBT Pipeline/Flow Through Pb-Free TQFP 250/6.5 I
4M x 18 GS8640ZV18GT-200I NBT Pipeline/Flow Through Pb-Free TQFP 200/7.5 I
4M x 18 GS8640ZV18GT-167I NBT Pipeline/Flow Through Pb-Free TQFP 167/8 I
2M x 36 GS8640ZV36GT-300I NBT Pipeline/Flow Through Pb-Free TQFP 300/5.5 I
2M x 36 GS8640ZV36GT-250I NBT Pipeline/Flow Through Pb-Free TQFP 250/6.5 I
2M x 36 GS8640ZV36GT-200I NBT Pipeline/Flow Through Pb-Free TQFP 200/7.5 I
2M x 36 GS8640ZV36GT-167I NBT Pipeline/Flow Through Pb-Free TQFP 167/8 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640ZV36T-167IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T
= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com
Part Number
1
Type Package
) for a complete listing of current offerings
Speed
(MHz/ns)
2
3
T
A
Status
Rev: 1.00 9/2004 22/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
72Mb Sync SRAM Datasheet Revision History
Product Preview
GS8640ZV18/36T-300/250/200/167
DS/DateRev. Code: Old;
New
8640ZVxx_r1
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
Rev: 1.00 9/2004 23/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Loading...