GSI TECHNOLOGY GS840Z18AT-180, GS840Z18AT-166, GS840Z18AT-150, GS840Z18AT-100, GS840Z36AT-180 Service Manual
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GS840Z18/36AT-180/166/150/100
100-Pin TQFP
4Mb Pipelined and Flow Through
Commercial Temp
Industrial Temp
Synchronous NBT SRAMs
Features
• 256K x 18 and 128K x 36 configurations
• User configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• Pin-compatible with 2M, 8M and 16M devices
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO
pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
The GS840Z18/36AT is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
180 MHz–100 MHz
3.3 V V
2.5 V and 3.3 V V
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS840Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS840Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDECstandard 100-pin TQFP package.
) must be tied to a power
DD
DDQ
Parameter Synopsis
–180 –166 –150 –100
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.03 11/2004 1/24 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
tCycle
KQ
t
IDD
t
KQ
tCycle
I
DD
5.5 ns
3.2 ns
335 mA
8 ns
9.1 ns
210 mA
6.0 ns
3.5 ns
310 mA
8.5 ns
10 ns
190 mA
6.6 ns
3.8 ns
280 mA
10 ns
12 ns
165 mA
10 ns
4.5 ns
190 mA
12 ns
15 ns
135 mA
GS840Z18AT Pinout (Package T)
GS840Z18/36AT-180/166/150/100
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQB
DQB
V
SS
V
DDQ
DQB
DQB
FT
V
DD
V
DD
V
SS
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQPB
NC
V
SS
V
DDQ
NC
NC
NC
NC
B
B
BA
NC
256K x 18
Top View
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DD
E3
SS
V
V
CK
W
CKE
G
ADV
NC
NC
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQPA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
V
SS
NC
V
DD
ZZ
DQ
A
DQA
V
DDQ
V
SS
DQA
DQA
NC
NC
V
SS
V
DDQ
NC
NC
NC
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
NC
NC
V
V
A A A A A
A
A
Rev: 1.03 11/2004 2/24 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z36AT Pinout (Package T)
GS840Z18/36AT-180/166/150/100
DQPC
DQC
DQC
V
DDQ
V
SS
DQC
DQC
DQC
DQC
V
SS
V
DDQ
DQC
DQC
FT
V
DD
V
DD
V
SS
DQD
DQD
V
DDQ
V
SS
DQD
DQD
DQD
DQD
V
SS
V
DDQ
DQD
DQD
DQPD
1
A
A
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D
E
E2
BB
BA
BC
B
128K x 36
Top View
DD
E3
SS
V
V
CK
W
CKE
G
ADV
NC
NC
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
A
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
DQA
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
NC
V
NC
V
A A A A A
A
A
Rev: 1.03 11/2004 3/24 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
100-Pin TQFP Pin Descriptions
Symbol Type Description
A0, A1 In Burst Address Inputs; preload the burst counter
A In Address Inputs
CK In Clock Input Signal
B
A In Byte Write signal for data inputs DQA1-DQA9; active low
B
B In Byte Write signal for data inputs DQB1-DQB9; active low
B
C In Byte Write signal for data inputs DQC1-DQC9; active low
B
D In Byte Write signal for data inputs DQD1-DQD9; active low
W
E
1 In Chip Enable; active low
E
2 In Chip Enable; active high; for self decoded depth expansion
E
3 In Chip Enable; active low, for self decoded depth expansion
G
ADV In Advance / Load
CKE
DQ
A I/O Byte A Data Input and Output pins
DQ
B I/O Byte B Data Input and Output pins
DQ
C I/O Byte C Data Input and Output pins
DQ
D I/O Byte D Data Input and Output pins
ZZ In Power down control; active high
FT
LBO
V
DD
V
SS
V
DDQ
NC — No Connect
In Write Enable; active low
In Output Enable; active low
—Burst address counter control pin
In Clock Input Buffer Enable; active low
In Pipeline/Flow Through Mode Control; active low
In Linear Burst Order; active low
In 3.3 V power supply
In Ground
In 3.3 V output power supply for noise reduction
GS840Z18/36AT-180/166/150/100
Rev: 1.03 11/2004 4/24 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18/36AT-180/166/150/100
GS840Z18/36A NBT SRAM Functional Block Diagram
DQa–DQn
SA1’
SA1
SA0’
Burst
SA0
Counter
FT
D Q
K
Sense Amps
Array
Memory
Write Drivers
Write Da ta
Write Data
K
Register 1
K
Register 2
FT
Register 2
Write Address
K
K
D Q
Register 1
Write Address
K
LBO
ADV
K
Match
Read, Write and
W
BA
Control Logic
Data Coherency
K
E3
E2
BB
BC
E1
BD
CK
G
CKE
A0–
Rev: 1.03 11/2004 5/24 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18/36AT-180/166/150/100
Functional Details
Clocking
Deassertion of the Clock Enable (CKE
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipelined Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load
activation is accomplished by asserting all three of the Chip Enable inputs (E
inputs will deactivate the device.
) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
pin (ADV) held low, in order to load the new address. Device
1, E2, and E3). Deassertion of any one of the Enable
Function W
BA BB BC BD
Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L
Write all Bytes L L L L L
Write Abort/NOP L H H H H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE
chip enables (E1
, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address
is asserted low, all three
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (B
A, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving
the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a
double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode,
address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising
edge of clock.
Rev: 1.03 11/2004 6/24 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Synchronous Truth Table
GS840Z18/36AT-180/166/150/100
Operation Type Address CK CKE
Read Cycle, Begin Burst R External L-H L L H X L H L L L Q
Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10
NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2
Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10
Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3
Write Cycle, Continue Burst B Next L-H L H X L X X X X L D 1,3,10
Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10
Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z
Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z
Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z
Deselect Cycle D None L-H L L L H L H L X L High-Z
Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z 1
Sleep Mode None X X X X X X X X X H High-Z
Clock Edge Ignore, Stall Current L-H H X X X X X X X L - 4
ADV W Bx E1 E2 E3 G ZZ DQ Notes
1
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G
can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx
6. All inputs, except G
7. Wait states can be inserted by setting CKE
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
= High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
and ZZ must meet setup and hold times of rising clock edge.
high.
Rev: 1.03 11/2004 7/24 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18/36AT-180/166/150/100
Pipelined and Flow Through Read-Write Control State Diagram
D
B
Deselect
R
D
W
New Read New Write
R
B
R
W
W
R
R
Burst Read Burst Write
B
Key Notes
ƒ
Current State (n)
Input Command Code
Transition
Next State (n+1)
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
D
W
B
W
B
DD
n n+1 n+2 n+3
Clock (CK)
Command
Current State Next State
ƒ
ƒƒƒ
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
Rev: 1.03 11/2004 8/24 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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