GSI TECHNOLOGY GS84018AGB-166, GS84018AGB-150, GS84018AGB-100, GS84032AGB-190, GS84032AGB-180 Service Manual
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GS84018/32/36AT/B-190/180/166/150/100
TQFP, BGA
256K x 18, 128K x 32, 128K x 36
Commercial Temp
Industrial Temp
4Mb Sync Burst SRAMs
Features
• FT pin for user-configurable flow through or pipelined
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC standard 100-lead TQFP or 119-bump BGA
packages
• RoHS-compliant 100-lead TQFP and 119-bump BGA
packages available
Functional Description
Applications
The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS84018/32/36A is
available in a JEDEC standard 100-lead TQFP or 119-Bump
BGA package.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (
(
Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either
ADSP, ADSC, ADV), and write control inputs
G)
ADSP or ADSC inputs. In
Parameter Synopsis
190 MHz–100 MHz
3.3 V V
3.3 V and 2.5 V I/O
Burst mode, subsequent burst addresses are generated
internally and are controlled by
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the
bump 5R in the BGA). Holding the
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding
RAM in Pipelined mode, activating the rising-edge-triggered
Data Output Register.
SCD Pipelined Reads
The GS84018/32/36A is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable
(
BW) input combined with one or more individual byte write
signals (
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS84018/32/36A operates on a 3.3 V power supply and
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
from the internal circuit.
FT mode pin/bump (pin 14 in the TQFP and
Bx). In addition, Global Write (GW) is available for
) pins are used to de-couple output noise
DDQ
ADV. The burst address
LBO) input. The
FT mode pin/bump low
FT high places the
DD
–190 –180 –166 –150 –100
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.17a 4/2006 1/31 © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
tCycle
tCycle
5.3 ns
t
3.0 ns
KQ
I
370 mA
DD
t
7.5 ns
KQ
8.5 ns
I
245 mA
DD
5.5 ns
3.0 ns
335 mA
8 ns
9 ns
210 mA
6.0 ns
3.5 ns
310 mA
8.5 ns
10 ns
190 mA
6.6 ns
3.8 ns
280 mA
10 ns
12 ns
165 mA
10 ns
4.5 ns
190 mA
12 ns
15 ns
135 mA
GS84018/32/36AT/B-190/180/166/150/100
GS84018A 100-Pin TQFP Pinout (Package T)
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQB
DQB
V
SS
V
DDQ
DQB
DQB
FT
V
DD
NC
V
SS
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQPB
NC
V
SS
V
DDQ
NC
NC
NC
NC
B
B
BA
NC
256K x 18
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DD
E3
SS
V
V
Top View
CK
GW
BW
ADSC
ADV
ADSP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQPA
DQA
DQA
V
SS
VDDQ
A
DQ
DQA
V
SS
NC
VDD
ZZ
A
DQ
DQA
VDDQ
V
SS
DQA
DQA
NC
NC
V
SS
VDDQ
NC
NC
NC
G
A
A
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
NC
V
V
NC
A A A A A
A
A
Rev: 1.17a 4/2006 2/31 © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36AT/B-190/180/166/150/100
GS84032A 100-Pin TQFP Pinout (Package T)
V
V
V
V
NC
DQC
DQ
DDQ
V
SS
DQC
DQ
DQC
DQC
V
SS
DDQ
DQC
DQC
FT
V
DD
NC
V
SS
DQD
DQD
DDQ
V
SS
DQD
DQD
DQD
DQD
V
SS
DDQ
DQD
DQD
NC
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
C
C
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
BB
BA
BC
BD
128K x 32
DD
E3
SS
V
V
Top View
CK
GW
BW
ADSC
ADV
ADSP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQ
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
NC
B
A
G
A
A
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
NC
V
V
NC
A A A A A
A
A
Rev: 1.17a 4/2006 3/31 © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36AT/B-190/180/166/150/100
GS84036A 100-Pin TQFP Pinout (Package T)
DQPC
DQC
DQC
V
DDQ
V
SS
DQC
DQC
DQC
DQC
V
SS
V
DDQ
DQC
DQC
FT
V
DD
NC
V
SS
DQD
DQD
V
DDQ
V
SS
DQD
DQD
DQD
DQD
V
SS
V
DDQ
DQD
DQD
DQPD
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
BB
BA
BC
BD
128K x 36
DD
E3
SS
V
V
Top View
CK
GW
BW
ADSC
ADV
ADSP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
A
DQ
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
DQPA
G
A
A
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
NC
V
V
NC
A A A A A
A
A
Rev: 1.17a 4/2006 4/31 © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36AT/B-190/180/166/150/100
TQFP Pin Description
Symbol Type Description
A0, A1 I Address field LSBs and Address Counter preset Inputs
A I Address Inputs
DQA
DQB
DQC
DQD
BW I Byte Write—Writes all enabled bytes; active low
BA, BB I Byte Write Enable for DQA, DQB Data I/’s; active low
BC, BD I Byte Write Enable for DQC, DQD Data I/Os; active low
CK I Clock Input Signal; active high
GW I Global Write Enable—Writes all bytes; active low
E1, E3 I Chip Enable; active low
E2 I Chip Enable; active high
G I Output Enable; active low
ADV I Burst address counter advance enable; active low
ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low
ZZ I Sleep Mode control; active high
FT I Flow Through or Pipeline mode; active low
LBO I Linear Burst Order mode; active low
V
DD
V
SS
V
DDQ
NC - No Connect
I/O Data Input and Output pins
I Core power supply
I I/O and Core Ground
I Output driver power supply
Rev: 1.17a 4/2006 5/31 © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36AT/B-190/180/166/150/100
GS84018A Pad Out—119-Bump BGA—Top View (Package B)
1234567
A
B
C
D
E
F
G
H
J
K
L
V
DDQ
NC E2 AADSCAE3 NC
NC A A V
DQB NC V
NC DQB V
V
DDQ
NC DQB BB ADV NC NC DQA
DQB NC V
V
DDQ
NC DQB V
DQB NC NC NC BA DQA NC
A A ADSP AAV
AANC
DQPA NC
SS
SS
SS
SS
NC V
SS
NC DQA
DQA V
DQA NC
DD
NC DQA
NC V
V
DD
SS
SS
SS
SS
NC V
SS
DD
NC V
E1 V
G V
GW V
DD
CK V
V
DDQ
DDQ
DDQ
M
N
P
R
T
U
V
DDQ
DQB NC V
NC DQPB V
NC A LBO V
NC A A NC A A ZZ
V
DDQ
DQB V
SS
SS
SS
BW V
A1 V
A0 V
DD
SS
SS
SS
NC V
DQA NC
NC DQA
FT ANC
NC NC NC NC NC V
DDQ
DDQ
Rev: 1.17a 4/2006 6/31 © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36AT/B-190/180/166/150/100
GS84032A Pad Out—119-Bump BGA—Top View (Package B)
1234567
A
B
C
D
E
F
G
H
J
K
L
V
DDQ
NC E2 AADSCAE3 NC
NC A A V
DQC NC V
DQC DQC V
V
DDQ
DQC DQC BC ADV BB DQB DQB
DQC DQC V
V
DDQ
DQD DQD V
DQD DQD BD NC BA DQA DQA
A A ADSP AAV
AANC
SS
SS
SS
SS
NC V
SS
NC DQB
DQB DQB
DQB V
DQB DQB
DD
DQA DQA
DQC V
V
DD
SS
SS
SS
SS
NC V
SS
DD
NC V
E1 V
G V
GW V
DD
CK V
V
DDQ
DDQ
DDQ
M
N
P
R
T
U
V
DDQ
DQD DQD V
DQD NC V
NC A LBO V
NC NC A A A NC ZZ
V
DDQ
DQD V
NC NC NC NC NC V
SS
SS
SS
BW V
A1 V
A0 V
DD
SS
SS
SS
FT ANC
DQA V
DQA DQA
NC DQA
DDQ
DDQ
Rev: 1.17a 4/2006 7/31 © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36AT/B-190/180/166/150/100
GS84036A Pad Out—119-Bump BGA—Top View (Package B)
1234567
A
B
C
D
E
F
G
H
J
K
L
V
DDQ
NC E2 AADSCAE3 NC
NC A A V
DQC DQPC V
DQC DQC V
V
DDQ
DQC2 DQC BC ADV BB DQB DQB2
DQC DQC V
V
DDQ
DQD DQD V
DQD DQD BD NC BA DQA DQA
A A ADSP AAV
AANC
DQPB DQB
SS
SS
SS
SS
NC V
SS
DQB DQB
DQB V
DQB DQB
DD
DQA DQA
DQC V
V
DD
SS
SS
SS
SS
NC V
SS
DD
NC V
E1 V
G V
GW V
DD
CK V
V
DDQ
DDQ
DDQ
M
N
P
R
T
U
V
DDQ
DQD DQD V
DQD DQPD V
NC A LBO V
NC NC A A A NC ZZ
V
DDQ
DQD V
SS
SS
SS
BW V
A1 V
A0 V
DD
SS
SS
SS
DQA V
DQA DQA
DQPA DQA
FT ANC
NC NC NC NC NC V
DDQ
DDQ
Rev: 1.17a 4/2006 8/31 © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36AT/B-190/180/166/150/100
BGA Pin Description
Symbol Type Description
A0, A1 I Address field LSBs and Address Counter Preset Inputs
A I Address Inputs
DQA
DQB
DQC
DQD
BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/O’s; active low
CK I Clock Input Signal; active high
BW I Byte Write—Writes all enabled bytes; active low
GW I Global Write Enable—Writes all bytes; active low
E1, E3 I Chip Enable; active low
E2 I Chip Enable; active high
G I Output Enable; active low
ADV I Burst address counter advance enable; active low
ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low
ZZ I Sleep Mode control; active high
FT I Flow Through or Pipeline mode; active low
LBO I Linear Burst Order mode; active low
VDD I Core power supply
VSS I I/O and Core Ground
VDDQ I Output driver power supply
NC - No Connect
I/O Data Input and Output pins
Rev: 1.17a 4/2006 9/31 © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36AT/B-190/180/166/150/100
GS84018/32/36A Block Diagram
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
Register
DQ
A0
A1
D0
D1
Counter
Load
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Q0
Q1
A0
A1
A
Memory
Array
QD
36
4
DQ
Register
36
Register
DQ
E1
E3
E2
FT
G
ZZ
Note: Only x36 version shown for simplicity.
Power Down
Control
Register
DQ
Register
DQ
Register
DQ
1
DQx1–DQx9
Rev: 1.17a 4/2006 10/31 © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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