GSI TECHNOLOGY GS8322Z18B-250I, GS8322Z18B-225I, GS8322Z18B-200I, GS8322Z18B-166I, GS8322Z18B-150I Service Manual

查询GS8322Z18E-133供应商

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

119, 165 & 209 BGA

36Mb Pipelined and Flow Through

Commercial Temp
Industrial Temp

Synchronous NBT SRAM

Features

• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO

pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-, 165- or 209-Bump BGA package

/low output drive

Functional Description

The GS8322Z18/36/72 is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.

250 MHz–133 MHz 2.5

V or 3.3 V V

DD

2.5 V or 3.3 V I/O

Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off­chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.

The GS8322Z18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge­triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.

The GS8322Z18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC­standard 119-bump, 165-bump or 209-bump BGA package.

) must be tied to a power

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

t

(x18/x36)

KQ

(x72)

t

KQ

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

Rev: 11/1/04 1/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tCycle

Curr

(x18)

Curr (x36)
Curr (x72)

t

KQ

tCycle

Curr

(x18)

Curr (x36)
Curr (x72)

2.5

3.0

4.0

285
350
440

6.5

6.5

205
235
315

2.7

3.0

4.4

265
320
410

7.0

7.0

195
225
295

3.0

3.0

5.0

245
295
370

7.5

7.5

185
210
265

3.5

3.5

6.0

220
260
320

8.0

8.0

175
200
255

3.8

3.8

6.7

210
240
300

8.5

8.5

165
190
240

4.0

4.0

7.5

185

mA

215

mA

265

mA

8.5

8.5nsns

155

mA

175

mA

230

mA

ns
ns
ns

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z72C Pad Out—209-Bump BGA—Top View (Package C)

1234567891011

ADQ

BDQ

CDQ

DDQG DQG

E DQP

FDQ

GDQ

HDQ

JDQ

G DQG AE2AADVAE3ADQB DQB A

G DQG BC BG NC W ABBBF DQB DQB B

G DQG BH BD NC E1 NC BE BA DQB DQB C

G DQPC

C DQC

C DQC

C DQC

C DQC

V

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

SS

NC NC G NC NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

KNCNCCKNC

LDQ

MDQ

H DQH

H DQH

V

DDQ

V

SS

V

DDQ

V

SS

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

ZQ

MCH

MCL

MCH

CKE

FT

MCL

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

NC NC NC NC K

V

DDQ

V

SS

V

DDQ

V

SS

DQB DQB D

DQPF DQPB E

DQF DQF F

DQF DQF G

DQF DQF H

DQF DQF J

DQA DQA L

DQA DQA M

NDQ

PDQ

R DQP

TDQ

UDQ

VDQ

WDQ

H DQH

H DQH

D DQPH

D DQD

D DQD NC A NC A A A NC DQE DQE U

D DQD AAAA1AAADQE DQE V

D DQD TMS TDI A A0 A TDO TCK DQE DQE W

V

V

DDQ

V

DDQ

V

SS

SS

V

DDQ

V

SS

V

DDQ

NC NC LBO NC NC

11 x 19 Bump BGA—14 x 22 mm

V

DD

V

SS

V

DD

MCH

ZZ

V

DD

V

DD

V

SS

V

DD

2

Body—1 mm Bump Pitch

V

V

DDQ

V

DDQ

SS

V

V

DDQ

V

DDQ

V

SS

SS

DQA DQA N

DQA DQA P

DQPA DQPE R

DQE DQE T

Rev: 1.04 11/2004 2/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z72 209-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

An I Address Inputs

DQ

A

DQB
DQC
DQD
DQE
DQF
DQG
DQH

I/O Data Input and Output pins

A, BB

B

B

C,BD

B

E, BF, BG,BH

I Byte Write Enable for DQA, DQB I/Os; active low

I Byte Write Enable for DQC, DQD I/Os; active low

I Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

NC — No Connect

CK I Clock Input Signal; active high

E

1

E

3

E

2

G

ADV

ZZ

FT

LBO

MCH

MCH

MCL

W

I Chip Enable; active low

I Chip Enable; active low

I Chip Enable; active high

I Output Enable; active low

I Burst address counter advance enable

I Sleep Mode control; active high

I Flow Through or Pipeline mode; active low

I Linear Burst Order mode; active low

I Must Connect High

I Must Connect High

Must Connect Low

I Write Enable; active low

FLXDrive Output Impedance Control

ZQ

I

Low = Low Impedance [High Drive],
High = High Impedance [Low Drive]

CKE

I Clock Enable; active low

Rev: 1.04 11/2004 3/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z72 209-Bump BGA Pin Description

Symbol Type Description

TMS

TDI

TDO

TCK

V

DD

V

SS

V

DDQ

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

I Core power supply

I I/O and Core Ground

I Output driver power supply

Rev: 1.04 11/2004 4/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z36B Pad Out—119-Bump BGA—Top View (Package B)

1234567

A

V

DDQ

AAAAA

BNCE2AADVAE3

CNCA A

DDQCDQPC

EDQCDQC

F

V

DDQ

DQC

V

SS

V

SS

V

SS

V

DD

ZQ

E1

G

AANCC

V

SS

V

SS

V

SS

DQPB DQB D

DQB DQB E

DQB

V

DDQ

NC B

V

DDQ

GDQCDQCBC ABBDQB DQB G

HDQCDQC

J

V

DDQ

V

DD

KDQDDQD

V

NC

V

SS

SS

LDQDDQDBD

M

V

DDQ

DQD

V

SS

W

V

DD

CK

NC BA DQA DQA L

CKE

V

NC

V

V

SS

SS

SS

DQB DQB H

V

DD

V

DDQ

DQA DQA K

DQA

V

DDQ

A

F

J

M

NDQDDQD

PDQDDQPD

V

SS

V

SS

RNCALBO

A1

A0

V

DD

V

SS

V

SS

DQA DQA N

DQPA DQA P

FT ANCR

TNCNCAAAAZZT

U

V

DDQ

TMS TDI TCK TDO NC

7 x 17 Bump BGA—14 x 22 mm

2

Body—1.27 mm Bump Pitch

V

DDQ

U

Rev: 1.04 11/2004 5/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z18B Pad Out—119-Bump BGA—Top View (Package B)

1234567

A

V

DDQ

AAAAA

BNCE2AADVAE3

CNCA A

DDQBNC

ENCDQB

F

V

DDQ

NC

V

SS

V

SS

V

SS

GNCDQBBB

HDQBNC

J

V

DDQ

V

DD

KNCDQB

V

NC

V

SS

SS

L DQB NC NC NC BA

M

V

DDQ

DQB

V

SS

V

ZQ

DD

E1

G

AANCC

V

SS

V

SS

V

SS

DQPA NC D

NC DQA E

DQA

ANCNCDQAG

V

NC

V

SS

SS

DQA NC H

V

DD

NC DQA K

V

CK

W

DD

DQA NC L

CKE

V

SS

NC

V

DDQ

NC B

V

DDQ

V

DDQ

V

DDQ

A

F

J

M

NDQBNC

PNCDQPB

V

SS

V

SS

RNCALBO

A1

A0

V

DD

V

SS

V

SS

DQA NC N

NC DQA P

FT ANCR

TNCAAAAAZZT

U

V

DDQ

TMS TDI TCK TDO NC

7 x 17 Bump BGA—14 x 22 mm

2

Body—1.27 mm Bump Pitch

V

DDQ

U

Rev: 1.04 11/2004 6/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z18/36 119-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

An I Address Inputs

DQ

A

DQB
DQC
DQD

A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

B

NC — No Connect

CK I Clock Input Signal; active high

I/O Data Input and Output pins

CKE

W

E

1 I Chip Enable; active low

E

3 I Chip Enable; active low

E

2 I Chip Enable; active high

G

I Clock Enable; active low

I Write Enable; active low

I Output Enable; active low

ADV I Burst address counter advance enable

ZZ I Sleep mode control; active high

FT

LBO

ZQ I

TMS

TDI

TDO

TCK

V

DD

V

SS

V

DDQ

I Flow Through or Pipeline mode; active low

I Linear Burst Order mode; active low

FLXDrive Output Impedance Control

Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

I Core power supply

I I/O and Core Ground

I Output driver power supply

BPR1999.05.18

Rev: 1.04 11/2004 7/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

165 Bump BGA—x18 Common I/O—Top View (Package E)

1234567891011

ANC

BNC

CNCNC

DNC

ENC

FNC

GNC

HFT

J

K

L

DQB NC V

DQB NC V

DQB NC V

AE1BB NC E3 CKE ADV A A AA

AE2NCBACK W G A ANC B

V

DQB V

DQB V

DQB V

DQB V

MCH NC V

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

V

SS

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

V

V

V

V

V

V

V

V

SS

DD

DD

DD

DD

DD

DD

DD

DD

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC DQPA C

NC DQA D

NC DQA E

NC DQA F

NC DQA G

NC ZQ ZZ H

V

V

V

DDQ

DDQ

DDQ

DQA NC J

DQA NC K

DQA NC L

M

N

DQB NC V

DQPB NC V

PNCNC

RLBO

A A ATMSA0 TCK A A A AR

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

DDQ

DDQ

V

DD

V

SS

V

SS

V

SS

V

SS

NC NC NC V

V

DD

SS

V

V

DDQ

DDQ

DQA NC M

NC NC N

A ATDIA1 TDO A A ANC P

Rev: 1.04 11/2004 8/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

165 Bump BGA—x36 Common I/O—Top View (Package E)

1234567891011

ANC

BNC

C

D

E

F

G

H FT

K

L

DQPC NC V

DQC DQC V

DQC DQC V

DQC DQC V

DQC DQC V

MCH NC V

J

DQD DQD V

DQD DQD V

DQD DQD V

AE1BC BB E3 CKE ADV A A NC A

AE2BDBA CK W G A ANC B

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

V

SS

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

V

V

V

V

V

V

V

V

SS

DD

DD

DD

DD

DD

DD

DD

DD

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC DQPB C

DQB DQB D

DQB DQB E

DQB DQB F

DQB DQB G

NC ZQ ZZ H

V

V

V

DDQ

DDQ

DDQ

DQA DQA J

DQA DQA K

DQA DQA L

M

N

DQD DQD V

DQPD NC V

PNCNC

RLBO

A A ATMSA0 TCK A A A AR

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

DDQ

DDQ

V

DD

V

SS

V

SS

V

SS

V

SS

NC NC NC V

V

DD

SS

V

V

DDQ

DDQ

DQA DQA M

NC DQPA N

A ATDIA1 TDO A A ANC P

Rev: 1.04 11/2004 9/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z18/36E 165-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

An I Address Inputs

A

18 I Address Input

DQ

A

DQB
DQC
DQD

B

A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

NC — No Connect

CK I Clock Input Signal; active high

CKE

W

E

1 I Chip Enable; active low

E

3 I Chip Enable; active low

E

2 I Chip Enable; active high

I/O Data Input and Output pins

I Clock Enable; active low

I Write Enable; active low

FT

G

I Flow Through / Pipeline Mode Control

I Output Enable; active low

ADV I Burst address counter advance enable; active high

ZQ I

Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

FLXDrive Output Impedance Control

ZZ I Sleep mode control; active high

LBO

TMS

TDI

TDO

TCK

MCH

V

DD

V

SS

V

DDQ

I Linear Burst Order mode; active low

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

— Must Connect High

I Core power supply

I I/O and Core Ground

I Output driver power supply

Rev: 1.04 11/2004 10/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Functional Details

Clocking

Deassertion of the Clock Enable (CKE
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load
activation is accomplished by asserting all three of the Chip Enable inputs (E
inputs will deactivate the device.

) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

pin (ADV) held low, in order to load the new address. Device

1, E2, and E3). Deassertion of any one of the Enable

Function W

BA BB BC BD

Read H X X X X

Write Byte “a” L L H H H

Write Byte “b” L H L H H

Write Byte “c” L H H L H

Write Byte “d” L H H H L

Write all Bytes L L L L L

Write Abort/NOP L H H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE
chip enables (E

1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

is asserted low, all three

presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B

A, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write

cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.

Rev: 1.04 11/2004 11/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Synchronous Truth Table

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Operation Type Address CK CKE

Read Cycle, Begin Burst R External L-H L L H X L H L L L Q

Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10

NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2

Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10

Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3

Write Cycle, Continue Burst B Next L-H L H X L X X X X L D 1,3,10

Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10

Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z

Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z

Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z

Deselect Cycle D None L-H L L L H L H L X L High-Z

Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z 1

Sleep Mode None X X X X X X X X X H High-Z

Clock Edge Ignore, Stall Current L-H H X X X X X X X L - 4

ADV W Bx E1 E2 E3 G ZZ DQ Notes

1

Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese­lect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.

3. G

can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during

write cycles.

4. If CKE

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx

6. All inputs, except G

7. Wait states can be inserted by setting CKE

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

= High = All Byte Write signals are high; Bx = Low = One or more Byte/Write

signals are Low

and ZZ must meet setup and hold times of rising clock edge.

high.

Rev: 1.04 11/2004 12/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.