GSI Technology GS8322V18B, GS8322V18E, GS8322V36B, GS8322V36E, GS8322V72C Service Manual

查询GS8322V18GB-133供应商

Preliminary

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

119-, 165-, & 209-Pin BGA

2M x 18, 1M x 36, 512K x 72

Commercial Temp
Industrial Temp

36Mb S/DCD Sync Burst SRAMs

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 1.8 V +10%/–10% core power supply

• 1.8 V +10%/–10% core power supply

• 1.8 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-, 165-, and 209-bump BGA package

• Pb-Free packages available

Functional Description

Applications

The GS8322V18/36/72 is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

ADSP, ADSC, ADV), and write control inputs (Bx, BW,

inputs (
GW) are synchronous and are controlled by a positive-edge­triggered clock input (CK). Output enable (
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either

ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in

G) and power down

250 MHz–133 MHz

1.8 V V

DD

1.8 V I/O

either linear or interleave order with the Linear Burst Order (
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the
user via the

FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding

FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.

SCD and DCD Pipelined Reads

The GS8322V18/36/72 is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(

BW) input combined with one or more individual byte write

signals (

Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.

LBO)

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

tKQ(x18/x36)

t

(x72)

KQ

tCycle

Curr (x18)
Curr (x36)
Curr (x72)

t

KQ

tCycle

Curr (x18)
Curr (x36)
Curr (x72)

2.5

3.0

4.0

285
350
440

6.5

6.5

205
235
315

2.7

3.0

4.4

265
320
410

7.0

7.0

195
225
295

3.0

3.0

5.0

245
295
370

7.5

7.5

185
210
265

3.5

3.5

6.0

220
260
320

8.0

8.0

175
200
255

3.8

3.8

6.7

210
240
300

8.5

8.5

165
190
240

4.0

4.0

7.5

185
215
265

8.5

8.5nsns

155
175
230

ns
ns
ns

mA
mA
mA

mA
mA
mA

Rev: 1.04 4/2005 1/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

209-Bump BGA—x72 Common I/O—Top View (Package C)

1 2 3 4 5 6 7 8 9 10 11

A DQG DQG A E2 ADSP ADSC ADV E3 A DQB DQB A

B DQG DQG BC BG NC BW A BB BF DQB DQB B

C DQG DQG BH BD NC E1 NC BE BA DQB DQB C

V

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

SS

NC NC G GW NC

V

DDQ

V

V

DDQ

V

V

DDQ

D DQG DQG

E DQPG DQPC

F DQC DQC

G DQC DQC

H DQC DQC

J DQC DQC

K NC NC CK NC

L DQH DQH

M DQH DQH

N DQH DQH

P DQH DQH

R DQPD DQPH

T DQD DQD

V

V

V

DDQ

V

DDQ

V

DDQ

V

SS

SS

SS

V

DDQ

V

V

DDQ

V

V

DDQ

NC NC LBO NC NC

SS

SS

SS

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

DD

ZQ

MCH

MCL

MCL

MCL

FT

MCL

SCD

ZZ

V

DD

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC NC NC NC K

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

V

V

V

V

V

V

V

DDQ

V

DDQ

V

DDQ

DDQ

V

DDQ

V

DDQ

V

SS

SS

SS

SS

SS

SS

DQB DQB D

DQPF DQPB E

DQF DQF F

DQF DQF G

DQF DQF H

DQF DQF J

DQA DQA L

DQA DQA M

DQA DQA N

DQA DQA P

DQPA DQPE R

DQE DQE T

U DQD DQD NC A A A A A A DQE DQE U

V DQD DQD A A A A1 A A A DQE DQE V

W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.04 4/2005 2/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

GS8322V72 209-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs.

An I Address Inputs

DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH

BA, BB

BC,BD

BE, BF, BG,BH

NC — No Connect

CK I Clock Input Signal; active high

GW

E1

E3

E2

G

ADV

ADSP, ADSC

ZZ

FT

LBO

SCD

MCH

MCL

BW

ZQ

TMS

TDI

TDO

TCK

I/O Data Input and Output pins

I Byte Write Enable for DQA, DQB I/Os; active low

I Byte Write Enable for DQC, DQD I/Os; active low

I Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

I Global Write Enable—Writes all bytes; active low

I Chip Enable; active low

I Chip Enable; active low

I Chip Enable; active high

I Output Enable; active low

I Burst address counter advance enable; active low

I Address Strobe (Processor, Cache Controller); active low

I Sleep Mode control; active high

I Flow Through or Pipeline mode; active low

I Linear Burst Order mode; active low

I Single Cycle Deselect/Dual Cycle Deselect Mode Control

I Must Connect High

Must Connect Low

I Byte Enable; active low

I

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

FLXDrive Output Impedance Control

Preliminary

Rev: 1.04 4/2005 3/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

GS8322V72 209-Bump BGA Pin Description (Continued)

Symbol Type Description

Preliminary

V

V

V

DDQ

DD

SS

I Core power supply

I I/O and Core Ground

I Output driver power supply

Rev: 1.04 4/2005 4/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

165-Bump BGA—x18 Commom I/O—Top View (Package E)

1 2 3 4 5 6 7 8 9 10 11

A NC A E1 BB NC E3 BW ADSC ADV A A A

B NC A E2 NC BA CK GW G ADSP A NC B

C NC NC V

D NC DQB V

E NC DQB V

F NC DQB V

G NC DQB V

DDQ

DDQ

DDQ

DDQ

DDQ

H FT MCL NC V

J DQB NC V

K DQB NC V

L DQB NC V

M DQB NC V

N DQPB SCD V

DDQ

DDQ

DDQ

DDQ

DDQ

V

SS

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC A NC V

V

V

V

V

V

V

V

V

V

V

SS

DD

DD

DD

DD

DD

DD

DD

DD

DD

SS

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC DQPA C

NC DQA D

NC DQA E

NC DQA F

NC DQA G

NC ZQ ZZ H

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

DQA NC J

DQA NC K

DQA NC L

DQA NC M

NC NC N

P NC NC A A TDI A1 TDO A A A A P

R LBO A A A TMS A0 TCK A A A A R

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

Rev: 1.04 4/2005 5/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

165-Bump BGA—x36 Common I/O—Top View

(Package E)

1 2 3 4 5 6 7 8 9 10 11

A NC A E1 BC BB E3 BW ADSC ADV A NC A

B NC A E2 BD BA CK GW G ADSP A NC B

C DQPC NC V

D DQC DQC V

E DQC DQC V

F DQC DQC V

G DQC DQC V

DDQ

DDQ

DDQ

DDQ

DDQ

H FT MCL NC V

J DQD DQD V

DDQ

V

SS

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

V

V

V

V

V

V

SS

DD

DD

DD

DD

DD

DD

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC DQPB C

DQB DQB D

DQB DQB E

DQB DQB F

DQB DQB G

NC ZQ ZZ H

V

DDQ

DQA DQA J

K DQD DQD V

L DQD DQD V

M DQD DQD V

N DQPD SCD V

DDQ

DDQ

DDQ

DDQ

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC A NC V

V

V

V

DD

DD

DD

SS

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DQA DQA K

DQA DQA L

DQA DQA M

NC DQPA N

P NC NC A A TDI A1 TDO A A A A P

R LBO A A A TMS A0 TCK A A A A R

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

Rev: 1.04 4/2005 6/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

GS8322V18/36 165-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

An I Address Inputs

DQA
DQB
DQC
DQD

BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)

NC — No Connect

CK I Clock Input Signal; active high

BW I Byte Write—Writes all enabled bytes; active low

GW I Global Write Enable—Writes all bytes; active low

E1 I Chip Enable; active low

E3 I Chip Enable; active low

E2 I Chip Enable; active high

G I Output Enable; active low

ADV I Burst address counter advance enable; active l0w

ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep mode control; active high

FT I Flow Through or Pipeline mode; active low

LBO I Linear Burst Order mode; active low

ZQ I

TMS

TDI

TDO

TCK

MCL

SCD

V

DD

V

SS

V

DDQ

I/O Data Input and Output pins

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

— Must Connect Low

— Single Cycle Deselect/Dual Cyle Deselect Mode Control

I Core power supply

I I/O and Core Ground

I Output driver power supply

Preliminary

Rev: 1.04 4/2005 7/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

119-Bump BGA—x36 Common I/O—Top View

1 2 3 4 5 6 7

Preliminary

A

V

DDQ

A A ADSP A A

V

DDQ

B NC A A ADSC A A NC B

C NC A A

D DQ DQP

E DQ DQ

F

G DQ DQ BC ADV BB DQB DQB G

H DQ DQ

J

C C

C C

V

DDQ

C2 C

C C

V

DDQ

DQ

V

C

DD

K DQD DQD

V

V

V

V

NC

V

SS

SS

SS

SS

SS

V

DD

ZQ

E1

G

GW

V

DD

CK

A A NC C

V

V

V

V

NC

V

SS

SS

SS

SS

SS

DQPB DQB D

DQB DQB E

DQB

V

DDQ

DQB DQB H

V

DD

V

DDQ

DQA DQA K

L DQD DQD BD SCD BA DQA DQA L

M

V

DDQ

DQD

V

SS

BW

V

SS

DQA

V

DDQ

A

F

J

M

N DQD DQD

P DQD DQPD

V

SS

V

SS

R NC A LBO

V

A1

A0

DD

V

SS

V

SS

DQA DQA N

DQPA DQA P

FT A NC R

T NC NC A A A A ZZ T

U

V

DDQ

TMS TDI TCK TDO NC

V

DDQ

7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch

U

Rev: 1.04 4/2005 8/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

119-Bump BGA—x18 Common I/O—Top View

1 2 3 4 5 6 7

Preliminary

A

V

DDQ

A A ADSP A A

V

DDQ

B NC A A ADSC A A NC B

C NC A A

D DQB NC

E NC DQB

F

V

DDQ

NC

V

V

V

SS

SS

SS

V

DD

ZQ

E1

G

A A NC C

V

SS

V

SS

V

SS

DQPA NC D

NC DQA E

DQA

V

DDQ

G NC DQB BB ADV NC NC DQA G

H DQB NC

J

V

DDQ

V

DD

K NC DQB

V

NC

V

SS

SS

GW

V

DD

CK

V

NC

V

SS

SS

DQA NC H

V

DD

V

DDQ

NC DQA K

L DQB NC NC SCD BA DQA NC L

M

V

DDQ

DQB

V

SS

BW

V

SS

NC

V

DDQ

A

F

J

M

N DQB NC

P NC DQPB

V

SS

V

SS

R NC A LBO

V

A1

A0

DD

V

SS

V

SS

DQA NC N

NC DQA P

FT A NC R

T NC A A A A A ZZ T

U

V

DDQ

TMS TDI TCK TDO NC

V

DDQ

7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch

U

Rev: 1.04 4/2005 9/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

GS8322V18/36 119-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

An I Address Inputs

DQA
DQB
DQC
DQD

BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

NC — No Connect

CK I Clock Input Signal; active high

BW I Byte Write—Writes all enabled bytes; active low

GW I Global Write Enable—Writes all bytes; active low

E1 I Chip Enable; active low

G I Output Enable; active low

ADV I Burst address counter advance enable; active low

ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep mode control; active high

FT I Flow Through or Pipeline mode; active low

LBO I Linear Burst Order mode; active low

ZQ I

SCD I Single Cycle Deselect/Dual Cyle Deselect Mode Control

TMS

TDI

TDO

TCK

V

DD

V

SS

V

SS

V

DDQ

I/O Data Input and Output pins

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

I Core power supply

I I/O and Core Ground

I I/O and Core Ground

I Output driver power supply

Preliminary

Rev: 1.04 4/2005 10/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

GS8322V18/36 Block Diagram

Preliminary

A0–An

LBO

ADV

CK

ADSC
ADSP

GW
BW

BA

BB

BC

BD

Register

DQ

A0

A1

D0

D1

Counter

Load

Register

DQ

Register

DQ

Register

DQ

Register

DQ

Q0

Q1

A0

A1

A

Memory

Array

QD

36

4

DQ

Register

36

Register

DQ

E1

FT

G

ZZ

Note: Only x36 version shown for simplicity.

Power Down

Control

Register

DQ

Register

DQ

Register

DQ

SCD

36

36

36

36

DQx1–DQx9

Rev: 1.04 4/2005 11/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Mode Pin Functions

Preliminary

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

Mode Name

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

Single/Dual Cycle Deselect Control SCD

FLXDrive Output Impedance Control ZQ

Note:

There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.

Burst Counter Sequences

Linear Burst Sequence

Pin

Name

State Function

L Linear Burst

H Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

L Dual Cycle Deselect

H or NC Single Cycle Deselect

L High Drive (Low Impedance)

H or NC Low Drive (High Impedance)

Standby, IDD = I

SB

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

Note:

The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.04 4/2005 12/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)

Byte Write Truth Table

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read H L H H H H 1

Write byte a H L L H H H 2, 3

Write byte b H L H L H H 2, 3

Write byte c H L H H L H 2, 3, 4

Write byte d H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4

Write all bytes L X X X X X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

Preliminary

Rev: 1.04 4/2005 13/42 © 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.