GSI TECHNOLOGY GS832218B-250, GS832218B-225, GS832218B-200, GS832218B-166, GS832218B-150 Service Manual

查询GS832218B-133供应商

Preliminary

GS832218(B/E)/GS832236(B/E)/GS832272(C)

119-, 165-, & 209-Pin BGA

2M x 18, 1M x 36, 512K x 72

Commercial Temp
Industrial Temp

36Mb S/DCD Sync Burst SRAMs

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high

/low output drive

• 2.5 V +10%/–10% core power supply

• 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply
pin for Linear or Interleaved Burst mode

• LBO

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW

) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-, 165-, and 209-bump BGA package

Functional Description

Applications

The GS832218/36/72 is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP

) are synchronous and are controlled by a positive-edge-

GW
triggered clock input (CK). Output enable (G
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP
burst addresses are generated internally and are controlled by

. The burst address counter may be configured to count in

ADV
either linear or interleave order with the Linear Burst Order (LBO
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.

, ADSC, ADV), and write control inputs (Bx, BW,

) and power down

or ADSC inputs. In Burst mode, subsequent

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT
Pipeline mode, activating the rising-edge-triggered Data Output
Register.

SCD and DCD Pipelined Reads

The GS832218/36/72 is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

) input combined with one or more individual byte write

(BW
signals (Bx

). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.

Core and Interface Voltages

The GS832218/36/72 operates on a 2.5 V or 3.3 V power supply.

)

All input are 3.3 V and 2.5 V compatible. Separate output power

) pins are used to decouple output noise from the internal

(V

DDQ

circuits and are 3.3 V and 2.5 V compatible.

high places the RAM in

DD

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

ns

4.0

3.8

3.5

3.0

2.5

3.0

4.0

285
350
440

6.5

6.5

205
235
315

2.7

3.0

4.4

265
320
410

7.0

7.0

195
225
295

3.0

5.0

245
295
370

7.5

7.5

185
210
265

3.5

6.0

220
260
320

8.0

8.0

175
200
255

3.8

6.7

210
240
300

8.5

8.5

165
190
240

4.0

7.5

185
215
265

8.5

8.5nsns

155
175
230

ns
ns

mA
mA
mA

mA
mA
mA

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

t

(x18/x36)

KQ

t

(x72)

KQ

tCycle

Curr (x18)
Curr (x36)
Curr (x72)

t

KQ

tCycle

Curr (x18)
Curr (x36)
Curr (x72)

Rev: 1.06 9/2004 1/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS832218(B/E)/GS832236(B/E)/GS832272(C)

209-Bump BGA—x72 Common I/O—Top View (Package C)

1234567891011

ADQ

BDQ

CDQ

DDQ

E DQP

FDQ

GDQ

HDQ

JDQ

G DQG AE2ADSPADSC ADV E3 ADQB DQB A

G DQG BC BG NC BW ABBBF DQB DQB B

G DQG BH BD NC E1 NC BE BA DQB DQB C

V

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

SS

NC NC G GW NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

G DQG

G DQPC

C DQC

C DQC

C DQC

C DQC

KNCNCCKNC

LDQ

MDQ

NDQ

PDQ

H DQH

H DQH

H DQH

H DQH

V

V

DDQ

V

DDQ

V

SS

SS

V

V

DDQ

V

DDQ

V

SS

SS

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

ZQ

MCH

MCL

MCL

MCL

FT

MCL

SCD

ZZ

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

NC NC NC NC K

V

V

DDQ

V

DDQ

V

SS

SS

V

V

DDQ

V

DDQ

V

SS

SS

DQB DQB D

DQPF DQPB E

DQF DQF F

DQF DQF G

DQF DQF H

DQF DQF J

DQA DQA L

DQA DQA M

DQA DQA N

DQA DQA P

R DQP

TDQ

UDQ

VDQ

WDQ

D DQPH

D DQD

D DQD NCAAAAAADQE DQE U

D DQD AAAA1AAADQE DQE V

D DQD TMS TDI A A0 A TDO TCK DQE DQE W

V

DDQ

V

SS

V

DDQ

NC NC LBO NC NC

11 x 19 Bump BGA—14 x 22 mm

V

DD

V

DD

V

DD

2

Body—1 mm Bump Pitch

V

DDQ

V

DDQ

V

SS

DQPA DQPE R

DQE DQE T

Rev: 1.06 9/2004 2/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832218(B/E)/GS832236(B/E)/GS832272(C)

GS832272 209-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs.

An I Address Inputs

DQ

A

DQB
DQC
DQD
DQE
DQF
DQG
DQH

A, BB

B

B

C,BD

B

E, BF, BG,BH

NC — No Connect

CK I Clock Input Signal; active high

GW

E

1

E

3

E

2

G

ADV

ADSP

, ADSC

ZZ

FT

LBO

SCD

MCH

MCL

BW

ZQ

TMS

TDI

TDO

TCK

I/O Data Input and Output pins

I Byte Write Enable for DQA, DQB I/Os; active low

I Byte Write Enable for DQC, DQD I/Os; active low

I Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

I Global Write Enable—Writes all bytes; active low

I Chip Enable; active low

I Chip Enable; active low

I Chip Enable; active high

I Output Enable; active low

I Burst address counter advance enable; active low

I Address Strobe (Processor, Cache Controller); active low

I Sleep Mode control; active high

I Flow Through or Pipeline mode; active low

I Linear Burst Order mode; active low

I Single Cycle Deselect/Dual Cycle Deselect Mode Control

I Must Connect High

Must Connect Low

I Byte Enable; active low

I

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

FLXDrive Output Impedance Control

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

Preliminary

Rev: 1.06 9/2004 3/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832218(B/E)/GS832236(B/E)/GS832272(C)

GS832272 209-Bump BGA Pin Description (Continued)

Symbol Type Description

Preliminary

V

V

V

DDQ

DD

SS

I Core power supply

I I/O and Core Ground

I Output driver power supply

Rev: 1.06 9/2004 4/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS832218(B/E)/GS832236(B/E)/GS832272(C)

165-Bump BGA—x18 Commom I/O—Top View (Package E)

1234567891011

ANC

BNC

CNCNC

DNC

ENC

FNC

GNC

HFT

J

K

L

DQB NC V

DQB NC V

DQB NC V

AE1BB NC E3 BW ADSC ADV A AA

AE2NCBACK GW G ADSP ANC B

V

DQB V

DQB V

DQB V

DQB V

MCL NC V

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

V

SS

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

V

V

V

V

V

V

V

V

SS

DD

DD

DD

DD

DD

DD

DD

DD

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC DQPA C

NC DQA D

NC DQA E

NC DQA F

NC DQA G

NC ZQ ZZ H

V

V

V

DDQ

DDQ

DDQ

DQA NC J

DQA NC K

DQA NC L

M

N

DQB NC V

DQPB SCD V

PNCNC

RLBO

A A ATMSA0 TCK A A A AR

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

DDQ

DDQ

V

DD

V

SS

V

SS

V

SS

V

SS

NC ANCV

V

DD

SS

V

V

DDQ

DDQ

DQA NC M

NC NC N

A ATDIA1 TDO A A A AP

Rev: 1.06 9/2004 5/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS832218(B/E)/GS832236(B/E)/GS832272(C)

165-Bump BGA—x36 Common I/O—Top View (Package E)

1234567891011

ANC

BNC

C

D

E

F

G

DQPC NC V

DQC DQC V

DQC DQC V

DQC DQC V

DQC DQC V

HFT

J

K

L

DQD DQD V

DQD DQD V

DQD DQD V

AE1BC BB E3 BW ADSC ADV ANC A

AE2BDBA CK GW G ADSP ANC B

DDQ

DDQ

DDQ

DDQ

DDQ

MCL NC V

DDQ

DDQ

DDQ

V

SS

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

V

V

V

V

V

V

V

V

SS

DD

DD

DD

DD

DD

DD

DD

DD

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC DQPB C

DQB DQB D

DQB DQB E

DQB DQB F

DQB DQB G

NC ZQ ZZ H

V

V

V

DDQ

DDQ

DDQ

DQA DQA J

DQA DQA K

DQA DQA L

M

N

DQD DQD V

DQPD SCD V

PNCNC

RLBO

A A ATMSA0 TCK A A A AR

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

DDQ

DDQ

V

DD

V

SS

V

SS

V

SS

V

SS

NC ANCV

V

DD

SS

V

V

DDQ

DDQ

DQA DQA M

NC DQPA N

A ATDIA1 TDO A A A AP

Rev: 1.06 9/2004 6/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832218(B/E)/GS832236(B/E)/GS832272(C)

GS832218/36 165-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

An I Address Inputs

DQ

A

DQB
DQC
DQD

A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)

B

NC — No Connect

CK I Clock Input Signal; active high

BW

GW

E

1 I Chip Enable; active low

E

3 I Chip Enable; active low

E

2 I Chip Enable; active high

G

ADV

ADSC

, ADSP I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep mode control; active high

FT

LBO

ZQ I

TMS

TDI

TDO

TCK

MCL

SCD

V

DD

V

SS

V

DDQ

I/O Data Input and Output pins

I Byte Write—Writes all enabled bytes; active low

I Global Write Enable—Writes all bytes; active low

I Output Enable; active low

I Burst address counter advance enable; active l0w

I Flow Through or Pipeline mode; active low

I Linear Burst Order mode; active low

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

— Must Connect Low

— Single Cycle Deselect/Dual Cyle Deselect Mode Control

I Core power supply

I I/O and Core Ground

I Output driver power supply

Preliminary

Rev: 1.06 9/2004 7/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832218(B/E)/GS832236(B/E)/GS832272(C)

119-Bump BGA—x36 Common I/O—Top View

1234567

Preliminary

A

V

DDQ

A A ADSP AA

BNCA AADSC

CNCA A

DDQ

EDQ

F

GDQ

C DQPC

C DQC

V

DDQ

C2 DQC BC ADV BB DQB DQB G

DQC

HDQC DQC

J

KDQ

LDQ

M

V

DDQ

D DQD

D DQD BD SCD BA DQA DQA L

V

DDQ

V

DD

DQD

V

V

V

V

NC

V

V

SS

SS

SS

SS

SS

SS

V

DD

ZQ

E1

G

GW

V

DD

CK

BW

V

V

V

V

NC

V

V

V

DDQ

A

AANCB

AANCC

SS

SS

SS

SS

SS

SS

DQPB DQB D

DQB DQB E

DQB

V

DDQ

DQB DQB H

V

DD

V

DDQ

DQA DQA K

DQA

V

DDQ

F

J

M

NDQ

PDQ

D DQD

D DQPD

V

SS

V

SS

RNCALBO

V

A1

A0

DD

V

SS

V

SS

DQA DQA N

DQPA DQA P

FT ANCR

TNCNCAAAAZZT

U

V

DDQ

TMS TDI TCK TDO NC

7 x 17 Bump BGA—14 x 22 mm

2

Body—1.27 mm Bump Pitch

V

DDQ

U

Rev: 1.06 9/2004 8/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832218(B/E)/GS832236(B/E)/GS832272(C)

119-Bump BGA—x18 Common I/O—Top View

1234567

Preliminary

A

V

DDQ

A A ADSP AA

BNCA AADSC

CNCA A

DDQ

ENCDQ

F

GNCDQ

B NC

V

DDQ

B

NC

B BB ADV NC NC DQA G

HDQB NC

J

V

DDQ

KNCDQ

LDQ

M

B NC NC SCD BA DQA NC L

V

DDQ

V

DD

DQB

B

V

V

V

V

NC

V

V

SS

SS

SS

SS

SS

SS

V

DD

ZQ

E1

G

GW

V

DD

CK

BW

V

V

V

V

NC

V

V

V

DDQ

A

AANCB

AANCC

SS

SS

SS

SS

SS

SS

DQPA NC D

NC DQA E

DQA

V

DDQ

DQA NC H

V

DD

V

DDQ

NC DQA K

NC

V

DDQ

F

J

M

NDQ

B NC

PNCDQP

V

SS

V

B

SS

RNCALBO

V

A1

A0

DD

V

SS

V

SS

DQA NC N

NC DQA P

FT ANCR

TNCAAAAAZZT

U

V

DDQ

TMS TDI TCK TDO NC

7 x 17 Bump BGA—14 x 22 mm

2

Body—1.27 mm Bump Pitch

V

DDQ

U

Rev: 1.06 9/2004 9/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832218(B/E)/GS832236(B/E)/GS832272(C)

GS832218/36 119-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

An I Address Inputs

DQ

A

DQB
DQC
DQD

B

A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

NC — No Connect

CK I Clock Input Signal; active high

BW

GW

E

1 I Chip Enable; active low

G

ADV

ADSP

, ADSC I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep mode control; active high

FT

LBO

ZQ I

SCD I Single Cycle Deselect/Dual Cyle Deselect Mode Control

TMS

TDI

TDO

TCK

V

DD

V

SS

V

SS

V

DDQ

I/O Data Input and Output pins

I Byte Write—Writes all enabled bytes; active low

I Global Write Enable—Writes all bytes; active low

I Output Enable; active low

I Burst address counter advance enable; active low

I Flow Through or Pipeline mode; active low

I Linear Burst Order mode; active low

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

I Core power supply

I I/O and Core Ground

I I/O and Core Ground

I Output driver power supply

Preliminary

Rev: 1.06 9/2004 10/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832218(B/E)/GS832236(B/E)/GS832272(C)

GS832218/36 Block Diagram

Preliminary

A0–An

LBO

ADV

CK

ADSC
ADSP

GW
BW

BA

BB

BC

BD

Register

DQ

A0

A1

D0

D1

Counter

Load

Register

DQ

Register

DQ

Register

DQ

Register

DQ

Q0

Q1

A0

A1

A

Memory

Array

QD

36

4

DQ

Register

36

Register

DQ

E1

FT

G

ZZ

Note: Only x36 version shown for simplicity.

Power Down

Control

Register

DQ

Register

DQ

Register

DQ

SCD

36

36

36

36

DQx1–DQx9

Rev: 1.06 9/2004 11/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Mode Pin Functions

Preliminary

GS832218(B/E)/GS832236(B/E)/GS832272(C)

Mode Name

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

Single/Dual Cycle Deselect Control SCD

FLXDrive Output Impedance Control ZQ

Note:

There are pull-up devices on the ZQ, SCD, and FT
chip will operate in the default states as specified in the above tables.

Burst Counter Sequences

Pin

Name

State Function

L Linear Burst

H Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

L Dual Cycle Deselect

H or NC Single Cycle Deselect

L High Drive (Low Impedance)

H or NC Low Drive (High Impedance)

pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the

Linear Burst Sequence

Standby, I

DD

= I

SB

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

Note:

The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.06 9/2004 12/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS832218(B/E)/GS832236(B/E)/GS832272(C)

Byte Write Truth Table

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read HL HHHH1

Write byte a H L L H H H 2, 3

Write byte b H L H L H H 2, 3

Write byte c H L H H L H 2, 3, 4

Write byte d H L H H H L 2, 3, 4

Write all bytesHLLLLL2, 3, 4

Write all bytesLXXXXX

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs B

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “

C” and “D” are only available on the x36 version.

A, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

Rev: 1.06 9/2004 13/41 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.