GSI TECHNOLOGY GS8320E18T-250, GS8320E18T-225, GS8320E18T-200, GS8320E18T-166, GS8320E18T-150 Service Manual
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Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
100-Pin TQFP
2M x 18, 1M x 32, 1M x 36
Commercial Temp
Industrial Temp
36Mb Sync Burst SRAMs
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO
pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
) and/or Global Write (GW) operation
Functional Description
Applications
The GS8320E18/32/36T is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1
control inputs (ADSP
(Bx
, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV
counter may be configured to count in either linear or
, ADSC, ADV), and write control inputs
, E2, E3), address burst
)
or ADSC inputs. In
. The burst address
250 MHz–133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
interleave order with the Linear Burst Order (LBO
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
DCD Pipelined Reads
The GS8320E18/32/36T is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW
) input combined with one or more individual byte write
signals (Bx
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8320E18/32/36T operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
from the internal circuits and are 3.3 V and 2.5 V compatible.
mode pin (Pin 14). Holding the FT mode
). In addition, Global Write (GW) is available for
) pins are used to decouple output noise
DDQ
) input. The
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
t
KQ
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.01 10/2004 1/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
tCycle
Curr
Curr (x32/x36)
t
KQ
tCycle
Curr
Curr (x32/x36)
(x18)
(x18)
2.5
4.0
285
350
6.5
6.5
205
235
2.7
4.4
265
320
7.0
7.0
195
225
3.0
5.0
245
295
7.5
7.5
185
210
3.5
6.0
220
260
8.0
8.0
175
200
3.8
6.6
210
240
8.5
8.5
165
190
4.0
7.5nsns
185
215mAmA
8.5
8.5nsns
155
175mAmA
GS8320E18/32/36T-250/225/200/166/150/133
GS8320E18 100-Pin TQFP Pinout
Preliminary
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQB
DQB
V
SS
V
DDQ
DQB
DQB
FT
V
DD
NC
V
SS
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQPB
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
B
B
BA
Top View
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DD
E3
SS
V
V
2M x 18
CK
GW
BW
ADSC
ADV
ADSP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQPA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
V
SS
NC
V
DD
ZZ
DQ
A
DQA
V
DDQ
V
SS
DQA
DQA
NC
NC
V
SS
V
DDQ
NC
NC
NC
G
A
A
SS
LBO
A
A
A
A
A1A0
NC
A
DD
A
A
V
V
A A A A A
A
A
Rev: 1.01 10/2004 2/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8320E18/32/36T-250/225/200/166/150/133
GS8320E32 100-Pin TQFP Pinout
Preliminary
NC
DQC
DQ
V
DDQ
V
SS
DQC
DQ
DQC
DQC
V
V
DDQ
DQC
DQC
FT
V
DD
NC
V
SS
DQD
DQD
V
DDQ
V
DQD3
DQD
DQD
DQD
V
V
DDQ
DQD
DQD
NC
SS
SS
SS
1
A
A
10099989796959493929190898887868584838281
1
2
C
C
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D
E
E2
BB
BA
BC
B
Top View
DD
E3
SS
V
V
1M x 32
CK
GW
BW
ADSC
ADV
ADSP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQ
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
NC
B
A
G
A
A
SS
LBO
A
A
A
A
A1A0
NC
A
DD
A
V
V
A
A A A A A
A
A
Rev: 1.01 10/2004 3/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8320E18/32/36T-250/225/200/166/150/133
GS8320E36 100-Pin TQFP Pinout
Preliminary
DQPC
DQC
DQC
V
DDQ
V
SS
DQC
DQC
DQC
DQC
V
SS
V
DDQ
DQC
DQC
FT
V
DD
NC
V
SS
DQD
DQD
V
DDQ
V
SS
DQD3
DQD
DQD
DQD
V
SS
V
DDQ
DQD
DQD
DQPD
1
A
A
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D
E
E2
BB
BA
BC
B
Top View
DD
E3
SS
V
V
1M x 32
CK
GW
BW
ADSC
ADV
ADSP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
A
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
DQPA
G
A
A
SS
LBO
A
A
A
A
A1A0
NC
A
DD
A
V
V
A
A A A A A
A
A
Rev: 1.01 10/2004 4/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8320E18/32/36T-250/225/200/166/150/133
TQFP Pin Description
Symbol Type Description
A0, A1 I Address field LSBs and Address Counter preset Inputs
A I Address Inputs
DQ
A
DQB1
DQC
DQD
NC No Connect
I/O Data Input and Output pins
Preliminary
BW
B
A, BB I Byte Write Enable for DQA, DQB Data I/Os; active low
B
C, BD I Byte Write Enable for DQC, DQD Data I/Os; active low
IByte Write—Writes all enabled bytes; active low
CK I Clock Input Signal; active high
GW
E
1, E3 I Chip Enable; active low
E
2 I Chip Enable; active high
G
ADV
ADSP
, ADSC I Address Strobe (Processor, Cache Controller); active low
I Global Write Enable—Writes all bytes; active low
I Output Enable; active low
I Burst address counter advance enable; active low
ZZ I Sleep Mode control; active high
FT
LBO
V
V
V
DDQ
DD
SS
I Flow Through or Pipeline mode; active low
I Linear Burst Order mode; active low
I Core power supply
I I/O and Core Ground
I Output driver power supply
Rev: 1.01 10/2004 5/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8320E18/32/36T-250/225/200/166/150/133
GS8320E18/32/36 Block Diagram
Preliminary
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
Register
DQ
A0
A1
D0
D1
Counter
Load
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Q0
Q1
A0
A1
A
Memory
Array
QD
36
4
DQ
Register
36
Register
DQ
E1
E2
E3
FT
G
ZZ
Note: Only x36 version shown for simplicity.
Power Down
Control
Register
DQ
Register
DQ
Register
DQ
1
DQx1–DQx9
Rev: 1.01 10/2004 6/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Mode Pin Functions
Mode Name Pin Name State Function
Burst Order Control LBO
Output Register Control FT
Power Down Control ZZ
Note:
There is a pull-up device on the FT
the default states as specified in the above tables.
Burst Counter Sequences
pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
L Linear Burst
H Interleaved Burst
L Flow Through
H or NC Pipeline
L or NC Active
H
Standby, I
DD
= I
SB
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.01 10/2004 7/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Byte Write Truth Table
Function GW BW BA BB BC BD Notes
Read H H X X X X 1
Read HLHHHH1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4
Write all bytesHLLLLL2, 3, 4
Write all bytesLXXXXX
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “
C” and “D” are only available on the x32 and x36 versions.
A, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
Rev: 1.01 10/2004 8/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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