GSI TECHNOLOGY GS816018BT-250, GS816018BT-200, GS816018BT-150, GS816032BT-250, GS816032BT-200 Service Manual
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GS816018/32/36BT-250/200/150
100-Pin TQFP
1M x 18, 512K x 32, 512K x 36
Commercial Temp
Industrial Temp
18Mb Sync Burst SRAMs
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
Applications
The GS816018/32/36BT is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (
(
Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (
and power down control (ZZ) are asynchronous inputs. Burst
ADSP, ADSC, ADV), and write control inputs
G)
250 MHz–150 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
cycles can be initiated with either
Burst mode, subsequent burst addresses are generated
internally and are controlled by
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the
FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding
high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(
BW) input combined with one or more individual byte write
signals (
writing all bytes at one time, regardless of the Byte Write
Bx). In addition, Global Write (GW) is available for
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS816018/32/36BT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
) pins are used to decouple output noise
DDQ
from the internal circuits and are 3.3 V and 2.5 V compatible.
ADSP or ADSC inputs. In
ADV. The burst address
LBO) input. The
DD
FT
Parameter Synopsis
-250 -200 -150 Unit
t
KQ
Pipeline
3-1-1-1
Flow Through
2-1-1-1
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
Rev: 1.03 9/2005 1/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2.5
4.0
295
345
5.5
5.5
225
255
3.0
5.0
245
285
6.5
6.5
200
220
3.8
6.7
200
225
7.5
7.5
185
205
ns
ns
mA
mA
ns
ns
mA
mA
GS816018B 100-Pin TQFP Pinout
GS816018/32/36BT-250/200/150
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQB
DQB
V
SS
V
DDQ
DQB
DQB
FT
V
DD
NC
V
SS
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQPB
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
B
B
BA
Top View
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DD
E3
SS
V
V
1M x 18
CK
GW
BW
ADSC
ADV
ADSP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQPA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
V
SS
NC
V
DD
ZZ
A
DQ
DQA
V
DDQ
V
SS
DQA
DQA
NC
NC
V
SS
V
DDQ
NC
NC
NC
G
A
A
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
A
A
V
V
A A A A A
A
A
Rev: 1.03 9/2005 2/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816032B 100-Pin TQFP Pinout
GS816018/32/36BT-250/200/150
V
V
V
V
NC
DQC
DQ
DDQ
V
SS
DQC
DQ
DQC
DQC
V
SS
DDQ
DQC
DQC
FT
V
DD
NC
V
SS
DQD
DQD
DDQ
V
SS
DQD
DQD
DQD
DQD
V
SS
DDQ
DQD
DQD
NC
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
C
C
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
BB
BA
BC
BD
512K x 32
Top View
DD
E3
SS
V
V
CK
GW
BW
G
ADSC
ADV
ADSP
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQ
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
NC
B
A
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
A
V
V
A
A A A A A
A
A
Rev: 1.03 9/2005 3/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816036B 100-Pin TQFP Pinout
GS816018/32/36BT-250/200/150
DQPC
DQC
DQC
V
DDQ
V
SS
DQC
DQC
DQC
DQC
V
SS
V
DDQ
DQC
DQC
FT
V
DD
NC
V
SS
DQD
DQD
V
DDQ
V
SS
DQD
DQD
DQD
DQD
V
SS
V
DDQ
DQD
DQD
DQPD
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
BB
BA
BC
BD
512K x 36
Top View
DD
E3
SS
V
V
CK
GW
BW
G
ADSC
ADV
ADSP
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
A
DQ
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
DQPA
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
V
V
A
A A A A A
A
A
A
Rev: 1.03 9/2005 4/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816018/32/36BT-250/200/150
TQFP Pin Description
Symbol Type Description
A0, A1 I Address field LSBs and Address Counter preset Inputs
A I Address Inputs
DQA
DQB
DQC
DQD
NC No Connect
BW I Byte Write—Writes all enabled bytes; active low
BA, BB, BC, BD I Byte Write Enable for DQA, DQB Data I/Os; active low
CK I Clock Input Signal; active high
GW I Global Write Enable—Writes all bytes; active low
E1, E3 I Chip Enable; active low
E2 I Chip Enable; active high
G I Output Enable; active low
ADV I Burst address counter advance enable; active low
ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low
ZZ I Sleep Mode control; active high
FT I Flow Through or Pipeline mode; active low
LBO I Linear Burst Order mode; active low
V
DD
V
SS
V
DDQ
I/O Data Input and Output pins
I Core power supply
I I/O and Core Ground
I Output driver power supply
Rev: 1.03 9/2005 5/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816018/32/36B Block Diagram
GS816018/32/36BT-250/200/150
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
Register
DQ
A0
A1
D0
D1
Counter
Load
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Q0
Q1
A0
A1
A
Memory
Array
QD
36
4
DQ
Register
36
Register
DQ
E1
E2
E3
FT
G
ZZ
Note: Only x36 version shown for simplicity.
Power Down
Control
Register
DQ
Register
DQ
Register
DQ
1
DQx1–DQx9
Rev: 1.03 9/2005 6/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Mode Pin Functions
GS816018/32/36BT-250/200/150
Mode Name
Burst Order Control LBO
Output Register Control FT
Power Down Control ZZ
Single/Dual Cycle Deselect Control SCD
FLXDrive Output Impedance Control ZQ
Note:
There is a are pull-up devices on the ZQ and SCD FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
Pin
Name
State Function
L Linear Burst
H Interleaved Burst
L Flow Through
H or NC Pipeline
L or NC Active
H
L Dual Cycle Deselect
H or NC Single Cycle Deselect
L High Drive (Low Impedance)
H or NC Low Drive (High Impedance)
Standby, IDD = I
SB
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note:
The burst counter wraps to initial state on the 5th clock.
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.03 9/2005 7/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816018/32/36BT-250/200/150
Byte Write Truth Table
Function GW BW BA BB BC BD Notes
Read H H X X X X 1
Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4
Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.03 9/2005 8/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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