GSI TECHNOLOGY GS72108TP-8, GS72108TP-10, GS72108TP-12, GS72108TP-15, GS72108TP-8I Service Manual

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GS72108TP/J

SOJ, TSOP

256K x 8

Commercial Temp
Industrial Temp

2Mb Asynchronous SRAM

Features

• Fast access time: 8, 10, 12, 15 ns

• CMOS low power operation: 150/125/110/90 mA at
minimum cycle time.

• Single 3.3 V ± 0.3 V power supply

• All inputs and outputs are TTL-compatible

• Fully static operation

• Industrial Temperature Option: –40° to 85°C

• Package line up

J: 400 mil, 36-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package

Description

The GS72108 is a high speed CMOS Static RAM organized as
262,144 words by 8 bits. Static design eliminates the need for
external clocks or timing strobes. The GS operates on a single

3.3 V power supply and all inputs and outputs are TTL-com-

patible. The GS72108 is available in 400 mil SOJ and 400 mil
TSOP Type-II packages.

SOJ 256K x 8-Pin Configuration

A

A

A

A

A

CE

DQ

DQ

V

V

DQ

DQ

WE

A

A

A

A

A

4

3

2

1

0

1

2

DD

SS

3

4

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

36-pin

400 mil SOJ

8, 10, 12, 15 ns

3.3 V V

Center VDD and V

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

NC

A

A

A

A

OE

DQ

DQ

V

V

DQ

DQ

A

A

A

A

NC

NC

5

6

7

8

SS

DD

9

10

11

12

DD

SS

8

7

6

5

Pin Descriptions

Symbol Description

17

A0–A

DQ

1–DQ8 Data input/output

CE

WE

OE

V

DD

V

SS

NC No connect

Address input

Chip enable input

Write enable input

Output enable input

+3.3 V power supply

Ground

Rev: 1.08 7/2002 1/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TSOP-II 256K x 8-Pin Configuration

GS72108TP/J

NC
NC

A
A
A
A
A
CE
DQ
DQ

V
V
DQ
DQ
WE

A

A

A
A

A

NC
NC

1

2

4

3

2

1

0

1

2

DD

SS

3

4

17

16

15

14

13

3
4

5
6
7
8

9
10
11
12
13

14
15
16
17

18

19
20

21

22

44-pin

400 mil TSOP II

44

43
42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

NC
NC

NC
A
A
A
A
OE
DQ
DQ

V
V
DQ
DQ

A
A
A
NC

NC

NC
NC

5

6

7

8

8

7

SS

DD

6

5

A

9

10

11

12

Block Diagram

A

A

CE

WE

OE

0

Row

Memory Array

Decoder

Address

Input

Buffer

Column

17

Control

Decoder

I/O Buffer

1

DQ

DQ

8

Rev: 1.08 7/2002 2/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Truth Table

GS72108TP/J

CE OE WE DQ1 to DQ

8

H X X Not Selected ISB1, ISB

L L H Read

LX L Write

LH H High Z

Note: X: “H” or “L”

Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage VDD –0.5 to +4.6 V

Input Voltage V

Output Voltage V

IN

OUT

–0.5 to V

(≤ 4.6 V max.)

–0.5 to V

(≤ 4.6 V max.)

DD

DD

+0.5

+0.5

V

V

VDD Current

2

I

DD

Allowable power dissipation PD 0.7 W

Storage temperature T

STG

–55 to 150

o

C

Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec­ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.

Rev: 1.08 7/2002 3/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

GS72108TP/J

Supply Voltage for -10/12/15

Supply Voltage for -8

Input High Voltage V

Input Low Voltage V

Ambient Temperature,

Commercial Range

Ambient Temperature,

Industrial Range

V

DD

V

DD

IH

IL

T

Ac 0 — 70

T

AI

3.0 3.3 3.6 V

3.135 3.3 3.6 V

2.0 —

–0.3 — 0.8 V

–40 — 85

Note:

1. Input overshoot voltage should be less than V

+2 V and not exceed 20 ns.

DD

2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.

Capacitance

Parameter Symbol Test Condition Max Unit

V

DD

+0.3

V

o

C

o

C

Input Capacitance CIN VIN = 0 V 5 pF

Output Capacitance C

OUT VOUT = 0 V 7 pF

Notes:

1. Tested at T

A = 25°C, f = 1 MHz

2. These parameters are sampled and are not 100% tested.

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage

Current

Output Leakage

Current

Output High Voltage V

Output Low Voltage V

IIL

I

LO

OH

OL

Rev: 1.08 7/2002 4/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

VIN = 0 to V

DD

Output High Z

V

OUT = 0 to V

OH

I

LO

I

DD

= –4mA 2.4 —

= +4mA — 0.4 V

– 1 uA 1 uA

–1 uA 1 uA