Preliminary
GS8170DW18/36/72C-333/300/250
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb Σ 1x1 Double Late Write
SigmaRAM™ SRAM
250 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
•Double Late Write mode
•JEDEC-standard SigmaRAM™ pinout and package
•1.8 V +150/–100 mV core power supply
•1.5 V or 1.8 V I/O supply
•Dual Cycle Deselect
•Synchronous Burst operation
•Fully coherent read and write pipelines
•Echo Clock outputs track data output drivers
•ZQ mode pin for user-selectable output drive strength
•Byte write operation (9-bit bytes)
•2 user-programmable chip enable inputs for easy depth expansion
•IEEE 1149.1 JTAG-compatible Boundary Scan
•209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
•Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
-333
Pipeline mode |
tKHKH |
3.0 ns |
|
tKHQV |
1.6 ns |
||
|
SigmaRAM Family Overview
GS8170DW18/36/72 SigmaRAMs (Σ RAM™) are built in compliance with the Σ RAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage CMOS I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
GSI's Σ RAMs are offered in a number of configurations that emulate other synchronous SRAMs, such as Burst RAMs, NBT, Late Write, or Double Data Rate (DDR) SRAMs. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering and write cueing. The Σ RAM family standard allows a user to implement the interface protocol best suited to the task at hand.
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Functional Description
Because Σ RAMs are synchronous devices, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.
The GS8170DW18/36/72C is configured to read in Pipeline mode. In Pipeline mode, single data rate Σ RAMs incorporate a rising-edge-triggered output register. For read cycles, a pipelined SRAM’s output data is staged at the input of an edgetriggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.
GS8170DW18/36/72C Σ RAMs are implemented with GSI's high performance CMOS technology and are packaged in a 209-bump BGA.
Rev: 1.00d 6/2002 |
1/36 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DW18/36/72C-333/300/250
8170DW72C 256K x 72 Pinout
256K x 72 Common I/O—Top View
|
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1 |
2 |
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3 |
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4 |
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5 |
6 |
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7 |
8 |
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9 |
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10 |
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11 |
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A |
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||||||||||||||||
DQg |
DQg |
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A |
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E2 |
A |
ADV |
A |
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E3 |
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A |
DQb |
DQb |
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B |
DQg |
DQg |
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NC |
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A |
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DQb |
DQb |
|||||
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Bc |
Bg |
W |
Bb |
Bf |
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C |
DQg |
DQg |
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NC |
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NC |
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DQb |
DQb |
||||||
Bh |
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Bd |
E1 |
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Be |
Ba |
||||||||||||||||||||||||||||
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(144M) |
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D |
DQg |
DQg |
VSS |
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NC |
NC |
MCL |
NC |
NC |
|
VSS |
DQb |
DQb |
||||||||||||||||||||||
E |
DQg |
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DQc |
VDDQ |
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VDDI |
VDD |
VDD |
VDD |
VDDI |
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VDDQ |
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DQf |
DQb |
||||||||||||||||||||
F |
DQc |
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DQc |
VSS |
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VSS |
VSS |
ZQ |
VSS |
VSS |
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VSS |
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DQf |
DQf |
||||||||||||||||||||
G |
DQc |
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DQc |
VDDQ |
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VDDQ |
VDD |
EP2 |
VDD |
VDDQ |
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VDDQ |
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DQf |
DQf |
||||||||||||||||||||
H |
DQc |
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DQc |
VSS |
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VSS |
VSS |
EP3 |
VSS |
VSS |
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VSS |
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DQf |
DQf |
||||||||||||||||||||
J |
DQc |
DQc |
VDDQ |
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VDDQ |
VDD |
MCH |
VDD |
VDDQ |
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VDDQ |
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DQf |
DQf |
|||||||||||||||||||||
K |
CQ2 |
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CK |
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NC |
VSS |
MCL |
VSS |
NC |
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NC |
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CQ1 |
||||||||||||||||||
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CQ2 |
CQ1 |
|||||||||||||||||||||||||||||||||
L |
DQh |
DQh |
VDDQ |
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VDDQ |
VDD |
MCH |
VDD |
VDDQ |
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VDDQ |
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DQa |
DQa |
|||||||||||||||||||||
M |
DQh |
DQh |
VSS |
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VSS |
VSS |
MCL |
VSS |
VSS |
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VSS |
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DQa |
DQa |
|||||||||||||||||||||
N |
DQh |
DQh |
VDDQ |
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VDDQ |
VDD |
MCH |
VDD |
VDDQ |
|
VDDQ |
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DQa |
DQa |
|||||||||||||||||||||
P |
DQh |
DQh |
VSS |
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VSS |
VSS |
MCL |
VSS |
VSS |
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VSS |
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DQa |
DQa |
|||||||||||||||||||||
R |
DQd |
DQh |
VDDQ |
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VDDI |
VDD |
VDD |
VDD |
VDDI |
|
VDDQ |
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DQa |
DQe |
|||||||||||||||||||||
T |
DQd |
DQd |
VSS |
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NC |
NC |
MCL |
NC |
NC |
|
VSS |
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DQe |
DQe |
|||||||||||||||||||||
U |
DQd |
DQd |
NC |
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A |
NC |
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A |
NC |
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A |
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NC |
DQe |
DQe |
|||||||||||||||||
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(72M) |
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(36M) |
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V |
DQd |
DQd |
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A |
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A |
A |
A1 |
A |
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A |
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A |
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DQe |
DQe |
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W |
DQd |
DQd |
TMS |
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TDI |
A |
A0 |
A |
TDO |
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TCK |
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DQe |
DQe |
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||||||||||
• 2001.03 |
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11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch |
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|
Rev: 1.00d 6/2002 |
2/36 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DW18/36/72C-333/300/250
8170DW36C 512K x 36 Pinout
512K x 36 Common I/O—Top View
|
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1 |
2 |
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3 |
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4 |
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5 |
6 |
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7 |
8 |
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9 |
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10 |
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11 |
|||||||||
A |
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NC |
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NC |
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A |
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E2 |
A |
ADV |
A |
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E3 |
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A |
DQb |
DQb |
|||||||||||||
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|||||||
B |
NC |
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NC |
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NC |
A |
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A |
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NC |
DQb |
DQb |
||||||||
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Bc |
W |
Bb |
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|||||||||
C |
NC |
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NC |
NC |
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NC |
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NC |
NC |
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DQb |
DQb |
||||||||
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Bd |
E1 |
Ba |
||||||||||||||||||||||||||
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(144M) |
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|||||||||||||||
D |
NC |
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NC |
VSS |
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NC |
NC |
MCL |
NC |
NC |
|
VSS |
DQb |
DQb |
||||||||||||||||
E |
NC |
|
DQc |
VDDQ |
|
VDDI |
VDD |
VDD |
VDD |
VDDI |
|
VDDQ |
|
NC |
DQb |
|||||||||||||||
F |
DQc |
|
DQc |
VSS |
|
VSS |
VSS |
ZQ |
VSS |
VSS |
|
VSS |
|
NC |
NC |
|||||||||||||||
G |
DQc |
|
DQc |
VDDQ |
|
VDDQ |
VDD |
EP2 |
VDD |
VDDQ |
|
VDDQ |
|
NC |
NC |
|||||||||||||||
H |
DQc |
|
DQc |
VSS |
|
VSS |
VSS |
EP3 |
VSS |
VSS |
|
VSS |
|
NC |
NC |
|||||||||||||||
J |
DQc |
|
DQc |
VDDQ |
|
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
|
VDDQ |
|
NC |
NC |
|||||||||||||||
K |
CQ2 |
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CK |
|
NC |
VSS |
MCL |
VSS |
NC |
|
NC |
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|
CQ1 |
|||||||||||||
|
CQ2 |
CQ1 |
||||||||||||||||||||||||||||
L |
NC |
|
NC |
VDDQ |
|
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
|
VDDQ |
|
DQa |
DQa |
|||||||||||||||
M |
NC |
|
NC |
VSS |
|
VSS |
VSS |
MCL |
VSS |
VSS |
|
VSS |
|
DQa |
DQa |
|||||||||||||||
N |
NC |
|
NC |
VDDQ |
|
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
|
VDDQ |
|
DQa |
DQa |
|||||||||||||||
P |
NC |
|
NC |
VSS |
|
VSS |
VSS |
MCL |
VSS |
VSS |
|
VSS |
|
DQa |
DQa |
|||||||||||||||
R |
DQd |
|
NC |
VDDQ |
|
VDDI |
VDD |
VDD |
VDD |
VDDI |
|
VDDQ |
|
DQa |
NC |
|||||||||||||||
T |
DQd |
DQd |
VSS |
|
NC |
NC |
MCL |
NC |
NC |
|
VSS |
|
NC |
NC |
||||||||||||||||
U |
DQd |
DQd |
NC |
|
|
A |
NC (72M) |
|
|
A |
NC (36M) |
|
A |
|
NC |
|
NC |
NC |
||||||||||||
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|||||||||||
V |
DQd |
DQd |
|
A |
|
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A |
A |
A1 |
A |
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A |
|
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A |
|
NC |
NC |
||||||||||||
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|
|
|
|
|
|
|||||||||||||||
W |
DQd |
DQd |
TMS |
|
TDI |
A |
A0 |
A |
TDO |
|
TCK |
|
NC |
NC |
||||||||||||||||
|
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|
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|
|
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|
|
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|
||||||||
• 2001.03 |
|
|
|
|
|
|
|
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch |
|
|
|
|
|
|
|
Rev: 1.00d 6/2002 |
3/36 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DW18/36/72C-333/300/250
8170DW18 1M x 18 Pinout
1M x 18 Common I/O—Top View
|
|
1 |
2 |
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3 |
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4 |
5 |
6 |
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7 |
8 |
|
9 |
|
10 |
11 |
||||||||
A |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
NC |
|
NC |
|
A |
|
E2 |
A |
ADV |
A |
E3 |
|
|
A |
|
NC |
|
NC |
|||||||||
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|
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|
|
|
|
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|||
B |
NC |
|
NC |
|
|
|
|
NC |
A |
|
|
|
|
|
A |
NC |
|
NC |
|
NC |
|
NC |
||||
Bb |
W |
|||||||||||||||||||||||||
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|||||
C |
NC |
|
NC |
NC |
|
NC |
NC |
|
|
|
|
|
A |
NC |
|
|
|
|
|
NC |
|
NC |
||||
E1 |
Ba |
|||||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
(144M) |
|
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|||||||||
D |
NC |
|
NC |
VSS |
|
NC |
NC |
MCL |
NC |
NC |
|
VSS |
|
NC |
|
NC |
||||||||||
E |
NC |
DQb |
VDDQ |
|
VDDI |
VDD |
VDD |
VDD |
VDDI |
|
VDDQ |
|
NC |
|
NC |
|||||||||||
F |
DQb |
DQb |
VSS |
|
VSS |
VSS |
ZQ |
VSS |
VSS |
|
VSS |
|
NC |
|
NC |
|||||||||||
G |
DQb |
DQb |
VDDQ |
|
VDDQ |
VDD |
EP2 |
VDD |
VDDQ |
|
VDDQ |
|
NC |
|
NC |
|||||||||||
H |
DQb |
DQb |
VSS |
|
VSS |
VSS |
EP3 |
VSS |
VSS |
|
VSS |
|
NC |
|
NC |
|||||||||||
J |
DQb |
DQb |
VDDQ |
|
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
|
VDDQ |
|
NC |
|
NC |
|||||||||||
K |
CQ2 |
|
|
|
CK |
|
NC |
VSS |
MCL |
VSS |
NC |
|
NC |
|
|
|
CQ1 |
|||||||||
|
CQ2 |
CQ1 |
||||||||||||||||||||||||
L |
NC |
|
NC |
VDDQ |
|
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
|
VDDQ |
|
DQa |
|
DQa |
||||||||||
M |
NC |
|
NC |
VSS |
|
VSS |
VSS |
MCL |
VSS |
VSS |
|
VSS |
|
DQa |
|
DQa |
||||||||||
N |
NC |
|
NC |
VDDQ |
|
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
|
VDDQ |
|
DQa |
|
DQa |
||||||||||
P |
NC |
|
NC |
VSS |
|
VSS |
VSS |
MCL |
VSS |
VSS |
|
VSS |
|
DQa |
|
DQa |
||||||||||
R |
NC |
|
NC |
VDDQ |
|
VDDI |
VDD |
VDD |
VDD |
VDDI |
|
VDDQ |
|
DQa |
|
NC |
||||||||||
T |
NC |
|
NC |
VSS |
|
NC |
NC |
MCL |
NC |
NC |
|
VSS |
|
NC |
|
NC |
||||||||||
U |
NC |
|
NC |
NC |
|
A |
NC |
|
|
A |
NC |
A |
|
NC |
|
NC |
|
NC |
||||||||
|
|
|
|
|
|
|
|
|
|
|
(72M) |
|
|
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|
|
(36M) |
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
V |
NC |
|
NC |
|
A |
|
A |
A |
A1 |
A |
A |
|
|
A |
|
NC |
|
NC |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
W |
NC |
|
NC |
TMS |
|
TDI |
A |
A0 |
A |
TDO |
|
TCK |
|
NC |
|
NC |
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
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• 2001.03 |
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11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch |
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Rev: 1.00d 6/2002 |
4/36 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DW18/36/72C-333/300/250
Pin Description Table
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Pin Location |
Symbol |
Description |
Type |
Comments |
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A3, A5, A7, A9, B7, U4, |
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U6, U8, V3, V4, V5, V6, |
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A |
Address |
Input |
— |
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V7, V8, V9, W5, W6, W7 |
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C7 |
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A |
Address |
Input |
x18 version only |
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B5 |
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A |
Address |
Input |
x18 and x36 versions |
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A6 |
ADV |
Advance |
Input |
Active High |
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B3, C9 |
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Byte Write Enable |
Input |
Active Low (all versions) |
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Bx |
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B8, C4 |
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Byte Write Enable |
Input |
Active Low (x36 and x72 versions) |
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Bx |
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B4, B9, C3, C8 |
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Byte Write Enable |
Input |
Active Low (x72 version only) |
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Bx |
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K3 |
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CK |
Clock |
Input |
Active High |
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K1, K11 |
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CQ |
Echo Clock |
Output |
Active High |
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K2, K10 |
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Echo Clock |
Output |
Active Low |
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CQ |
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E2, F1, F2, G1, G2, H1, |
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H2, J1, J2, L10, L11, |
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DQ |
Data I/O |
Input/Output |
x18, x36, and x72 versions |
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M10, M11, N10, N11, |
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P10, P11, R10 |
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A10, A11, B10, B11, |
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C10, C11, D10, D11, |
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DQ |
Data I/O |
Input/Output |
x36 and x72 versions |
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E11, R1, T1, T2, U1, U2, |
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V1, V2, W1, W2 |
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A1, A2, B1, B2, C1, C2, |
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D1, D2, E1, E10, F10, |
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F11, G10, G11, H10, |
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H11, J10, J11, L1, L2, |
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DQ |
Data I/O |
Input/Output |
x72 version only |
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M1, M2, N1, N2, P1, P2, |
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R2, R11, T10, T11, U10, |
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U11, V10, V11, W10, |
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W11 |
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C6 |
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Chip Enable |
Input |
Active Low |
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E1 |
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A4, A8 |
E2 & E3 |
Chip Enable |
Input |
Programmable Active High or Low |
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G6, H6 |
EP2 & EP3 |
Chip Enable Program Pin |
Input |
— |
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W9 |
TCK |
Test Clock |
Input |
Active High |
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W4 |
TDI |
Test Data In |
Input |
— |
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W8 |
TDO |
Test Data Out |
Output |
— |
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W3 |
TMS |
Test Mode Select |
Input |
— |
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J6, L6, N6 |
MCH |
Must Connect High |
Input |
Active High |
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D6, K6, M6, P6, T6 |
MCL |
Must Connect Low |
Input |
Active Low |
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Rev: 1.00d 6/2002 |
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5/36 |
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© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DW18/36/72C-333/300/250
Pin Description Table
Pin Location |
Symbol |
Description |
Type |
Comments |
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C5, D4, D5, D7, D8,K4, |
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K8, K9, T4, T5, T7, T8, |
NC |
No Connect |
— |
Not connected to die (all versions) |
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U3, U5, U7, U9 |
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B5 |
NC |
No Connect |
— |
Not connected to die (x72 version) |
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C7 |
NC |
No Connect |
— |
Not connected to die (x72/x36 versions) |
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A1, A2, B1, B2, B4, B9, |
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C1, C2, C3, C8, D1, D2, |
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E1, E10, F10, F11, G10, |
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G11, H10, H11, J10, J11, |
NC |
No Connect |
— |
Not connected to die (x36/x18 versions) |
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L1, L2, M1, M2, N1, N2, |
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P1, P2, R2, R11, T10, |
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T11, U10, U11, V10, |
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V11, W10, W11 |
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A10, A11, B8, B10, B11, |
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C4, C10, C11, D10, D11, |
NC |
No Connect |
— |
Not connected to die (x18 version) |
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E11, R1, T1, T2, U1, U2, |
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V1, V2, W1, W2 |
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B6 |
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Write |
Input |
Active Low |
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W |
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E5, E6, E7, G5, G7, J5, |
VDD |
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J7, L5, L7, N5, N7, R5, |
Core Power Supply |
Input |
1.8 V Nominal |
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R6, R7 |
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E3, E9, J3, J4, J8, J9, |
VDDQ |
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L3, L4, L8, L9, N3, N4, |
Output Driver Power Supply |
Input |
1.8 V or 1.5 V Nominal |
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N8, N9, R3, R9 |
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E4, E8, R4, R8 |
VDDI |
Input Buffer Power Supply |
Input |
1.8 V or 1.5 V Nominal |
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D3, D9, F3, F4, F5, F7, |
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F8, F9, H3, H4, H5, H7, |
VSS |
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H8, H9, K5, K7, M3, M4, |
Ground |
Input |
— |
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M5, M7, M8, M9, P3, P4, |
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P5, P7, P8, P9, T3, T9 |
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F6 |
ZQ |
Output Impedance Control |
Input |
Low = Low Impedance [High Drive] |
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High = High Impedance [Low Drive] |
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Rev: 1.00d 6/2002 |
6/36 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DW18/36/72C-333/300/250
Background
The central characteristics of Σ RAMs are that they are extremely fast and consume very little power. Because both operating and interface power is low, Σ RAMs can be implemented in a wide (x72) configuration, providing very high single package bandwidth (in excess of 20 Gb/s in ordinary pipelined configuration) and very low random access latency (5 ns). The use of very low voltage circuits in the core and 1.8 V or 1.5 V interface voltages allow the speed, power and density performance of Σ RAMs.
The Σ RAM family of pinouts has been designed to support a number of different common read and write protocols. The following timing diagrams provide a quick comparison between single data rate read and write protocols options available in the context of the Σ RAM standard. This particular datasheet covers the single data rate (non-DDR), Double Late Write (DW) Σ RAM.
Rev: 1.00d 6/2002 |
7/36 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DW18/36/72C-333/300/250
Common I/O SigmaRAM Family Mode Comparison—EW vs. LW vs. DLW
Σ 1x1Ef (Early Write - Flow Through Read)
CK |
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Address |
A |
B |
C |
D |
E |
F |
Control |
R |
X |
W |
R |
X |
W |
DQ |
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QA |
DC |
QD |
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DF |
Σ 1x1Lf (Late Write - Flow Through Read)
CK |
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Address |
A |
B |
C |
D |
E |
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F |
Control |
R |
W |
R |
W |
R |
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W |
DQ |
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QA |
DB |
QC |
DD |
QE |
DF |
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Σ 1x1Ep (Early Write - Pipelined Read)
CK |
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Address |
A |
B |
C |
D |
E |
F |
Control |
R |
X |
X |
W |
R |
R |
DQ |
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QA |
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DD |
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QE |
CQ
Σ 1x1Lp (Late Write - Pipelined Read)
CK |
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Address |
A |
B |
C |
D |
E |
F |
Control |
R |
Z |
W |
R |
X |
W |
QA |
DC |
QD |
DF |
CQ |
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Σ 1x1Dp (Double Late Write - Pipelined Read)
CK |
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Address |
A |
B |
C |
D |
E |
F |
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Control |
R |
W |
R |
W |
R |
W |
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QA |
QC |
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DD |
QE |
CQ |
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Note: R = Read, W = Write, Z = Deselect
Rev: 1.00d 6/2002 |
8/36 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DW18/36/72C-333/300/250
The character of the applications for fast synchronous SRAMs in networking systems are extremely diverse. Σ RAMs have been developed to address the broad variety of applications in the networking market in a manner that can be supported with a unified development and manufacturing infrastructure. Σ RAMs address each of the bus protocol options commonly found in networking systems. This allows the Σ RAM to find application in radical shrinks and speed-ups of existing networking chip sets that were designed for use with older SRAMs, like the NBT, Late Write, or Double Data Rate SRAMs, as well as with new chip sets and ASICs that employ the Echo Clocks and realize the full potential of the Σ RAMs.
Mode Selection Truth Table Standard
L6 |
M6 |
J6 |
Name |
Function |
Analogous to... |
In This Data Sheet? |
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0 |
0 |
0 |
Σ 1x1Ef |
Early Write, Flow through Read |
Flow through Burst RAM |
No |
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0 |
0 |
1 |
Σ 1x1Lf |
Late Write, Flow through Read |
Flow through NBT SRAM |
No |
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0 |
1 |
0 |
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RFU |
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n/a |
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0 |
1 |
1 |
Σ 1x2Lp |
DDR |
Double Data Rate SRAM |
No |
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1 |
0 |
0 |
Σ 1x1Ep |
Early Write, Pipeline Read |
Pipelined Burst RAM |
No |
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1 |
0 |
1 |
Σ 1x1Dp |
Double Late Write, Pipeline Read |
Pipelined NBT SRAM |
Yes |
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1 |
1 |
0 |
Σ 1x1Lp |
Late Write, Pipeline Read |
Pipelined Late Write SRAM |
No |
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1 |
1 |
1 |
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RFU |
— |
n/a |
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All address, data and control inputs (with the exception of PE2, PE3, ZQ, and the mode pins, L6, M6, J6) are synchronized to rising clock edges. Read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted that ONLY deactivation of the RAM via E2 and/or
E3 deactivates the Echo Clocks, CQ1–CQ2.
Rev: 1.00d 6/2002 |
9/36 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DW18/36/72C-333/300/250
Read Operations
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Single Data Rate Pipelined Read
|
Read |
Deselect |
Read |
Read |
Read |
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CK |
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Address |
A |
XX |
C |
D |
E |
F |
ADV |
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/E1 |
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/W |
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DQ |
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QA |
QC |
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QD |
CQ |
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Key |
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Hi-Z |
Access |
|
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Rev: 1.00d 6/2002 |
10/36 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DW18/36/72C-333/300/250
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Double Late Write
Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement Pipeline mode NBT SRAMs.
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SigmaRAM Double Late Write with Pipelined Read |
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Read |
Write |
Read |
Write |
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Read |
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CK |
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Address |
A |
B |
C |
D |
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E |
F |
ADV |
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/E1 |
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/W |
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DQ |
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QA |
DB |
QC |
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DD |
CQ |
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Key |
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Hi-Z |
Access |
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Rev: 1.00d 6/2002 |
11/36 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.