GSI GS882Z36B-66, GS882Z36B-11I, GS882Z36B-11, GS882Z36B-100I, GS882Z36B-100 Datasheet

Preliminary

GS882Z18/36B-11/100/80/66

119-Bump BGA

8Mb Pipelined and Flow Through

Commercial Temp
Industrial Temp

Synchronous NBT SRAMs

Features

• 512K x 18 and 256K x 36 configurations

• User-configurable Pipelined and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

• Read-Write-Read bus utilization

• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• ZQ mode pin for user selectable high/low output drive
strength.

• x16/x32 mode with on-chip parity encoding and error
detection

• Pin-compatible with 2M, 4M and 16M devices

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• Clock Control, registered, address, data, and control

• ZZ Pin for automatic power-down

• JEDEC-standard 119-Bump BGA package

-11 -100 -80 -66

t
Pipeline
3-1-1-1

Flow Through
2-1-1-1

Cycle

t

KQ

I

DD

t

KQ

t

Cycle

I

DD

10 ns

4.5 ns

210 mA

11 ns
15 ns

150 mA

10 ns

4.5 ns

210 mA

12 ns
15 ns

150 mA

12.5 ns

4.8 ns

190 mA

14 ns
15 ns

130 mA

15 ns

5 ns

170 mA

18 ns
20 ns

130 mA

100 MHz–66 MHz

3.3 V V

2.5 V and 3.3 V V

DD

DDQ

Functional Description

The GS882Z818/36B is an 8Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off­chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.

The GS882Z818/36B may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge­triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.

The GS882Z818/36B is implemented with GSI's high
performance CMOS technology and is available in a JEDEC­Standard 119-bump BGA package.

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

Clock

Address

Read/Write

Flow Through

Data I/O

Pipelined

Data I/O

A B C D E F

R W R W R W

Q

A

D

B

Q

A

Q

C

D

B

D

D

Q

C

Q

E

D

D

Q

E

Rev: 1.15 6/2001 1/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

GS882Z36 Pad Out

Preliminary.

GS882Z18/36B-11/100/80/66

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

B

C

D

E

F

G

H

J

K

L

V

DDQ

NC E2 A4 ADV A15 E3 NC

NC A5 A3 V

DQC4 DQPC9 V

DQC3 DQC8 V

V

DDQ

DQC2 DQC6 BC A17 BB DQB6 DQB2

DQC1 DQC5 V

V

DDQ

DQD1 DQD5 V

DQD2 DQD6 BD NC BA DQA6 DQA2

A6 A7 NC A8 A9 V

A14 A16 NC

DQPB9 DQB4

SS

DQB8 DQB3

SS

DQB7 V

SS

DQB5 DQB1

SS

QE V

SS

DD

DQA5 DQA1

DQC7 V

V

DD

SS

SS

SS

SS

DP V

SS

DD

ZQ V

E1 V

G V

W V

DD

CK V

V

DDQ

DDQ

DDQ

M

N

P

R

T

U

V

DDQ

DQD3 DQD8 V

DQD4 DQPD9 V

NC A2 LBO V

NC NC A10 A11 A12 NC ZZ

V

DDQ

DQD7 V

SS

SS

SS

CKE V

A1 V

A0 V

DD

DQA7 V

SS

DQA8 DQA3

SS

DQPA9 DQA4

SS

FT A13 PE

TMS TDI TCK TDO NC V

DDQ

DDQ

Rev: 1.15 6/2001 2/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS882Z18 Pad Out

Preliminary.

GS882Z18/36B-11/100/80/66

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

B

C

D

E

F

G

H

J

K

L

V

DDQ

NC E2 A4 ADV A15 E3 NC

NC A5 A3 V

DQB1 NC V

NC DQB2 V

V

DDQ

NC DQB3 BB A17 NC NC DQA6

DQB4 NC V

V

DDQ

NC DQB5 V

DQB6 NC NC NC BA DQA3 NC

A6 A7 NC A8 A9 V

A14 A16 NC

DQA9 NC

SS

SS

SS

SS

QE V

SS

NC DQA8

DQA7 V

DQA5 NC

DD

NC DQA4

NC V

V

DD

SS

SS

SS

SS

DP V

SS

DD

ZQ V

E1 V

G V

W V

DD

CK V

V

DDQ

DDQ

DDQ

M

N

P

R

T

U

V

DDQ

DQB8 NC V

NC DQB9 V

NC A2 LBO V

NC A10 A11 NC A12 A18 ZZ

V

DDQ

DQB7 V

SS

SS

SS

CKE V

A1 V

A0 V

DD

SS

SS

SS

NC V

DDQ

DQA2 NC

NC DQA1

FT A13 PE

NC V

DDQ

Rev: 1.15 6/2001 3/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS882Z18/36 BGA Pin Description

Pin Location Symbol Type Description

P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs

A2, A3, A5, A6, B3, B5, C2, C3, C5,

C6, G4, R2, R6, T3, T5

T4 An I Address Inputs (x36 Version)
T2, T6 NC — No Connect (x36 Version)
T2, T6 An I Address Inputs (x18 Version)

K7, L7, N7, P7, K6, L6, M6, N6, P6
H7, G7, E7, D7, H6, G6, F6, E6, D6
H1, G1, E1, D1, H2, G2, F2, E2, D2

K1, L1, N1, P1, K2, L2, M2, N2, P2

L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version)

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2

L5, G3 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version)

P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,

G5, L3, T4

K4 CK I Clock Input Signal; active high

M4 CKE I Clock Input Buffer Enable; active low
H4 W I Write Enable—Writes all enabled bytes; active low

E4 E1 I Chip Enable; active low

B2 E2 I Chip Enable; active high

B6 E3 I Chip Enable; active low

F4 G I Output Enable; active low

B4 ADV I Burst address counter advance enable; active high

T7 ZZ I Sleep Mode control; active high

R5 FT I Flow Through or Pipeline mode; active low
R3 LBO I Linear Burst Order mode; active low
R7 PE I Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)

J3 DP I Data Parity Mode Input; 1 = Even, 0 = Odd

J5 QE O Parity Error Out; Open Drain Output

D4 ZQ I

B1, C1, R1, T1, L4, B7, C7, U6 NC — No Connect

An I Address Inputs

DQA1–DQPA9
DQB1–DQPB9
DQC1–DQPC9
DQD1–DQPD9

DQA1–DQA9
DQB1–DQB9

NC — No Connect (x18 Version)

I/O Data Input and Output pins (x36 Version)

I/O Data Input and Output pins (x18 Version)

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

Preliminary.

GS882Z18/36B-11/100/80/66

Rev: 1.15 6/2001 4/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

GS882Z18/36 BGA Pin Description

Pin Location Symbol Type Description

U2 TMS I Scan Test Mode Select
U3 TDI I Scan Test Data In
U5 TDO O Scan Test Data Out
U4 TCK I Scan Test Clock

V

V

V

DDQ

DD

SS

I Core power supply

I I/O and Core Ground

I Output driver power supply

BPR2000.002.14

J2, C4, J4, R4, J6

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.

Function W BA BB BC BD

Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H

Write Byte “c” L H H L H

Write Byte “d” L H H H L

Write all Bytes L L L L L

Write Abort/NOP L H H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.

Write operation occurs when the RAM is selected, CKE is active and the Write input is sampled low at the rising edge of clock.

Rev: 1.15 6/2001 5/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A Write
Cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.

Rev: 1.15 6/2001 6/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

Synchronous Truth Table

Operation Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes

Deselect Cycle, Power Down D None H X X L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z
Deselect Cycle, Continue D None X X X L H X X X L L-H High-Z 1
Read Cycle, Begin Burst R External L H L L L H X L L L-H Q
Read Cycle, Continue Burst B Next X X X L H X X L L L-H Q 1,10
NOP/Read, Begin Burst R External L H L L L H X H L L-H High-Z 2
Dummy Read, Continue Burst B Next X X X L H X X H L L-H High-Z 1,2,10
Write Cycle, Begin Burst W External L H L L L L L X L L-H D 3
Write Cycle, Continue Burst B Next X X X L H X L X L L-H D 1,3,10
NOP/Write Abort, Begin Burst W None L H L L L L H X L L-H High-Z 2,3
Write Abort, Continue Burst B Next X X X L H X H X L L-H High-Z 1,2,3,10
Clock Edge Ignore, Stall Current X X X L X X X X H L-H - 4
Sleep Mode None X X X H X X X X X X High-Z
Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect
cycle is executed first

2. Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is
sampled low but no Byte Write pins are active, so no Write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write
cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Rev: 1.15 6/2001 7/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Pipeline and Flow Through Read-Write Control State Diagram

Preliminary.

GS882Z18/36B-11/100/80/66

D

B

Deselect

R

D

W

New Read New Write

R

B

R

W

W

R

R

Burst Read Burst Write

B

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

Next State (n+1)

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B and D represent input command

codes, as indicated in the Synchronous Truth Table.

D

W

B

W

B

DD

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒ ƒ ƒ

Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram

Rev: 1.15 6/2001 8/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

Pipeline Mode Data I/O State Diagram

Intermediate Intermediate

Key

ƒ

Transition

Current State (n) Next State (n+2)

W

B

High Z
(Data In)

Input Command Code

Intermediate State (N+1)

D

R

Intermediate

Transition

Intermediate

W

High Z

B

D

Intermediate

R

B

Data Out

W

(Q Valid)

Intermediate

R

Notes

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.

D

n n+1 n+2 n+3

Clock (CK)

Command

Current State

ƒ

ƒ ƒ ƒ

Intermediate

State

Next State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.15 6/2001 9/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Flow Through Mode Data I/O State Diagram

Preliminary.

GS882Z18/36B-11/100/80/66

W

B

High Z
(Data In)

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

R

D

Next State (n+1)

W

R

High Z

B

D

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

R

B

Data Out

W

(Q Valid)

D

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒ ƒ ƒ

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Rev: 1.15 6/2001 10/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.

FLXDrive™

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

ByteSafe Data Parity Control DP

Parity Enable PE

FLXDrive Output Impedance Control ZQ

Note:
There are pull-up devices on the LBO, ZQ, DP and FT pins and a pull down device on the PE and ZZ pins, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above table.

L Linear Burst

H or NC Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

L Check for Odd Parity

H or NC Check for Even Parity

L or NC Activate 9th I/Os (x18/36 Mode)

H Deactivate 9th I/Os (x16/32 Mode)

L High Drive (Low Impedance)

H Low Drive (High Impedance)

Standby, IDD = I

SB

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or
x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.

Rev: 1.15 6/2001 11/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com