GSI GS882Z36B-66, GS882Z36B-11I, GS882Z36B-11, GS882Z36B-100I, GS882Z36B-100 Datasheet

Preliminary

GS882Z18/36B-11/100/80/66

119-Bump BGA

8Mb Pipelined and Flow Through

Commercial Temp
Industrial Temp

Synchronous NBT SRAMs

Features

• 512K x 18 and 256K x 36 configurations

• User-configurable Pipelined and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

• Read-Write-Read bus utilization

• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• ZQ mode pin for user selectable high/low output drive
strength.

• x16/x32 mode with on-chip parity encoding and error
detection

• Pin-compatible with 2M, 4M and 16M devices

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• Clock Control, registered, address, data, and control

• ZZ Pin for automatic power-down

• JEDEC-standard 119-Bump BGA package

-11 -100 -80 -66

t
Pipeline
3-1-1-1

Flow Through
2-1-1-1

Cycle

t

KQ

I

DD

t

KQ

t

Cycle

I

DD

10 ns

4.5 ns

210 mA

11 ns
15 ns

150 mA

10 ns

4.5 ns

210 mA

12 ns
15 ns

150 mA

12.5 ns

4.8 ns

190 mA

14 ns
15 ns

130 mA

15 ns

5 ns

170 mA

18 ns
20 ns

130 mA

100 MHz–66 MHz

3.3 V V

2.5 V and 3.3 V V

DD

DDQ

Functional Description

The GS882Z818/36B is an 8Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off­chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.

The GS882Z818/36B may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge­triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.

The GS882Z818/36B is implemented with GSI's high
performance CMOS technology and is available in a JEDEC­Standard 119-bump BGA package.

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

Clock

Address

Read/Write

Flow Through

Data I/O

Pipelined

Data I/O

A B C D E F

R W R W R W

Q

A

D

B

Q

A

Q

C

D

B

D

D

Q

C

Q

E

D

D

Q

E

Rev: 1.15 6/2001 1/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

GS882Z36 Pad Out

Preliminary.

GS882Z18/36B-11/100/80/66

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

B

C

D

E

F

G

H

J

K

L

V

DDQ

NC E2 A4 ADV A15 E3 NC

NC A5 A3 V

DQC4 DQPC9 V

DQC3 DQC8 V

V

DDQ

DQC2 DQC6 BC A17 BB DQB6 DQB2

DQC1 DQC5 V

V

DDQ

DQD1 DQD5 V

DQD2 DQD6 BD NC BA DQA6 DQA2

A6 A7 NC A8 A9 V

A14 A16 NC

DQPB9 DQB4

SS

DQB8 DQB3

SS

DQB7 V

SS

DQB5 DQB1

SS

QE V

SS

DD

DQA5 DQA1

DQC7 V

V

DD

SS

SS

SS

SS

DP V

SS

DD

ZQ V

E1 V

G V

W V

DD

CK V

V

DDQ

DDQ

DDQ

M

N

P

R

T

U

V

DDQ

DQD3 DQD8 V

DQD4 DQPD9 V

NC A2 LBO V

NC NC A10 A11 A12 NC ZZ

V

DDQ

DQD7 V

SS

SS

SS

CKE V

A1 V

A0 V

DD

DQA7 V

SS

DQA8 DQA3

SS

DQPA9 DQA4

SS

FT A13 PE

TMS TDI TCK TDO NC V

DDQ

DDQ

Rev: 1.15 6/2001 2/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS882Z18 Pad Out

Preliminary.

GS882Z18/36B-11/100/80/66

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

B

C

D

E

F

G

H

J

K

L

V

DDQ

NC E2 A4 ADV A15 E3 NC

NC A5 A3 V

DQB1 NC V

NC DQB2 V

V

DDQ

NC DQB3 BB A17 NC NC DQA6

DQB4 NC V

V

DDQ

NC DQB5 V

DQB6 NC NC NC BA DQA3 NC

A6 A7 NC A8 A9 V

A14 A16 NC

DQA9 NC

SS

SS

SS

SS

QE V

SS

NC DQA8

DQA7 V

DQA5 NC

DD

NC DQA4

NC V

V

DD

SS

SS

SS

SS

DP V

SS

DD

ZQ V

E1 V

G V

W V

DD

CK V

V

DDQ

DDQ

DDQ

M

N

P

R

T

U

V

DDQ

DQB8 NC V

NC DQB9 V

NC A2 LBO V

NC A10 A11 NC A12 A18 ZZ

V

DDQ

DQB7 V

SS

SS

SS

CKE V

A1 V

A0 V

DD

SS

SS

SS

NC V

DDQ

DQA2 NC

NC DQA1

FT A13 PE

NC V

DDQ

Rev: 1.15 6/2001 3/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS882Z18/36 BGA Pin Description

Pin Location Symbol Type Description

P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs

A2, A3, A5, A6, B3, B5, C2, C3, C5,

C6, G4, R2, R6, T3, T5

T4 An I Address Inputs (x36 Version)
T2, T6 NC — No Connect (x36 Version)
T2, T6 An I Address Inputs (x18 Version)

K7, L7, N7, P7, K6, L6, M6, N6, P6
H7, G7, E7, D7, H6, G6, F6, E6, D6
H1, G1, E1, D1, H2, G2, F2, E2, D2

K1, L1, N1, P1, K2, L2, M2, N2, P2

L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version)

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2

L5, G3 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version)

P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,

G5, L3, T4

K4 CK I Clock Input Signal; active high

M4 CKE I Clock Input Buffer Enable; active low
H4 W I Write Enable—Writes all enabled bytes; active low

E4 E1 I Chip Enable; active low

B2 E2 I Chip Enable; active high

B6 E3 I Chip Enable; active low

F4 G I Output Enable; active low

B4 ADV I Burst address counter advance enable; active high

T7 ZZ I Sleep Mode control; active high

R5 FT I Flow Through or Pipeline mode; active low
R3 LBO I Linear Burst Order mode; active low
R7 PE I Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)

J3 DP I Data Parity Mode Input; 1 = Even, 0 = Odd

J5 QE O Parity Error Out; Open Drain Output

D4 ZQ I

B1, C1, R1, T1, L4, B7, C7, U6 NC — No Connect

An I Address Inputs

DQA1–DQPA9
DQB1–DQPB9
DQC1–DQPC9
DQD1–DQPD9

DQA1–DQA9
DQB1–DQB9

NC — No Connect (x18 Version)

I/O Data Input and Output pins (x36 Version)

I/O Data Input and Output pins (x18 Version)

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

Preliminary.

GS882Z18/36B-11/100/80/66

Rev: 1.15 6/2001 4/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

GS882Z18/36 BGA Pin Description

Pin Location Symbol Type Description

U2 TMS I Scan Test Mode Select
U3 TDI I Scan Test Data In
U5 TDO O Scan Test Data Out
U4 TCK I Scan Test Clock

V

V

V

DDQ

DD

SS

I Core power supply

I I/O and Core Ground

I Output driver power supply

BPR2000.002.14

J2, C4, J4, R4, J6

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.

Function W BA BB BC BD

Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H

Write Byte “c” L H H L H

Write Byte “d” L H H H L

Write all Bytes L L L L L

Write Abort/NOP L H H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.

Write operation occurs when the RAM is selected, CKE is active and the Write input is sampled low at the rising edge of clock.

Rev: 1.15 6/2001 5/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A Write
Cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.

Rev: 1.15 6/2001 6/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

Synchronous Truth Table

Operation Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes

Deselect Cycle, Power Down D None H X X L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z
Deselect Cycle, Continue D None X X X L H X X X L L-H High-Z 1
Read Cycle, Begin Burst R External L H L L L H X L L L-H Q
Read Cycle, Continue Burst B Next X X X L H X X L L L-H Q 1,10
NOP/Read, Begin Burst R External L H L L L H X H L L-H High-Z 2
Dummy Read, Continue Burst B Next X X X L H X X H L L-H High-Z 1,2,10
Write Cycle, Begin Burst W External L H L L L L L X L L-H D 3
Write Cycle, Continue Burst B Next X X X L H X L X L L-H D 1,3,10
NOP/Write Abort, Begin Burst W None L H L L L L H X L L-H High-Z 2,3
Write Abort, Continue Burst B Next X X X L H X H X L L-H High-Z 1,2,3,10
Clock Edge Ignore, Stall Current X X X L X X X X H L-H - 4
Sleep Mode None X X X H X X X X X X High-Z
Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect
cycle is executed first

2. Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is
sampled low but no Byte Write pins are active, so no Write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write
cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Rev: 1.15 6/2001 7/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Pipeline and Flow Through Read-Write Control State Diagram

Preliminary.

GS882Z18/36B-11/100/80/66

D

B

Deselect

R

D

W

New Read New Write

R

B

R

W

W

R

R

Burst Read Burst Write

B

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

Next State (n+1)

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B and D represent input command

codes, as indicated in the Synchronous Truth Table.

D

W

B

W

B

DD

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒ ƒ ƒ

Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram

Rev: 1.15 6/2001 8/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

Pipeline Mode Data I/O State Diagram

Intermediate Intermediate

Key

ƒ

Transition

Current State (n) Next State (n+2)

W

B

High Z
(Data In)

Input Command Code

Intermediate State (N+1)

D

R

Intermediate

Transition

Intermediate

W

High Z

B

D

Intermediate

R

B

Data Out

W

(Q Valid)

Intermediate

R

Notes

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.

D

n n+1 n+2 n+3

Clock (CK)

Command

Current State

ƒ

ƒ ƒ ƒ

Intermediate

State

Next State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.15 6/2001 9/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Flow Through Mode Data I/O State Diagram

Preliminary.

GS882Z18/36B-11/100/80/66

W

B

High Z
(Data In)

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

R

D

Next State (n+1)

W

R

High Z

B

D

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

R

B

Data Out

W

(Q Valid)

D

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒ ƒ ƒ

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Rev: 1.15 6/2001 10/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.

FLXDrive™

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

ByteSafe Data Parity Control DP

Parity Enable PE

FLXDrive Output Impedance Control ZQ

Note:
There are pull-up devices on the LBO, ZQ, DP and FT pins and a pull down device on the PE and ZZ pins, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above table.

L Linear Burst

H or NC Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

L Check for Odd Parity

H or NC Check for Even Parity

L or NC Activate 9th I/Os (x18/36 Mode)

H Deactivate 9th I/Os (x16/32 Mode)

L High Drive (Low Impedance)

H Low Drive (High Impedance)

Standby, IDD = I

SB

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or
x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.

Rev: 1.15 6/2001 11/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Burst Counter Sequences

Linear Burst Sequence

I

Preliminary.

GS882Z18/36B-11/100/80/66

nterleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01
4th address 11 00 01 10

Note: The burst counter wraps to initial state on the 5th clock.

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01
4th address 11 10 01 00

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

BPR 1999.05.18

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

CK

ZZ

tZZS

~

Sleep

~

~

~

tZZR

tZZH

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found
on bump 5R. Not all vendors offer this option, however most mark bump 5R as VDD or V

through parts. GSI NBT SRAMs are fully compatible with these sockets.

on pipelined parts and VSS on flow

DDQ

ByteSafe™ Parity Functions

In x32/x16 mode this RAM features a parity encoding and checking function. It is assumed that the RAM is being used in x32/x16
mode because there is no source for parity bits from the system. So, in x32/x16 mode, the device generates parity and stores it
along with written data. It is also assumed that there is no facility for parity checking, so the RAM checks read parity and reports an
error in the cycle following parity check. In x32/x16 mode the device does not drive the 9th data output, even though the internal
ByteSafe parity encoding has been activated. A ByteSafe SRAM, used in x32/x16 mode, allows parity protection of data in
applications where parity encoding or checking are not otherwise available. As in any system that checks read parity, reads of un-

Rev: 1.15 6/2001 12/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

written memory locations may well produce parity errors. Initialization of the memory should be implemented to avoid this issue.

In x18/x36 mode this SRAM includes a write data parity check that checks the validity of data coming into the RAM on write
cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write
data errors are reported one clock cycle later. (See Write Parity Error Output Timing Diagram.) The Data Parity Mode (DP) pin
must be tied high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the
RAM as data. Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low
to indicate a parity error. Multiple Parity Error Output pins may share a common pull-up resistor.

x32 Mode (PE = 1) Read Parity Error Output Timing Diagram

CK

Address A Address B Address C Address D Address E Address F

DQ

D Out A D Out B D Out C D Out D D Out E

tKQ

tLZ

tHZ

tKQX

QE

Flow Through ModePipelined Mode

DQ

Err A Err C

D Out A D Out B D Out C D Out D

tKQ

tLZ

tHZ

tKQX

QE

Err A

Err C

Rev: 1.15 6/2001 13/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

x18/x36 Mode (PE = 0) Write Parity Error Output Timing Diagram

CK

Preliminary.

GS882Z18/36B-11/100/80/66

DQ

D In A D In B D In C D In D D In E

tKQ

tLZ

tHZ

tKQX

QE

Flow Through ModePipelined Mode

DQ

D In A D In B D In C D In D D In E

Err A

tLZ

tKQ

Err C

tHZ

tKQX

QE

Err A Err C

BPR 1999.05.18

Rev: 1.15 6/2001 14/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

V

DD

V

DDQ

V

CK

V

I/O

V

IN

I

IN

I

OUT

P

D

T

STG

T

BIAS

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.

Voltage on VDD Pins

Voltage in V

Pins –0.5 to V

DDQ

–0.5 to 4.6 V

DD

V

Voltage on Clock Input Pin –0.5 to 6 V

Voltage on I/O Pins

Voltage on Other Input Pins

–0.5 to V

–0.5 to V

+0.5 (≤ 4.6 V max.)

DDQ

+0.5 (≤ 4.6 V max.)

DD

V
V

Input Current on Any Pin +/–20 mA

Output Current on Any I/O Pin +/–20 mA

Package Power Dissipation 1.5 W

Storage Temperature –55 to 125

Temperature Under Bias –55 to 125

o

o

C
C

Recommended Operating Conditions

Parameter Symbol Min. Typ. Max. Unit Notes

Supply Voltage
I/O Supply Voltage
Input High Voltage

Input Low Voltage

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ V
(i.e., 2.5 V I/O) and 3.6 V ≤ V

≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.

DDQ

2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be –2 V > Vi < V

V

DD

V

DDQ

V

IH

V

IL

T

A

T

A

+2 V with a pulse width not to exceed 20% tKC.

DD

3.135 3.3 3.6 V

2.375 2.5

1.7 —

–0.3 — 0.8 V 2

0 25 70 °C 3

–40 25 85 °C 3

V

DD

V

+0.3

DD

V 1
V 2

≤ 2.375 V

DDQ

Rev: 1.15 6/2001 15/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS882Z18/36B-11/100/80/66

Undershoot Measurement and Timing Overshoot Measurement and Timing

V

IH

VDD + 2.0 V

V

SS

50%

20% tKC

Preliminary.

50%

VSS – 2.0 V

20% tKC

V

DD

V

IL

Capacitance

(TA = 25oC, f = 1 MHZ, V

DD

= 3.3 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

Input/Output Capacitance

Note: These parameters are sample tested.

C

IN

C

I/O

V

V

IN

OUT

= 0 V

= 0 V

4 5 pF
6 7 pF

Package Thermal Characteristics

Rating Layer Board Symbol Max Unit Notes

Junction to Ambient (at 200 lfm) single
Junction to Ambient (at 200 lfm) four

Junction to Case (TOP) —

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper­ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

R
R
R

ΘJA
ΘJA

ΘJC

40 °C/W 1,2
24 °C/W 1,2

9 °C/W 3

Rev: 1.15 6/2001 16/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

Output load Fig. 1& 2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, t

4. Device is deselected as defined by the Truth Table.

DQ

and t

OLZ

Output Load 1

OHZ

Preliminary.

GS882Z18/36B-11/100/80/66

Output Load 2

2.5 V

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins)

ZZ Input Current

Mode Pin Input Current

Output Leakage Current

Output High Voltage
Output High Voltage

Output Low Voltage

I

I

INZZ

I

INM

I

V
V
V

IL

OL

OH

OH

OL

50Ω

VT = 1.25 V

I

OH

I

OH

*

30pF

* Distributed Test Jig Capacitance

V

= 0 to V

IN

V

DD ≥ VIN ≥ VIH

0 V ≤ V
V

DD ≥ VIN ≥ VIL

0 V ≤ V

IN

IN

DD

≤ V

≤ V

IH

IL

Output Disable,

V

= 0 to V

OUT

= –8 mA, V
= –8 mA, V

I

OL

DDQ

DDQ

= 8 mA

DD

= 2.375 V
= 3.135 V

DQ

5pF

–1 uA 1 uA

–1 uA
–1 uA

300 uA

–300 uA

–1 uA

–1 uA 1 uA

1.7 V —

2.4 V —
— 0.4 V

*

1 uA

1 uA
1 uA

225Ω

225Ω

Rev: 1.15 6/2001 17/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Operating Currents

Parameter Test Conditions Symbol

Device Selected;

Operating

Current

Standby

Current

Deselect

Current

All other inputs

≥ VIH or ≤ V

Output open

ZZ ≥ V

Device Deselected;

All other inputs

≥ VIH or ≤ V

DD

IL

– 0.2 V

IL

I

DD

Pipeline

I

DD

Flow-through

I

SB

Pipeline

I

SB

Flow-through

I

DD

Pipeline

I

DD

Flow-through

Preliminary.

GS882Z18/36B-11/100/80/66

-11 -100 -80 -66

0 to

-40 to

70°C

+85°C

210 220 210 220 190 200 170 180 mA

150 160 150 160 130 140 130 140 mA

30 40 30 40 30 40 30 40 mA

30 40 30 40 30 40 30 40 mA

80 90 80 90 70 80 65 75 mA

65 75 65 75 55 65 55 65 mA

0 to

70°C

-40 to

+85°C

0 to

70°C

-40 to

+85°C

0 to

70°C

-40 to

+85°C

Unit

Rev: 1.15 6/2001 18/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

AC Electrical Characteristics

Preliminary.

GS882Z18/36B-11/100/80/66

Parameter Symbol

Unit

Min Max Min Max Min Max Min Max

Clock Cycle Time tKC 10 — 10 — 12.5 — 15 — ns
Clock to Output Valid tKQ — 4.5 — 4.5 — 4.8 — 5 ns

-11 -100 -80 -66

Pipeline

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — ns
Clock to Output in Low-Z

tLZ

1

1.5 — 1.5 — 1.5 — 1.5 — ns

Clock Cycle Time tKC 15.0 — 15.0 — 15.0 — 20 — ns

Flow­through

Clock to Output Valid tKQ — 11.0 — 12.0 — 14.0 — 18.0 ns
Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

1

3.0 — 3.0 — 3.0 — 3.0 — ns

Clock HIGH Time tKH 1.7 — 2 — 2 — 2.3 — ns
Clock LOW Time tKL 2 — 2.2 — 2.2 — 2.5 — ns

Clock to Output in High-Z

tHZ

1

1.5 4.0 1.5 4.5 1.5 4.8 1.5 5 ns
G to Output Valid tOE — 4.0 — 4.5 — 4.8 — 5 ns
G to output in Low-Z

G to output in High-Z

tOLZ

tOHZ

1

1

0 — 0 — 0 — 0 — ns

— 4.0 — 4.5 — 4.8 — 5 ns

Setup time tS 1.5 — 2.0 — — 2.0 — 2.0 ns
Hold time tH 0.5 — 0.5 — — 0.5 — 0.5 ns

ZZ setup time
ZZ hold time

tZZS
tZZH

2

2

5 — 5 — 5 — 5 — ns
1 — 1 — 1 — 1 — ns

ZZ recovery tZZR 20 — 20 — 20 — 20 — ns

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup
and hold times as specified above.

Rev: 1.15 6/2001 19/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Pipeline Mode Read/Write Cycle Timing

1 2 3 4 5 6 7 8 9 10

CK

tH

CKE

E*

ADV

Bn

tS

tS

tS

tS

tS

tH

tH

tH

tH

tKHWtKL tKC

Preliminary.

GS882Z18/36B-11/100/80/66

tS

tH

A0–An

DQA–DQD

A1

A2 A3

D(A1)

tS

D(A2)

tH

G

COMMAND

Write
D(A1)

Write
D(A2)

BURST
Write
D(A2+1)

Read
Q(A3)

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

A4 A5 A6 A7

tKQLZ

(A2+1)

tKQ

D

tKQHZ

Q(A3)

Q(A4)

tGLQV

Q

(A4+1)

tOEHZ

tOELZ

Read
Q(A4)

BURST
Read
Q(A4+1)

Write
D(A5)

Read
Q(A6)

DON’T CARE UNDEFINED

tKHQZ

tKQX

Write
D(A7)

D(A5)

Q(A6)

DESELECT

Rev: 1.15 6/2001 20/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Pipeline Mode No-Op, Stall and Deselect Timing

Preliminary.

GS882Z18/36B-11/100/80/66

CK

CKE

E*

ADV

W

Bn

A0–An

1

tS

tS

tS

tS

tH

A1 A5

2

tH

tH

tH

A2 A3 A4

3

4

5 6

7

8

9

10

tKHQZ

DQ

COMMAND

Write
D(A1)

Read
Q(A2)

D(A1)

STALL Read

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

Q(A3)

Q(A2)

Write
D(A4)

Q(A3)

STALL

NOP

DON’T CARE UNDEFINED

D(A4)

Read
Q(A5)

tKQHZ

DESELECT

Q(A5)

CONTINUE
DESELECT

Rev: 1.15 6/2001 21/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Flow Through Mode Read/Write Cycle Timing

Preliminary.

GS882Z18/36B-11/100/80/66

CK

CKE

E*

ADV

Bn

A0–An

DQ

1 2

tH

tS

tH

tS

tS

tH

tS

tH

tS

tH

tS

3

tKHWtKL

tH

4

5 6

7

tKC

A1 A2 A3 A4 A5 A6

D(A1)

D(A2)

tKQLZ

(A2+1)

tKQ

tKQHZ

D

Q(A3)

tGLQV

Q(A4)

Q

(A4+1)

tKHQZ

8

D(A5)

9

A7

Q(A6)

10

tS

tH

tOEHZ

tOELZ

tKQX

G

COMMAND

Write
D(A1)

Write
D(A2)

BURST
Write
D(A2+1)

Read
Q(A3)

Read
Q(A4)

BURST
Read
Q(A4+1)

Write
D(A5)

Read
Q(A6)

DON’T CARE

DESELECT

Write
D(A7)

UNDEFINED

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

Rev: 1.15 6/2001 22/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Flow Through Mode No-Op, Stall and Deselect Timing

Preliminary.

GS882Z18/36B-11/100/80/66

CK

CKE

E*

ADV

W

Bn

A0–An

1 2

tH

tS

tH

tS

tH

tS

3

4

A1 A5A2 A3 A4

5 6

7

8

9

10

tKHQZ

DQ

COMMAND

Write
D(A1)

D(A1)

Read
Q(A2)

STALL Read

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

Q(A2)

Q(A3)

Q(A3)

Write
D(A4)

D(A4)

Q(A5)

tKQHZ

STALL

NOP

Read
Q(A5)

DESELECT

CONTINUE
DESELECT

DON’T CARE UNDEFINED

Rev: 1.15 6/2001 23/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some
functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP
(Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of
Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.

JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In

TMS

TDI Test Data In In

TDO Test Data Out Out

Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Test Mode

Select

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the
falling edge of TCK.

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state

In

machine. An undriven TMS input will produce the same result as a logic one input level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed

between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP
Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to
the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input
level.

Output that is active depending on the state of the TAP state machine. Output changes in response to the
falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.

JTAG Port Registers

Overview

The various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS
as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and
push serial data out on the next falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAMs JTAG Port to another device in the scan chain with as little delay as possible.

Rev: 1.15 6/2001 24/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

Boundary Scan Register

Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The
flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary
Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins
and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the
control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then
is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP instructions can be used to
activate the Boundary Scan Register.

JTAG TAP Block Diagram

0

Bypass Register

012

Instruction Register

TDI

ID Code Register

31 30 29

· · · ·

012

TDO

Boundary Scan Register

n

· · ·· · ·

· · ·

012

TMS
TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

Die

Revision

Not Used

Code

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12

x36

X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1

x32

X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1

x18

X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1

x16

X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 1 0 0 1 1

I/O

Configuration

1
1

GSI Technology

JEDEC Vendor

ID Code

Presence Register

10 9 8 7 6 5 4 3 2 1 0

Rev: 1.15 6/2001 25/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1­compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor
all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This
device will not perform EXTEST, INTEST or the SAMPLE/PRELOAD command.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

Run Test Idle

0

1

Select DR

1

Capture DR

0

0

Shift DR

1

1

Exit1 DR

0

Pause DR

1

Exit2 DR

1

Update DR

1

1 1

0

1

Capture IR

1

Select IR

Pause IR

0

0 0

Update IR

0

1 0

0

0

Shift IR

1

Exit1 IR

0

1

Exit2 IR

1

0

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.

Rev: 1.15 6/2001 26/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruc­tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con­tents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm
the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data cap­ture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O
ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the
TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update­DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This
functionality is not Standard 1149.1-compliant.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in
the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not 1149.1-compliant. Neverthe­less, this RAM’s TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction regis­ter the RAM responds just as it does in response to the BYPASS instruction described above.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound­ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

Rev: 1.15 6/2001 27/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

SAMPLE-Z 010

RFU 011

SAMPLE/

PRELOAD

100

GSI 101 GSI private instruction. 1

RFU 110

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
This RAM does not implement 1149.1 EXTEST function. *Not 1149.1 Compliant *

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant *

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

1

1

1

1

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

Test Port Input High Voltage

Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

V

V

I

INTH

I

INTL

I

OLT

V

OHT

V

IHT

ILT

–300 1 uA 3

OLT

Notes:

1. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

2. Input Under/overshoot voltage must be –2 V > Vi < V

+2 V with a pulse width not to exceed 20%

DD

tTKC.

3. V

DD ≥ VIN ≥ VIL

4. 0 V ≤ V

5. Output Disable, V

IN

≤ V

IL

OUT

= 0 to V

DD

6. The TDO output driver is served by the VDD supply.

7. I

8. I

= –4 mA

OH

= +4 mA

OL

V

1.7

DD

+0.3

–0.3 0.8 V 1, 2

–1 1 uA 4
–1 1 uA 5

2.4 — V 6, 7
— 0.4 V 6, 8

V 1, 2

Rev: 1.15 6/2001 28/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

JTAG Port AC Test Conditions

Preliminary.

GS882Z18/36B-11/100/80/66

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

Notes:

1. Include scope and jig capacitance.

JTAG Port Timing Diagram

tTKH

TCK

TMS

tTKL

tTS tTH

tTKC

DQ

JTAG Port AC Test Load

50Ω

VT = 1.25 V

* Distributed Test Jig Capacitance

30pF

*

TDI

TDO

tTKQ

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 20 — ns

TCK Low to TDO Valid tTKQ — 10 ns

TCK High Pulse Width tTKH 10 — ns

TCK Low Pulse Width tTKL 10 — ns

TDI & TMS Set Up Time tTS 5 — ns

TDI & TMS Hold Time tTH 5 — ns

Rev: 1.15 6/2001 29/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS882Z18/36B BGA Boundary Scan Register

Preliminary.

GS882Z18/36B-11/100/80/66

x36 x18

Bump

Order

1 PE 7R
2 PH = 0 n/a
3 A10 3T 2T
4 A11 4T 3T
5 A12 5T
6 A13 6R
7 A14 5C
8 A15 5B
9 A16 6C

x36 = DQA9

10

x32 = NA = 0

11 DQA8 NC = 1 7N
12 DQA4 NC = 1 6M
13 DQA3 NC = 1 7L
14 DQA7 NC = 1 6K
15 DQA6 DQA1 7P
16 DQA5 DQA2 6N
17 DQA2 DQA3 6L
18 DQA1 DQA4 7K
19 ZZ 7T
20 QE 5J
21 DQB5 DQA5 6H
22 DQB1 DQA6 7G
23 DQB2 DQA7 6F
24 DQB6 DQA8 7E

25 DQB3
26 DQB4 NC = 1 6G

27 DQB7 NC = 1 6E
28 DQB8 NC = 1 7D

x36 = DQB9

29

x32 = NA = 0

NC = 1 6P

x18 =DQA9

x16 = NA = 0

A18

x36 x18

7H 6D

6D 6T

x36 x18

Bump

Order

30 A9 6A
31 A8 5A
32 A17 4G
33 NC = 0 4A
34 ADV 4B
35 G 4F
36 CKE 4M
37 W 4H
38 CK 4K
39 PH = 0 n/a
40 PH = 1 n/a
41 CE3 6B
42 BA 5L
43 BB BB 5G 3G
44 BC NC = 1 3G 5G
45 BD NC = 1 3L
46 CE2 2B
47 CE1 4E
48 A7 3A
49 A6 2A

x36 =DQC9

50

x32 = NA = 0

51 DQC8 NC = 1 1E
52 DQC4 NC = 1 2F
53 DQC3 NC = 1 1G
54 DQC7 NC = 1 2H
55 DQC6 DQB1 1D
56 DQC5 DQB2 2E
57 DQC2 DQB3 2G
58 DQC1 DQB4 1H
59 FT 5R

NC = 1 2D

x36 x18

x36 x18

Bump

Order

60 DP 3J
61 PH = 1 n/a
62 DQD1 DQB5 2K
63 DQD2 DQB6 1L
64 DQD5 DQB7 2M
65 DQD6 DQB8 1N

66 DQD3
67 DQD4 NC = 1 2L

68 DQD7 NC = 1 2N
69 DQD8 NC = 1 1P

x36 = DQD9

70

x32 = NA = 0

71 LBO 3R
72 A5 2C
73 A4 3B
74 A3 3C
75 A2 2R
76 A1 4N
77 A0 4P
78 ZQ 4D

x18 = DQB9

x16 = NA = 0

NC = 1 2P 1K

x36 x18

1K 2P

BPR 1999.08.11

Note:

1. The Boundary Scan Register contains a number of registers that are not connected to any pin. They default to the value shown at reset.

2. Registers are listed in exit order (i.e., Location 1 is the first out of the TDO pin).

3. NC = No Connect, NA = Not Active

Rev: 1.15 6/2001 30/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

FLXDrive Output Driver Characteristics

I Out (mA)

VSS

120.0

100.0
Pull Down Drivers

80.0

60.0

40.0

Preliminary.

GS882Z18/36B-11/100/80/66

20.0

0.0

-20.0

-40.0

-60.0
Pull Up Drivers

-80.0

-100.0

-120.0

-140.0

-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4

VDD

I Out

VOut

V Out (Pull Down)

VDDQ - V Out (Pull Up)

3.6V PD HD 3.3V PD HD 3.1V PD HD 3.6V PD LD 3.3V PD LD 3.1V PD LD

3.1V PU LD 3.3V PU LD 3.6V PU LD 3.1V PU HD 3.3V PU HD 3.6V PU HD

BPR 1999.05.18

Rev: 1.15 6/2001 31/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Package Dimensions—119-Bump PBGA

Preliminary.

GS882Z18/36B-11/100/80/66

Pin 1
Corner

A

1234567

A

G

P

B

N

Top View

Package Dimensions—119-Bump PBGA

D

S

R

Bottom View

B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U

F

C T

Side View

Symbol Description Min Nom Max

A Width 13.8 14.0 14.2
B Length 21.8 22.0 22.2
C Package Height (including ball) — — 2.40
D Ball Size 0.60 0.75 0.90
E Ball Height 0.50 0.60 0.70

F Package Height (excluding balls) — 1.46 1.70

G Width between Balls — 1.27 —

K

E

K Package Height above board 0.80 0.90 1.00
N Cut-out Package Width — 12.00 —
P Foot Length — 19.50 —
R Width of package between balls — 7.62 —
S Length of package between balls — 20.32 —

T Variance of Ball Height — 0.15 —

Unit: mm

BPR 1999.05.18

Rev: 1.15 6/2001 32/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS882Z18/36B-11/100/80/66

Ordering Information—GSI NBT Synchronous SRAM

2

Org

512K x 18 GS882Z18B-11 ByteSafe NBT Pipeline/Flow Through BGA 100/11 C
512K x 18 GS882Z18B-100 ByteSafe NBT Pipeline/Flow Through BGA 100/12 C
512K x 18 GS882Z18B-80 ByteSafe NBT Pipeline/Flow Through BGA 80/14 C
512K x 18 GS882Z18B-66 ByteSafe NBT Pipeline/Flow Through BGA 66/18 C
256K x 36 GS882Z36B-11 ByteSafe NBT Pipeline/Flow Through BGA 100/11 C
256K x 36 GS882Z36B-100 ByteSafe NBT Pipeline/Flow Through BGA 100/12 C
256K x 36 GS882Z36B-80 ByteSafe NBT Pipeline/Flow Through BGA 80/14 C
256K x 36 GS882Z36B-66 ByteSafe NBT Pipeline/Flow Through BGA 66/18 C
512K x 18 GS882Z18B-11I ByteSafe NBT Pipeline/Flow Through BGA 100/11 I
512K x 18 GS882Z18B-100I ByteSafe NBT Pipeline/Flow Through BGA 100/12 I
512K x 18 GS882Z18B-80I ByteSafe NBT Pipeline/Flow Through BGA 80/14 I
512K x 18 GS882Z18B-66I ByteSafe NBT Pipeline/Flow Through BGA 66/18 I
256K x 36 GS882Z36B-11I ByteSafe NBT Pipeline/Flow Through BGA 100/11 I
256K x 36 GS882Z36B-100I ByteSafe NBT Pipeline/Flow Through BGA 100/12 I
256K x 36 GS882Z36B-80I ByteSafe NBT Pipeline/Flow Through BGA 80/14 I
256K x 36 GS882Z36B-66I ByteSafe NBT Pipeline/Flow Through BGA 66/18 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882Z36B-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some

Part Number

1

Type Package

Speed

(MHz/ns)

of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

3

T

A

Status

Rev: 1.15 6/2001 33/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Revision History

Preliminary.

GS882Z18/36B-11/100/80/66

DS/DateRev. Code: Old;

New

GS882Z818/36BRev1.04h 5/

1999;

1.05 9/1999

GS882Z818/36B 1.05 9/

1999K/ 1.06 10/1999

GS882Z818/36B 1.06 9/

1999K 1.07 1/2000L

Rev.1.10; 882Z18_r1_11 Content/Format

882Z18_r1_11;

882Z18_r1_12

Types of Changes
Format or Content

Format/Typos

Content

Format

Content

Content

Page /Revisions/Reason

• Last Page/Fixed “GSGS..” in Ordering Information
Note.Document/Changed format of all E’s from EN to EN.

• Timing Diagrams/Changed format. ex. A0 to A0.

• Flow Through Timing Diagrams/Upper case “T” in Flow
Through. thru to Through.

• Pin outs/Block Diagrams -Updated format to small caps.

• Added Rev History.

• Pin Outs/Numbered all data I/O’s.

• Boundary Scan/Ordered Data I/O pins correctly.

• Speed Bins on Page 1/Last column-changed 12ns to 15ns
and 15ns to 12ns.

• Improved Appearance of Timing Diagrams.

• Minor formatting changes.

• Changed pin 4J to VDD in x 18 Pinout.

• Took out overbar on NC in PinoutNew GSI Logo.Placed pin
4A in the No Connect list in the pin description.

• Removed 166 and 150 MHz speed bins

• Used 100 MHz Pipeline numbers for 133 MHz

• Changed all 133 MHz references to 11 ns

• Updated format to comply with Technical Publications
standards

• Updated Capitance table—removed Input row and changed
Output row to I/O

882Z18_r1_12;

882Z18_r1_13

882Z18_r1_13;

882Z18_r1_14

882Z18_r1_14;

882Z18_r1_15

Rev: 1.15 6/2001 34/34 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Content

Content

Content

• Corrected typo on pinouts

• Removed SCD/DCD reference from Mode Pin Functions table
on page 11

• Added parity bit references to x36 pad out

• Updated order of data input and output pins in pin description

table