GSI GS88219AB-150, GS88219AB-133I, GS88219AB-133, GS88219AB-250I, GS88219AB-250 Datasheet
...
1/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 5/17/02
GS88219/37AB
Datasheet Errata
Base datasheet:
GS88219/37AB, Rev.1.00, 3/2002
Product(s) covered in this supplement:
GS88219/37AB-250/225/200/166/150/133
Product specification(s) addressed by this supplement:
Bump R5
Note: The specifications cited in the base datasheet for the products addressed by this errata remain in force except where
superseded by the information in this errata.
2/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 5/17/02
GS88219/37AB
Datasheet Errata
GS88237A Pad Out
119 Bump BGA—Top View
1234567
A
V
DDQ
A
6
A
7
ADSP A
8
A
9
V
DDQ
B
NC NC A
4
ADSC A
15
A
17
NC
C
NC A
5
A
3
V
DD
A
14
A
16
NC
D
DQ
C4
DQ
C9
V
SS
ZQ V
SS
DQ
B9
DQ
B4
E
DQ
C3
DQ
C8
V
SS
E
1
V
SS
DQ
B8
DQ
B3
F
V
DDQ
DQ
C7
V
SS
G V
SS
DQ
B7
V
DDQ
G
DQ
C2
DQ
C6
B
C
ADV B
B
DQ
B6
DQ
B2
H
DQ
C1
DQ
C5
V
SS
GW V
SS
DQ
B5
DQ
B1
J
V
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
K
DQ
D1
DQ
D5
V
SS
CK V
SS
DQ
A5
DQ
A1
L
DQ
D2
DQ
D6
B
D
SCD B
A
DQ
A6
DQ
A2
M
V
DDQ
DQ
D7
V
SS
BW V
SS
DQ
A7
V
DDQ
N
DQ
D3
DQ
D8
V
SS
A
1
V
SS
DQ
A8
DQ
A3
P
DQ
D4
DQ
D9
V
SS
A
0
V
SS
DQ
A9
DQ
A4
R
NC A
2
LBO V
DD
V
DDQ
/
DNU
A
13
PE
T
NC NC A
10
A
11
A
12
NC ZZ
U
V
DDQ
TMS TDI TCK TDO NC V
DDQ
3/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 5/17/02
GS88219/37AB
Datasheet Errata
GS88219A Pad Out
119 Bump BGA—Top View
1234567
A
V
DDQ
A
6
A
7
ADSP A
8
A
9
V
DDQ
B
NC NC A
4
ADSC A
15
A
17
NC
C
NC A
5
A
3
V
DD
A
14
A
16
NC
D
DQ
B1
NC V
SS
ZQ V
SS
DQ
A9
NC
E
NC DQ
B2
V
SS
E
1
V
SS
NC DQ
A8
F
V
DDQ
NC V
SS
G V
SS
DQ
A7
V
DDQ
G
NC DQ
B3
B
B
ADV NC NC DQ
A6
H
DQ
B4
NC V
SS
GW V
SS
DQ
A5
NC
J
V
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
K
NC DQ
B5
V
SS
CK V
SS
NC DQ
A4
L
DQ
B6
NC NC SCD B
A
DQ
A3
NC
M
V
DDQ
DQ
B7
V
SS
BW V
SS
NC V
DDQ
N
DQ
B8
NC V
SS
A
1
V
SS
DQ
A2
NC
P
NC DQ
B9
V
SS
A
0
V
SS
NC DQ
A1
R
NC A
2
LBO V
DD
V
DDQ
/
DNU
A
13
PE
T
NC A
10
A
11
NC A
12
A
18
ZZ
U
V
DDQ
TMS TDI TCK TDO NC V
DDQ
4/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 5/17/02
GS88219/37AB
Datasheet Errata
GS88219/37A BGA Pin Description
Pin Location Symbol Type Description
P4, N4 A0, A
1
I Address field LSBs and Address Counter Preset Inputs
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, R2, R6, T3, T5
An I Address Inputs
T4 An I Address Input (x36 Versions)
T2, T6 NC — No Connect (x36 Versions)
T2, T6 An I Address Input (x18 Version)
K7, L7, N7, P7, K6, L6, M6, N6, P6
H7, G7, E7, D7, H6, G6, F6, E6, D6
H1, G1, E1, D1, H2, G2, F2, E2, D2
K1, L1, N1, P1, K2, L2, M2, N2, P2
DQ
A1
–DQ
A9
DQB1–DQ
B9
DQC1–DQ
C9
DQD1–DQ
D9
I/O Data Input and Output pins (x36 Versions)
L5, G5, G3, L3 B
A
, BB, BC, B
D
I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
DQ
A1–DQA9
DQB1–DQB9
I/O Data Input and Output pins (x18 Version)
L5, G3 B
A
, B
B
I Byte Write Enable for DQA, DQB I/Os; active low (x18 Version)
B1, B2, C1, R1, T1, U6, B7, C7, J3,
J5
NC — No Connect
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3, T4
NC — No Connect (x18 Version)
K4 CK I Clock Input Signal; active high
M4 BW
I Byte Write—Writes all enabled bytes; active low
H4 GW
I Global Write Enable—Writes all bytes; active low
E4 E
1 I Chip Enable; active low
F4 G
I Output Enable; active low
G4 ADV
I Burst address counter advance enable; active low
A4, B4 ADSP
, ADSC I Address Strobe (Processor, Cache Controller); active low
T7 ZZ I Sleep Mode control; active high
R3 LBO
I Linear Burst Order mode; active low
L4
SCD
I Single Cycle Deselect/Dual Cycle Deselect Mode Control
R7
PE
I Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
D4
ZQ
I
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
U2
TMS
I Scan Test Mode Select
5/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 5/17/02
GS88219/37AB
Datasheet Errata
U3
TDI
I Scan Test Data In
U5
TDO
O Scan Test Data Out
U4
TCK
I Scan Test Clock
J2, C4, J4, R4, J6
V
DD
I Core power supply
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
V
SS
I I/O and Core Ground
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
V
DDQ
I Output driver power supply
R5
V
DDQ
/DNU
—
V
DDQ
or V
DD
(must be tied high)
or
Do Not Use (must be left floating)
GS88219/37A BGA Pin Description
Pin Location Symbol Type Description
Rev: 1.00 3/2002 1/36 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88219/37AB-250/225/200/166/150/133
512K x 18, 256K x 36
9Mb SCD/DCD Sync Burst SRAMs
250 MHz–133MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119-Bump BGA
Commercial Temp
Industrial Temp
Features
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-bump BGA package
Functional Description
Applications
The GS88219/37AB is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
SCD and DCD Pipelined Reads
The GS88219/37AB is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS88219/37AB operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.0
4.0
2.2
4.4
2.5
5.0
2.9
6.0
3.3
6.7
3.5
7.5nsns
3.3 V
Curr (x18)
Curr (x36)
280
330
255
300
230
270
200
230
185
215
165
190mAmA
2.5 V
Curr (x18)
Curr (x36)
275
320
250
295
230
265
195
225
180
210
165
185mAmA
Rev: 1.00 3/2002 2/36 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88219/37AB-250/225/200/166/150/133
GS88237A Pad Out
119 Bump BGA—Top View
1 2 3 4 5 6 7
A
V
DDQ
A6 A7 ADSP A8 A9 V
DDQ
B
NC NC A4 ADSC A15 A17 NC
C
NC A5 A3 V
DD
A14 A16 NC
D
DQC4 DQC9 V
SS
ZQ V
SS
DQB9 DQB4
E
DQC3 DQC8 V
SS
E1 V
SS
DQB8 DQB3
F
V
DDQ
DQC7 V
SS
G V
SS
DQB7 V
DDQ
G
DQC2 DQC6 BC ADV BB DQB6 DQB2
H
DQC1 DQC5 V
SS
GW V
SS
DQB5 DQB1
J
V
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
K
DQD1 DQD5 V
SS
CK V
SS
DQA5 DQA1
L
DQD2 DQD6 BD SCD BA DQA6 DQA2
M
V
DDQ
DQD7 V
SS
BW V
SS
DQA7 V
DDQ
N
DQD3 DQD8 V
SS
A1 V
SS
DQA8 DQA3
P
DQD4 DQD9 V
SS
A0 V
SS
DQA9 DQA4
R
NC A2 LBO V
DD
NC A13 PE
T
NC NC A10 A11 A12 NC ZZ
U
V
DDQ
TMS TDI TCK TDO NC V
DDQ
Rev: 1.00 3/2002 3/36 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88219/37AB-250/225/200/166/150/133
GS88219A Pad Out
BPR1999.05.18
119 Bump BGA—Top View
1 2 3 4 5 6 7
A
V
DDQ
A6 A7 ADSP A8 A9 V
DDQ
B
NC NC A4 ADSC A15 A17 NC
C
NC A5 A3 V
DD
A14 A16 NC
D
DQB1 NC V
SS
ZQ V
SS
DQA9 NC
E
NC DQB2 V
SS
E1 V
SS
NC DQA8
F
V
DDQ
NC V
SS
G V
SS
DQA7 V
DDQ
G
NC DQB3 BB ADV NC NC DQA6
H
DQB4 NC V
SS
GW V
SS
DQA5 NC
J
V
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
K
NC DQB5 V
SS
CK V
SS
NC DQA4
L
DQB6 NC NC SCD BA DQA3 NC
M
V
DDQ
DQB7 V
SS
BW V
SS
NC V
DDQ
N
DQB8 NC V
SS
A1 V
SS
DQA2 NC
P
NC DQB9 V
SS
A0 V
SS
NC DQA1
R
NC A2 LBO V
DD
NC A13 PE
T
NC A10 A11 NC A12 A18 ZZ
U
V
DDQ
TMS TDI TCK TDO NC V
DDQ
Rev: 1.00 3/2002 4/36 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88219/37AB-250/225/200/166/150/133
GS88219/37A BGA Pin Description
Pin Location Symbol Type Description
P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, R2, R6, T3, T5
An I Address Inputs
T4 An I Address Input (x36 Versions)
T2, T6 NC — No Connect (x36 Versions)
T2, T6 An I Address Input (x18 Version)
K7, L7, N7, P7, K6, L6, M6, N6, P6
H7, G7, E7, D7, H6, G6, F6, E6, D6
H1, G1, E1, D1, H2, G2, F2, E2, D2
K1, L1, N1, P1, K2, L2, M2, N2, P2
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
I/O Data Input and Output pins (x36 Versions)
L5, G5, G3, L3 BA, BB, BC , BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
DQA1–DQA9
DQB1–DQB9
I/O Data Input and Output pins (x18 Version)
L5, G3 BA, BB I Byte Write Enable for DQA, DQB I/Os; active low (x18 Version)
B1, B2, C1, R1, T1, U6, B7, C7, J3,
J5, R5
NC — No Connect
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3, T4
NC — No Connect (x18 Version)
K4 CK I Clock Input Signal; active high
M4 BW I Byte Write—Writes all enabled bytes; active low
H4 GW I Global Write Enable—Writes all bytes; active low
E4 E1 I Chip Enable; active low
F4 G I Output Enable; active low
G4 ADV I Burst address counter advance enable; active low
A4, B4 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low
T7 ZZ I Sleep Mode control; active high
R3 LBO I Linear Burst Order mode; active low
L4
SCD
I Single Cycle Deselect/Dual Cycle Deselect Mode Control
R7
PE
I Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
D4
ZQ
I
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Rev: 1.00 3/2002 5/36 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88219/37AB-250/225/200/166/150/133
U2
TMS
I Scan Test Mode Select
U3
TDI
I Scan Test Data In
U5
TDO
O Scan Test Data Out
U4
TCK
I Scan Test Clock
J2, C4, J4, R4, J6
V
DD
I Core power supply
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
V
SS
I I/O and Core Ground
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
V
DDQ
I Output driver power supply
GS88219/37A BGA Pin Description
Pin Location Symbol Type Description
Rev: 1.00 3/2002 6/36 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88219/37AB-250/225/200/166/150/133
GS88219/37A (PE = 0) Block Diagram
A1
A0
A0
A1
D0
D1
Q1
Q0
Counter
Load
D Q
D Q
Register
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
DQ
Register
DQ
Register
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
E1
1
G
ZZ
Power Down
Control
Memory
Array
36
36
4
A
Q D
DQx1–DQx9
NC
Parity
NC
Parity
Encode
Compare
36
4
36
36
4
32
Note: Only x36 version shown for simplicity.
SCD
36
36
D Q
Register
4
BA
BB
BC
BD
Rev: 1.00 3/2002 7/36 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88219/37AB-250/225/200/166/150/133
GS88219/37A (PE = 1) x32 Mode Block Diagram
A1
A0
A0
A1
D0
D1
Q1
Q0
Counter
Load
D Q
D Q
Register
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
DQ
Register
DQ
Register
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
E1
1
G
ZZ
Power Down
Control
Memory
Array
36
36
4
A
Q D
DQx1–DQx9
NC
Parity
NC
Parity
Encode
Compare
32
4
32
36
4
32
Note: Only x36 version shown for simplicity.
SCD
D Q
Register
D Q
Register
Parity
Encode
32
4
32
36
Rev: 1.00 3/2002 8/36 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88219/37AB-250/225/200/166/150/133
Note:
Thereis a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin
Name
State Function
Burst Order Control LBO
L Linear Burst
H Interleaved Burst
Power Down Control ZZ
L or NC Active
H
Standby, IDD = I
SB
Single/Dual Cycle Deselect Control SCD
L Dual Cycle Deselect
H or NC Single Cycle Deselect
FLXDrive Output Impedance Control ZQ
L High Drive (Low Impedance)
H or NC Low Drive (High Impedance)
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
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