GSI GS881Z36BD-133I, GS881Z36BD-133, GS881Z36BT-225I, GS881Z36BT-225, GS881Z36BT-200I Datasheet
...
Rev: 1.00b 12/2002 1/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO
pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages
Functional Description
The GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D) is a
9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like
ZBT, NtRAM, NoBL or other pipelined read/double late write
or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO
) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D) is
implemented with GSI's high performance CMOS technology
and is available in a JEDEC-standard 100-pin TQFP package.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5nsns
3.3 V
Curr (x18)
Curr (x36)
280
330
255
300
230
270
200
230
185
215
165
190mAmA
2.5 V
Curr (x18)
Curr (x36)
275
320
250
295
230
265
195
225
180
210
165
185mAmA
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5nsns
3.3 V
Curr (x18)
Curr (x36)
175
200
165
190
160
180
150
170
145
165
135
150mAmA
2.5 V
Curr (x18)
Curr (x36)
175
200
165
190
160
180
150
170
145
165
135
150mAmA
Rev: 1.00b 12/2002 2/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
GS881Z18BT Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
B1
DQB2
V
SS
V
DDQ
DQ
B3
DQ
B4
FT
V
DD
NC
V
SS
DQB5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQB8
DQ
B9
V
SS
V
DDQ
V
DDQ
V
SS
DQ
A8
DQA7
V
SS
V
DDQ
DQ
A6
DQA5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQA2
DQA1
V
SS
V
DDQ
LBO
A5A4A3A2A1A
0
TMS
TDI
V
SS
V
DD
TDO
TCK
A
10
A
11
A12 A13 A14 A
16
A
6
A
7
E
1
E
2
NC
NC
B
B
B
A
E
3
CK
W
CKE
V
DD
V
SS
G
ADV
NC
A
17
A
8
A
9
A
15
512K x 18
Top View
DQA9
A
18
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00b 12/2002 3/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
GS881Z36BT Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C4
DQC3
V
SS
V
DDQ
DQ
C2
DQ
C1
FT
V
DD
NC
V
SS
DQD1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQD4
DQ
D5
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B4
DQB3
V
SS
V
DDQ
DQ
B2
DQB1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQA3
DQA4
V
SS
V
DDQ
LBO
A5A4A3A2A1A
0
TMS
TDI
V
SS
V
DD
TDO
TCK
A
10
A
11
A12 A13 A14 A
16
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
CK
W
CKE
V
DD
V
SS
G
ADV
NC
A
17
A
8
A
9
A
15
256K x 36
Top View
DQB5
DQ
B9
DQ
B7
DQB8
DQ
B6
DQA6
DQ
A5
DQA8
DQA7
DQA9
DQ
C7
DQ
C8
DQ
C6
DQD6
DQD8
DQD7
DQD9
DQC5
DQC9
10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00b 12/2002 4/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
100-Pin TQFP Pin Descriptions
Symbol Type Description
A0, A
1
In Burst Address Inputs; Preload the burst counter
A
2–A17
In Address Inputs
A
18 In Address Input
CK In Clock Input Signal
B
A
In Byte Write signal for data inputs DQA1–DQA9; active low
B
B In Byte Write signal for data inputs DQB1–DQB9; active low
BC
In Byte Write signal for data inputs DQC1–DQC9; active low
B
D
In Byte Write signal for data inputs DQD1–DQD9; active low
W
In Write Enable; active low
E1
In Chip Enable; active low
E
2
In Chip Enable—Active High. For self decoded depth expansion
E
3 In Chip Enable—Active Low. For self decoded depth expansion
G
In Output Enable; active low
ADV In Advance/Load
; Burst address counter control pin
CKE
In Clock Input Buffer Enable; active low
NC — No Connect
DQ
A1
–DQ
A9
I/O Byte A Data Input and Output pins
DQ
B1–DQB9 I/O Byte B Data Input and Output pins
DQC1
–DQ
C9
I/O Byte C Data Input and Output pins
DQ
D1
–DQ
D9
I/O Byte D Data Input and Output pins
ZZ In Power down control; active high
FT
In Pipeline/Flow Through Mode Control; active low
LBO
In Linear Burst Order; active low.
V
DD
In Core power supply
V
SS
In Ground
V
DDQ
In Output driver power supply
Rev: 1.00b 12/2002 5/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
165 Bump BGA—x18 Commom I/O—Top View (Package D)
123456 7891011
ANC
AE1BB NC E3
CKE
ADV A17 A
A189 A
BNC
AE2NCBACK W G
A18N
C
ANC B
CNCNC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC DQA C
DNC
DQB V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC DQA D
ENC
DQB V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC DQA E
FNC
DQB V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC DQA F
GNC
DQB V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC DQA G
HFT
MCH NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC NC ZZ H
J
DQB NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA NC J
K
DQB NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA NC K
L
DQB NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA NC L
M
DQB NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA NC M
N
DQB NC V
DDQ
V
SS
NC NC NC V
SS
V
DDQ
NC NC N
PNCNC
A ATDIA1 TDO A A ANC P
RLBO
NC A ATMSA0 TCK A A A AR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.00b 12/2002 6/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
165 Bump BGA—x32 Common I/O—Top View (Package D)
123456 7891011
ANC
AE1BC BB E3 CKE ADV A17 A NC A
BNC
AE2BDBA CK W G A18N
C
ANC B
CNCNC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC NC C
D
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB D
E
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB E
F
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB F
G
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB G
HFT
MCH NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC NC ZZ H
J
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA J
K
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA K
L
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA L
M
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA M
NNCNC
V
DDQ
V
SS
NC NC NC V
SS
V
DDQ
NC NC N
PNCNC
A ATDIA1 TDO A A ANC P
RLBO
NC A ATMSA0 TCK A A A AR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.00b 12/2002 7/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
165 Bump BGA—x36 Common I/O—Top View (Package D)
123456 7891011
ANC
AE1BC BB E3 CKE ADV A17 A NC A
BNC
AE2BDBA CK W G A18N
C
ANC B
C
DQC NC V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC DQB C
D
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB D
E
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB E
F
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB F
G
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB G
HFT
MCH NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC NC ZZ H
J
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA J
K
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA K
L
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA L
M
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA M
N
DQD NC V
DDQ
V
SS
NC NC NC V
SS
V
DDQ
NC DQA N
PNCNC
A ATDIA1 TDO A A ANC P
RLBO
NC A ATMSA0 TCK A A A AR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.00b 12/2002 8/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
GS881Z18/32/36BD 165-Bump BGA Pin Description
Symbol Type Description
A0, A
1
I Address field LSBs and Address Counter Preset Inputs
An I Address Inputs
A
17, A18, A19
I Address Inputs
DQ
A1
–DQ
A9
DQB1–DQ
B9
DQC1–DQ
C9
DQD1–DQ
D9
I/O Data Input and Output pins
B
A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC — No Connect
CK I Clock Input Signal; active high
CKE
I Clock Enable; active low
W
I Write Enable; active low
E
1
I Chip Enable; active low
E
3 I Chip Enable; active low
E2
I Chip Enable; active high
G
I Output Enable; active low
ADV I Burst address counter advance enable; active high
ZZ I Sleep mode control; active high
FT
I Flow Through or Pipeline mode; active low
LBO
I Linear Burst Order mode; active low
TMS
I Scan Test Mode Select
TDI
I Scan Test Data In
TDO
O Scan Test Data Out
TCK
I Scan Test Clock
MCH
— Must Connect High
DNU
—Do Not Use
V
DD
I Core power supply
V
SS
I I/O and Core Ground
V
DDQ
I Output driver power supply
Rev: 1.00b 12/2002 9/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
GS881Z18/32/36B NBT SRAM Functional Block Diagram
K
18
SA1
SA0
Burst
Counter
LBO
ADV
Memory
Array
G
CK
CKE
D Q
FT
NC
NC
DQa–DQn
K
SA1’
SA0’
D Q
Match
Write Address
Register 2
Write Address
Register 1
Write Data
Register 2
Write Data
Register 1
K
K
K
K
K
K
Sense Amps
Write Drivers
Read, Write and
Data Coherency
Control Logic
D Q
K
Parity
Check
FT
A
0
–An
E
3
E
2E1
W
B
D
B
C
B
B
B
A
Rev: 1.00b 12/2002 10/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load
pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE
is asserted low, all three
chip enables (E
1
, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (B
A
, BB, BC & BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Function W
B
A
B
B
B
C
B
D
Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L
Write all Bytes L L L L L
Write Abort/NOP L H H H H
Rev: 1.00b 12/2002 11/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
Synchronous Truth Table
Operation Type Address E1E2E3ZZ ADV W Bx G CKE CK DQ Notes
Deselect Cycle, Power Down D None H X X L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z
Deselect Cycle, Continue D None X X X L H X X X L L-H High-Z 1
Read Cycle, Begin Burst R External L H L L L H X L L L-H Q
Read Cycle, Continue Burst B Next X X X L H X X L L L-H Q 1,10
NOP/Read, Begin Burst R External L H L L L H X H L L-H High-Z 2
Dummy Read, Continue Burst B Next X X X L H X X H L L-H High-Z 1,2,10
Write Cycle, Begin Burst W External L H L L L L L X L L-H D 3
Write Cycle, Continue Burst B Next X X X L H X L X L L-H D 1,3,10
NOP/Write Abort, Begin Burst W None L H L L L L H X L L-H High-Z 2,3
Write Abort, Continue Burst B Next X X X L H X H X L L-H High-Z 1,2,3,10
Clock Edge Ignore, Stall Current X X X L X X X X H L-H - 4
Sleep Mode None X X X H X X X X X X High-Z
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect
cycle is executed first.
2. Dummy Read and Write abort can be considered NOP’s because the SRAM performs no operation. A Write abort occurs when the W
pin
is sampled low but no Byte Write pins are active so no Write operation is performed.
3. G
can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write
cycles.
4. If CKE
High occurs during a pipelined Read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a Write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx
= High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are low
6. All inputs, except G
and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE
high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.00b 12/2002 12/37 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)
Deselect
New Read New Write
Burst Read Burst Write
W
R
B
R
B
W
DD
B
B
W
R
D
B
W
R
D
D
Pipelined and Flow Through Read Write Control State Diagram
Current State (n)
Next State (n+1)
Transition
ƒ
Input Command Code
Key Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Clock (CK)
Command
Current State Next State
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
W
R
Loading...