Rev: 1.03 3/2000 1/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
512K x 18, 256K x 36
8Mb Sync Burst SRAMs
10ns - 14ns
3.3V VDD
3.3V & 2.5V I/O
100 Pin TQFP
Commercial Temp
Industrial Temp
Features
• Flow through mode operation.
• 3.3V +10%/-5% Core power supply.
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• 100-lead TQFP package
Functional Description
Applications
The GS880F18/32/36T is a 9,437,184 bit (8,388,608 bit for x32
version) high performance synchronous SRAM with a 2 bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPU’s, the device
now finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive edge triggered
clock input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Designing For Compatibility
The JEDEC Standard for Burst RAMS calls for a FT mode pin option
(pin 14 on TQFP). Board sites for Flow through Burst RAMS should
be designed with VSS connected to the FT pin location to ensure the
broadest access to multiple vendor sources. Boards designed with FT
pin pads tied low may be stuffed with GSI’s Pipeline/Flow through
configurable Burst RAMS or any vendor’s Flow through or
configurable Burst SRAM. Bumps designed with the FT pin location
tied High or floating must employ a non-configurable Flow through
Burst RAM, like this RAM, to achieve Flow through functionality.
88018/32/36TByte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS880F18/32/36T operates on a 3.3V power supply and all
inputs/outputs are 3.3V and 2.5V compatible. Separate output power
(V
DDQ
) pins are used to de-couple output noise from the internal
circuit.
-10 -11 -11.5 -12 -14
Flow Through
2-1-1-1
t
KQ
tCycle
I
DD
10ns
10ns
225mA
11ns
15ns
180mA
11.5ns
15ns
180mA
12ns
15ns
180mA
14ns
15ns
175mA
Rev: 1.03 3/2000 2/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
GS880F18 100 Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
VDD
NC
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
VSS
VDDQ
VDDQ
VSS
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
VSS
VDDQ
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
A17
A10
A11
A12
A13
A14
A16
A6
A7
E1
E2
NC
NC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A8
A9
A15
512K x 18
Top View
DQA9
A18
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
Rev: 1.03 3/2000 3/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
GS880F32 100 Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
VSS
VDDQ
VDDQ
VSS
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
VSS
VDDQ
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
A17
A10
A11
A12
A13
A14
A16
A6
A7
E1
E2
BD
BC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A8
A9
A15
256K x 32
Top View
DQB5
NC
DQB7
DQB8
DQB6
DQA6
DQA5
DQA8
DQA7
NC
DQC7
DQC8
DQC6
DQD6
DQD8
DQD7
NC
DQC5
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
Rev: 1.03 3/2000 4/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
GS880F36 100 Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
VSS
VDDQ
VDDQ
VSS
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
VSS
VDDQ
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
A17
A10
A11
A12
A13
A14
A16
A6
A7
E1
E2
BD
BC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A8
A9
A15
256K x 36
Top View
DQB5
DQB9
DQB7
DQB8
DQB6
DQA6
DQA5
DQA8
DQA7
DQA9
DQC7
DQC8
DQC6
DQD6
DQD8
DQD7
DQD9
DQC5
DQC9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
Rev: 1.03 3/2000 5/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
TQFP Pin Description
Pin Location Symbol Type Description
37, 36 A0, A1 I Address field LSB’s and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 43
A2-17 I Address Inputs
80 A18 I Address Inputs
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8
I/O Data Input and Output pins. (x32, x36 Version)
51, 80, 1, 30
DQA9, DQB9,
DQC9, DQD9
I/O Data Input and Output pins.
51, 80, 1, 30 NC - No Connect (x32 Version)
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQA1-DQA9
DQB1- DQB9
I/O Data Input and Output pins.
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7
25, 28, 29, 30
NC - No Connect
16 DP I Parity Input. 1 = Even, 0 = Odd.
66 QE O Parity Error Out. Open Drain Output.
87 BW I Byte Write. Writes all enabled bytes. Active Low.
93, 94 BA, BB I Byte Write Enable for DQA, DQB Data I/O’s. Active Low.
95, 96 BC, BD I
Byte Write Enable for DQC, DQD Data I/O’s. Active Low. (x32, x36
Version)
95, 96 NC - No Connect (x18 Version)
89 CK I Clock Input Signal. Active High.
88 GW I Global Write Enable. Writes all bytes. Active Low.
98, 92 E1, E3 I Chip Enable. Active Low.
97 E2 I Chip Enable. Active High.
86 G I Output Enable. Active Low.
83 ADV I Burst address counter advance enable. Active Low.
84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller). Active Low.
64 ZZ I Sleep Mode control. Active High.
31 LBO I Linear Burst Order mode. Active Low.
15, 41, 65, 91
V
DD
I Core power supply.
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
V
SS
I I/O and Core Ground.
4, 11, 20, 27, 54, 61, 70, 77
V
DDQ
I Output driver power supply.
14, 16, 38, 39, 42, 66 NC - No Connect.
Rev: 1.03 3/2000 6/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
GS880F18/32/36 Block Diagram
A1
A0
A0
A1
D0
D1
Q1
Q0
Counter
Load
D Q
D Q
Register
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
DQ
Register
DQ
Register
A0-An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
E1
G
ZZ
Power Down
Control
Memory
Array
4
A
Q D
E2
E3
1
0
36 36
DQx0-DQx9
Note: Only x36 version shown for simplicity.
Rev: 1.03 3/2000 7/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Note:
There is a pull up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Byte Write Truth Table
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Mode Pin Functions
Mode Name Pin Name State Function
Burst Order Control LBO
L Linear Burst
H or NC Interleaved Burst
Power Down Control ZZ
L or NC Active
H
Standby, IDD = I
SB
Function GW BW BA BB BC BD Notes
Read H H X X X X 1
Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4
Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Rev: 1.03 3/2000 8/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Synchronous Truth Table
Operation
Address
Used
State
Diagram
Key
5
E1
E2
2
(x36only)
ADSP ADSC ADV
W
3
DQ
4
Deselect Cycle, Power
Down
None X H X X L X X High-Z
Deselect Cycle, Power Down None X L F L X X X High-Z
Deselect Cycle, Power
Down
None X L F H L X X High-Z
Read Cycle, Begin Burst External R L T L X X X Q
Read Cycle, Begin Burst External R L T H L X F Q
Write Cycle, Begin Burst External W L T H L X T D
Read Cycle, Continue Burst Next CR X X H H L F Q
Read Cycle, Continue Burst Next CR H X X H L F Q
Write Cycle, Continue Burst Next CW X X H H L T D
Write Cycle, Continue Burst Next CW H X X H L T D
Read Cycle, Suspend Burst Current X X H H H F Q
Read Cycle, Suspend Burst Current H X X H H F Q
Write Cycle, Suspend Burst Current X X H H H T D
Write Cycle, Suspend Burst Current H X X H H T D
Note:
1. X = Don’t Care, H = High, L = Low.
2. For x36 Version, E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to
accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items
above.
Rev: 1.03 3/2000 9/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CRCW
X
X
W R
R
W R
XX
X
Simple Synchronous OperationSimple Burst Synchronous Operation
CR
R
CW CR
CR
Simplified State Diagram
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E1E2) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
Rev: 1.03 3/2000 10/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CRCW
X
X
W R
R
W
R
X
X
X
CR
R
CW CR
CR
W
CW
W
CW
Simplified State Diagram with G
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.03 3/2000 11/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V ≤ VDDQ ≤ 2.375V (i.e. 2.5V I/O)
and 3.6V ≤ VDDQ ≤ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be -2V > Vi < VDD+2V with a pulse width not to exceed 20% tKC.
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
V
DD
Voltage on VDD Pins
-0.5 to 4.6 V
V
DDQ
Voltage in V
DDQ
Pins -0.5 to V
DD
V
V
CK
Voltage on Clock Input Pin -0.5 to 6 V
V
I/O
Voltage on I/O Pins
-0.5 to V
DDQ
+0.5 (≤ 4.6 V
max.)
V
V
IN
Voltage on Other Input Pins
-0.5 to VDD+0.5 (≤ 4.6 V max.)
V
I
IN
Input Current on Any Pin +/- 20 mA
I
OUT
Output Current on Any I/O Pin +/- 20 mA
P
D
Package Power Dissipation 1.5 W
T
STG
Storage Temperature -55 to 125
o
C
T
BIAS
Temperature Under Bias -55 to 125
o
C
Recommended Operating Conditions
Parameter Symbol Min. Typ. Max. Unit Notes
Supply Voltage
V
DD
3.135 3.3 3.6 V
I/O Supply Voltage
V
DDQ
2.375 2.5
V
DD
V 1
Input High Voltage
V
IH
1.7 ---
VDD+0.3
V 2
Input Low Voltage
V
IL
-0.3 --- 0.8 V 2
Ambient Temperature (Commercial Range Versions)
T
A
0 25 70 °C 3
Ambient Temperature (Industrial Range Versions)
T
A
-40 25 85 °C 3
Rev: 1.03 3/2000 12/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Note: This parameter is sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, t
OLZ
and t
OHZ
.
4. Device is deselected as defined by the Truth Table.
Package Thermal Characteristics
Rating Layer Board Symbol Max Unit Notes
Junction to Ambient (at 200 lfm) single
R
ΘJA
40 °C/W 1,2
Junction to Ambient (at 200 lfm) four
R
ΘJA
24 °C/W 1,2
Junction to Case (TOP)
R
ΘJC
9 °C/W 3
AC Test Conditions
Parameter Conditions
Input high level 2.3V
Input low level 0.2V
Input slew rate 1V/ns
Input reference level 1.25V
Output reference level 1.25V
Output load Fig. 1& 2
20% tKC
VSS-2.0V
50%
V
SS
V
IH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKC
VDD+-2.0V
50%
V
DD
V
IL
Rev: 1.03 3/2000 13/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
DC Electrical Characteristics
Parameter
Symb
ol
Test Conditions Min Max
Input Leakage Current
(except mode pins)
I
IL
V
IN
= 0 to V
DD
-1uA 1uA
ZZ Input Current
I
INZZ
V
DD ≥ VIN ≥ VIH
0V ≤ V
IN
≤ V
IH
-1uA
-1uA
1uA
uA
Mode Pin Input Current
I
INM
V
DD ≥ VIN ≥ VIL
0V ≤ V
IN
≤ V
IL
-uA
-1uA
1uA
1uA
Output Leakage Current
I
OL
Output Disable,
V
OUT
= 0 to V
DD
-1uA 1uA
Output High Voltage
V
OH
I
OH
= - mA, V
DDQ
=2.375V
1.7V
Output High Voltage
V
OH
I
OH
= - mA, V
DDQ
=3.135V
2.4V
Output Low Voltage
V
OL
I
OL
= mA
0.4V
DQ
VT=1.25V
50Ω
30pF
*
DQ
2.5V
Output Load 1
Output Load 2
225Ω
225Ω
5pF
*
* Distributed Test Jig Capacitance
Rev: 1.03 3/2000 14/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V ≤ VDDQ ≤ 2.375V (i.e. 2.5V I/O)
and 3.6V ≤ VDDQ ≤ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be -2V > Vi < VDD+2V with a pulse width not to exceed 20% tKC.
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
V
DD
Voltage on VDD Pins
-0.5 to 4.6 V
V
DDQ
Voltage in V
DDQ
Pins -0.5 to V
DD
V
V
CK
Voltage on Clock Input Pin -0.5 to 6 V
V
I/O
Voltage on I/O Pins
-0.5 to V
DDQ
+0.5 (≤ 4.6 V
max.)
V
V
IN
Voltage on Other Input Pins
-0.5 to VDD+0.5 (≤ 4.6 V max.)
V
I
IN
Input Current on Any Pin +/- 20 mA
I
OUT
Output Current on Any I/O Pin +/- 20 mA
P
D
Package Power Dissipation 1.5 W
T
STG
Storage Temperature -55 to 125
o
C
T
BIAS
Temperature Under Bias -55 to 125
o
C
Recommended Operating Conditions
Parameter Symbol Min. Typ. Max. Unit Notes
Supply Voltage
V
DD
3.135 3.3 3.6 V
I/O Supply Voltage
V
DDQ
2.375 2.5
V
DD
V 1
Input High Voltage
V
IH
1.7 ---
VDD+0.3
V 2
Input Low Voltage
V
IL
-0.3 --- 0.8 V 2
Ambient Temperature (Commercial Range Versions)
T
A
0 25 70 °C 3
Ambient Temperature (Industrial Range Versions)
T
A
-40 25 85 °C 3
Rev: 1.03 3/2000 15/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Note: This parameter is sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, t
OLZ
and t
OHZ
.
4. Device is deselected as defined by the Truth Table.
Package Thermal Characteristics
Rating Layer Board Symbol Max Unit Notes
Junction to Ambient (at 200 lfm) single
R
ΘJA
40 °C/W 1,2
Junction to Ambient (at 200 lfm) four
R
ΘJA
24 °C/W 1,2
Junction to Case (TOP)
R
ΘJC
9 °C/W 3
AC Test Conditions
Parameter Conditions
Input high level 2.3V
Input low level 0.2V
Input slew rate 1V/ns
Input reference level 1.25V
Output reference level 1.25V
Output load Fig. 1& 2
20% tKC
VSS-2.0V
50%
V
SS
V
IH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKC
VDD+-2.0V
50%
V
DD
V
IL
Rev: 1.03 3/2000 16/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Operating Currents
DC Electrical Characteristics
Parameter
Symb
ol
Test Conditions Min Max
Input Leakage Current
(except mode pins)
I
IL
V
IN
= 0 to V
DD
-1uA 1uA
ZZ Input Current
I
INZZ
V
DD ≥ VIN ≥ VIH
0V ≤ V
IN
≤ V
IH
-1uA
-1uA
1uA
uA
Mode Pin Input Current
I
INM
V
DD ≥ VIN ≥ VIL
0V ≤ V
IN
≤ V
IL
-uA
-1uA
1uA
1uA
Output Leakage Current
I
OL
Output Disable,
V
OUT
= 0 to V
DD
-1uA 1uA
Output High Voltage
V
OH
I
OH
= - mA, V
DDQ
=2.375V
1.7V
Output High Voltage
V
OH
I
OH
= - mA, V
DDQ
=3.135V
2.4V
Output Low Voltage
V
OL
I
OL
= mA
0.4V
Parameter Test Conditions Symbol
-10 -11 -11.5 -12 -14
0 to
70°C
-40 to
85°C
0 to
70°C
-40 to
85°C
0 to
70°C
-40 to
85°C
0 to
70°C
-40 to
85°C
0 to
70°C
-40 to
85°C
Operating
Current
Device Selected;
All other inputs
≥VIH or ≤ V
IL
Output open
I
DD
Flow-Thru
225mA 235mA 180mA 190mA 180mA 190mA 180mA 190mA 175mA 185mA
Standby
Current
ZZ ≥ V
DD
- 0.2V
I
SB
Flow-Thru
30mA 40mA 30mA 40mA 30mA 40mA 30mA 40mA 30mA 40mA
Deselect
Current
Device Deselected;
All other inputs
≥ VIH or ≤ V
IL
I
DD
Flow-Thru
80mA 90mA 65mA 75mA 65mA 75mA 65mA 75mA 55 65
DQ
VT=1.25V
50Ω
30pF
*
DQ
2.5V
Output Load 1
Output Load 2
225Ω
225Ω
5pF
*
* Distributed Test Jig Capacitance
Rev: 1.03 3/2000 17/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
AC Electrical Characteristics
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Parameter Symbol
-10 -11 -11.5 -12 -14
Unit
Min Max Min Max Min Max Min Max Min Max
Flow-
Thru
Clock Cycle Time tKC 10.0 --- 10.0 --- 15.0 --- 15.0 --- 15.0 --- ns
Clock to Output Valid tKQ --- 8.0 --- 10.0 --- 11.0 --- 11.5 --- 12.0 ns
Clock to Output Invalid tKQX 3.0 --- 3.0 --- 3.0 --- 3.0 --- 3.0 --- ns
Clock to Output in Low-Z
tLZ
1
3.0 --- 3.0 --- 3.0 --- 3.0 --- 3.0 --- ns
Clock HIGH Time tKH 1.3 --- 1.5 --- 1.7 --- 1.7 --- 2 --- ns
Clock LOW Time tKL 1.5 --- 1.7 --- 2 --- 2 --- 2.2 --- ns
Clock to Output in High-Z
tHZ
1
1.5 3.2 1.5 3.8 1.5 4.0 1.5 4.2 1.5 4.5 ns
G to Output Valid tOE --- 3.2 --- 3.8 --- 4.0 --- 4.2 --- 4.5 ns
G to output in Low-Z
tOLZ
1
0 --- 0 --- 0 --- 0 --- 0 --- ns
G to output in High-Z
tOHZ
1
--- 3.2 --- 3.8 --- 4.0 --- 4.2 --- 4.5 ns
Setup time tS 1.5 --- 1.5 --- 1.5 --- 2.0 --- 2.0 --- ns
Hold time tH 0.5 --- 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns
ZZ setup time
tZZS
2
5 --- 5 --- 5 --- 5 --- 5 --- ns
ZZ hold time
tZZH
2
1 --- 1 --- 1 --- 1 --- 1 --- ns
ZZ recovery tZZR 20 --- 20 --- 20 --- 20 --- 20 --- ns
Rev: 1.03 3/2000 18/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
CK
ADSP
ADSC
ADV
GW
BW
G
WR2 WR3
WR1
WR1
WR2 WR3
tKC
Single Write
Burst Write
D2A D2B
D2C D2D D3A
D1A
tKL
tKH
tS
tH
tS tH
tS
tH
tS
tH
tS tH
tS
tH
tS
tH
tS
tH
Write specified byte for 2A and all bytes for 2B, 2c& 2D
ADV must be inactive for ADSP Write
ADSC initiated write
ADSP is blocked by E inactive
A0-An
BA - BD
DQA - DQD
Write
Deselected
Hi-Z
WR1 WR2 WR3
Write Cycle Timing
E1
E3
tS
tH
tS
tH
tS tH
E2 and E3 only sampled with ADSP or ADSC
E1 masks ADSP
E2
Deselected with E2
Rev: 1.03 3/2000 19/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Flow Through Read-Write Cycle Timing
CK
ADSP
ADSC
ADV
GW
BW
G
RD1
RD2
Q1A
Q2A
Q2B Q2c
Q2D
Single Read
Burst Read
tOE
tOHZ
tS
tH
tH
tS
tH
tS tH
tS
tH
tS
tH
tKH
ADSC initiated read
DQA - DQD
BA - BD
A0-An
tKL
tKC
tS
Single Write
ADSP is blocked by E inactive
tKQ
Hi-Z
Q2A
Burst wrap around to it’s initial state
E1
E3
E2
tS
tS
tH
tS
E1 masks ADSP
E2 and E3 only sampled with ADSP and ADSC
Deselected with E3
tH
tH
WR1
tS
WR1
tS
tH
D1A
tS
tH
Rev: 1.03 3/2000 20/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Q1A
Q3A
Q2D
Q2CQ2B
Q2A
tKQ
tLZ
tOE
tOHZ
tOLZ
tKQX
tHZ
tKQX
CK
ADSP
ADSC
BW
G
GW
ADV
Burst Read
RD2 RD3
tKL
tS
tH
tH
tS
tH
tS
tH
ADSC initiated read
Suspend Burst
Single Read
ADSP is blocked by E inactive
A0-An
BA - BD
tKH
tKC
tS
tH
tS
tS
tH
DQA-DQD
RD1
Hi-Z
Suspend Burst
Flow Through Read Cycle Timing
E2
tS
tH
tH
tH
E1 masks ADSP
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E3
E1
tS
tS
Rev: 1.03 3/2000 21/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
CK
ADSP
ADSC
tH
tKH
tKL
tKC
tS
ZZ
tZZR
tZZH
tZZS
~
~
~
~
~
~
~
~
~
~
~
~
Snooze
Sleep Mode Timing Diagram
Rev: 1.03 3/2000 22/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Output Driver Characteristics
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
40.0
60.0
80.0
100.0
120.0
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
I Out (mA)
3.6V PD HD 3.3V PD HD 3.1V PD HD 3.1V PU HD 3.3V PU HD 3.6V PU HD
Pull Up Drivers
Pull Down Drivers
VDDQ
VOut
I Out
VSS
Rev: 1.03 3/2000 23/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
TQFP Package Drawing
BPR 1999.05.18
D1
D
E1
E
Pin 1
b
e
c
L
L1
A2
A1
Y
θ
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
b Lead Width 0.20 0.30 0.40
c Lead Thickness 0.09 0.20
D Terminal Dimension 21.9 22.0 22.1
D1 Package Body 19.9 20.0 20.1
E Terminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
e Lead Pitch 0.65
L Foot Length 0.45 0.60 0.75
L1 Lead Length 1.00
Y Coplanarity 0.10
θ Lead Angle 0° 7°
Rev: 1.03 3/2000 24/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Ordering Information for GSI Synchronous Burst RAMs
Org
Part Number
1
Type Package
Speed
2
(Mhz/ns)
T
A
3
Status
512K x 18 GS880F18T-10 Flow Through TQFP 10 C
512K x 18 GS880F18T-11 Flow Through TQFP 11 C
512K x 18 GS880F18T-11.5 Flow Through TQFP 11.5 C
512K x 18 GS880F18T-12 Flow Through TQFP 12 C
512K x 18 GS880F18T-14 Flow Through TQFP 14 C
256K x 32 GS880F32T-10 Flow Through TQFP 10 C
256K x 32 GS880F32T-11 Flow Through TQFP 11 C
256K x 32 GS880F32T--11.5 Flow Through TQFP 11.5 C
256K x 32 GS880F32T-12 Flow Through TQFP 12 C
256K x 32 GS880F32T-14 Flow Through TQFP 14 C
256K x 36 GS880F36T-10 Flow Through TQFP 10 C
256K x 36 GS880F36T-11 Flow Through TQFP 11 C
256K x 36 GS880F36T--11.5 Flow Through TQFP 11.5 C
256K x 36 GS880F36T-12 Flow Through TQFP 12 C
256K x 36 GS880F36T-14 Flow Through TQFP 14 C
512K x 18 GS880F18T-10I Flow Through TQFP 10 I Not Available
512K x 18 GS880F18T-11I Flow Through TQFP 11 I
512K x 18 GS880F18T--11.5I Flow Through TQFP 11.5 I
512K x 18 GS880F18T-12I Flow Through TQFP 12 I
512K x 18 GS880F18T-14I Flow Through TQFP 14 I
256K x 32 GS880F32T-10 Flow Through TQFP 10 I Not Available
256K x 32 GS880F32T-11 Flow Through TQFP 11 I
256K x 32 GS880F32T--11.5 Flow Through TQFP 11.5 I
256K x 32 GS880F32T-12 Flow Through TQFP 12 I
256K x 32 GS880F32T-14 Flow Through TQFP 14 I
256K x 36 GS880F36T-10I Flow Through TQFP 10 I Not Available
256K x 36 GS880F36T-11I Flow Through TQFP 11 I
256K x 36 GS880F36T--11.5I Flow Through TQFP 11.5 I
256K x 36 GS880F36T-12I Flow Through TQFP 12 I
256K x 36 GS880F36T-14I Flow Through TQFP 14 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880LF18TT.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Rev: 1.03 3/2000 25/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
GS880F18/361.00 11/1999J
Content
• First Release of 880 F.
GS880F18/36T1.00
K880F18/36T1.02 1/2000L
Content
• Changed Flow Through Read-Write Cycle Timing Diagram for accuracy.
• Changed order of TQFP Address Inputs to match pinout.
• Changed order of TQFP DATA Input and Output pins to match pinout.
• New GSI Logo.
GS880F1836T Rev. 1.02 1/2000L;
GS880F1836T Rev. 1.03 3/2000N
Content
• Changed all speed bin information (headings, references, tables, ordering
info..) to reflect 14 -10Mhz
Loading...