GSI GS880F36T-14I, GS880F36T-14, GS880F36T-12I, GS880F36T-12, GS880F36T-11I Datasheet

Rev: 1.03 3/2000 1/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N

Preliminary

GS880F18/36T-10/11/11.5/12/14

512K x 18, 256K x 36

8Mb Sync Burst SRAMs

10ns - 14ns

3.3V VDD

3.3V & 2.5V I/O

100 Pin TQFP
Commercial Temp
Industrial Temp

Features

• Flow through mode operation.

• 3.3V +10%/-5% Core power supply.

• 2.5V or 3.3V I/O supply.

• LBO pin for linear or interleaved burst mode.

• Internal input resistors on mode pins allow floating mode pins.
Default to Interleaved Pipelined Mode.

• Byte write (BW) and/or global write (GW) operation.

• Common data inputs and data outputs.

• Clock Control, registered, address, data, and control.

• Internal Self-Timed Write cycle.

• Automatic power-down for portable applications.

• 100-lead TQFP package

Functional Description

Applications

The GS880F18/32/36T is a 9,437,184 bit (8,388,608 bit for x32
version) high performance synchronous SRAM with a 2 bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPU’s, the device
now finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support.

Controls

Addresses, data I/O’s, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive edge triggered
clock input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.

Designing For Compatibility

The JEDEC Standard for Burst RAMS calls for a FT mode pin option
(pin 14 on TQFP). Board sites for Flow through Burst RAMS should
be designed with VSS connected to the FT pin location to ensure the

broadest access to multiple vendor sources. Boards designed with FT
pin pads tied low may be stuffed with GSI’s Pipeline/Flow through
configurable Burst RAMS or any vendor’s Flow through or
configurable Burst SRAM. Bumps designed with the FT pin location
tied High or floating must employ a non-configurable Flow through
Burst RAM, like this RAM, to achieve Flow through functionality.

88018/32/36TByte Write and Global Write
Byte write operation is performed by using byte write enable (BW)

input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.

Core and Interface Voltages

The GS880F18/32/36T operates on a 3.3V power supply and all
inputs/outputs are 3.3V and 2.5V compatible. Separate output power
(V

DDQ

) pins are used to de-couple output noise from the internal

circuit.

-10 -11 -11.5 -12 -14

Flow Through

2-1-1-1

t

KQ

tCycle

I

DD

10ns
10ns

225mA

11ns
15ns

180mA

11.5ns
15ns

180mA

12ns
15ns

180mA

14ns
15ns

175mA

Rev: 1.03 3/2000 2/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N

Preliminary

GS880F18/36T-10/11/11.5/12/14

GS880F18 100 Pin TQFP Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

VDDQ

VSS

DQB1
DQB2

VSS

VDDQ
DQB3
DQB4

VDD
NC

VSS
DQB5
DQB6

VDDQ

VSS
DQB7
DQB8
DQB9

VSS

VDDQ

VDDQ
VSS

DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1

VSS
VDDQ

LBO

A5

A4

A3

A2

A1

A0

NC

NC

VSS

VDD

NC

A17

A10

A11

A12

A13

A14

A16

A6

A7

E1

E2

NC

NC

BB

BA

E3

CK

GW

BW

VDD

VSS

G

ADSC

ADSP

ADV

A8

A9

A15

512K x 18

Top View

DQA9

A18

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NC

Rev: 1.03 3/2000 3/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N

Preliminary

GS880F18/36T-10/11/11.5/12/14

GS880F32 100 Pin TQFP Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

VDDQ

VSS

DQC4
DQC3

VSS

VDDQ
DQC2
DQC1

VDD
NC

VSS
DQD1
DQD2

VDDQ

VSS
DQD3
DQD4
DQD5

VSS

VDDQ

VDDQ
VSS

DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4

VSS
VDDQ

LBO

A5

A4

A3

A2

A1

A0

NC

NC

VSS

VDD

NC

A17

A10

A11

A12

A13

A14

A16

A6

A7

E1

E2

BD

BC

BB

BA

E3

CK

GW

BW

VDD

VSS

G

ADSC

ADSP

ADV

A8

A9

A15

256K x 32

Top View

DQB5

NC

DQB7

DQB8

DQB6

DQA6

DQA5

DQA8

DQA7

NC

DQC7

DQC8

DQC6

DQD6

DQD8

DQD7

NC

DQC5

NC

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NC

Rev: 1.03 3/2000 4/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N

Preliminary

GS880F18/36T-10/11/11.5/12/14

GS880F36 100 Pin TQFP Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

VDDQ

VSS

DQC4
DQC3

VSS

VDDQ
DQC2
DQC1

VDD
NC

VSS
DQD1
DQD2

VDDQ

VSS
DQD3
DQD4
DQD5

VSS

VDDQ

VDDQ
VSS

DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4

VSS
VDDQ

LBO

A5

A4

A3

A2

A1

A0

NC

NC

VSS

VDD

NC

A17

A10

A11

A12

A13

A14

A16

A6

A7

E1

E2

BD

BC

BB

BA

E3

CK

GW

BW

VDD

VSS

G

ADSC

ADSP

ADV

A8

A9

A15

256K x 36

Top View

DQB5

DQB9

DQB7

DQB8

DQB6

DQA6

DQA5

DQA8

DQA7

DQA9

DQC7

DQC8

DQC6

DQD6

DQD8

DQD7

DQD9

DQC5

DQC9

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NC

Rev: 1.03 3/2000 5/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N

Preliminary

GS880F18/36T-10/11/11.5/12/14

TQFP Pin Description

Pin Location Symbol Type Description

37, 36 A0, A1 I Address field LSB’s and Address Counter preset Inputs

35, 34, 33, 32, 100, 99, 82, 81, 44, 45,

46, 47, 48, 49, 50, 43

A2-17 I Address Inputs

80 A18 I Address Inputs

63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79

13, 12, 9, 8, 7, 6, 3, 2

18, 19, 22, 23, 24, 25, 28, 29

DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8

I/O Data Input and Output pins. (x32, x36 Version)

51, 80, 1, 30

DQA9, DQB9,

DQC9, DQD9

I/O Data Input and Output pins.

51, 80, 1, 30 NC - No Connect (x32 Version)

58, 59, 62, 63, 68, 69, 72, 73, 74

8, 9, 12, 13, 18, 19, 22, 23, 24

DQA1-DQA9

DQB1- DQB9

I/O Data Input and Output pins.

51, 52, 53, 56, 57

75, 78, 79,

1, 2, 3, 6, 7

25, 28, 29, 30

NC - No Connect

16 DP I Parity Input. 1 = Even, 0 = Odd.
66 QE O Parity Error Out. Open Drain Output.
87 BW I Byte Write. Writes all enabled bytes. Active Low.

93, 94 BA, BB I Byte Write Enable for DQA, DQB Data I/O’s. Active Low.
95, 96 BC, BD I

Byte Write Enable for DQC, DQD Data I/O’s. Active Low. (x32, x36

Version)

95, 96 NC - No Connect (x18 Version)

89 CK I Clock Input Signal. Active High.
88 GW I Global Write Enable. Writes all bytes. Active Low.

98, 92 E1, E3 I Chip Enable. Active Low.

97 E2 I Chip Enable. Active High.
86 G I Output Enable. Active Low.
83 ADV I Burst address counter advance enable. Active Low.

84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller). Active Low.

64 ZZ I Sleep Mode control. Active High.
31 LBO I Linear Burst Order mode. Active Low.

15, 41, 65, 91

V

DD

I Core power supply.

5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90

V

SS

I I/O and Core Ground.

4, 11, 20, 27, 54, 61, 70, 77

V

DDQ

I Output driver power supply.

14, 16, 38, 39, 42, 66 NC - No Connect.

Rev: 1.03 3/2000 6/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N

Preliminary

GS880F18/36T-10/11/11.5/12/14

GS880F18/32/36 Block Diagram

A1

A0

A0

A1

D0
D1

Q1

Q0

Counter

Load

D Q

D Q

Register

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

DQ

Register

DQ

Register

A0-An

LBO

ADV
CK

ADSC
ADSP

GW

BW
BA

BB

BC

BD

E1

G

ZZ

Power Down

Control

Memory

Array

4

A

Q D

E2
E3

1

0

36 36

DQx0-DQx9

Note: Only x36 version shown for simplicity.

Rev: 1.03 3/2000 7/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N

Preliminary

GS880F18/36T-10/11/11.5/12/14

Note:
There is a pull up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.

Burst Counter Sequences

BPR 1999.05.18

Byte Write Truth Table

Note:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x32 and x36 versions.

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

L Linear Burst

H or NC Interleaved Burst

Power Down Control ZZ

L or NC Active

H

Standby, IDD = I

SB

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

I

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01
4th address 11 00 01 10

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01
4th address 11 10 01 00

Rev: 1.03 3/2000 8/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N

Preliminary

GS880F18/36T-10/11/11.5/12/14

Synchronous Truth Table

Operation

Address

Used

State

Diagram

Key

5

E1

E2

2

(x36only)

ADSP ADSC ADV

W

3

DQ

4

Deselect Cycle, Power

Down

None X H X X L X X High-Z

Deselect Cycle, Power Down None X L F L X X X High-Z

Deselect Cycle, Power

Down

None X L F H L X X High-Z

Read Cycle, Begin Burst External R L T L X X X Q

Read Cycle, Begin Burst External R L T H L X F Q
Write Cycle, Begin Burst External W L T H L X T D

Read Cycle, Continue Burst Next CR X X H H L F Q

Read Cycle, Continue Burst Next CR H X X H L F Q

Write Cycle, Continue Burst Next CW X X H H L T D

Write Cycle, Continue Burst Next CW H X X H L T D
Read Cycle, Suspend Burst Current X X H H H F Q
Read Cycle, Suspend Burst Current H X X H H F Q

Write Cycle, Suspend Burst Current X X H H H T D
Write Cycle, Suspend Burst Current H X X H H T D

Note:

1. X = Don’t Care, H = High, L = Low.

2. For x36 Version, E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active driv­ers (shown as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to
accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items
above.