GSI GS840H32B-180I, GS840H32B-180, GS840H32B-166I, GS840H32B-166, GS840H32B-150I Datasheet
...
Rev: 2.04 6/2000 1/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36T/B-180/166/150/100
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
180Mhz - 100Mhz
3.3V VDD
3.3V & 2.5V I/O
TQFP, BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user configurable flow through or pipelined operation.
• Single Cycle Deselect (SCD) Operation.
• High Output Drive current.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or 119 Bump BGA package.
Functional Description
Applications
The GS840H18/32/36 is a 4,718,592 bit (4,194,304 bit for x32
version) high performance synchronous SRAM with a 2 bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPU’s, the device
now finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support. The GS840H18/32/36
is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA
package.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through / Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the
BGA, ). Holding the FT mode pin/bump low places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
SCD Pipelined Reads
The GS840H18/32/36 is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available.SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS840H18/32/36 operates on a 3.3V power supply and all
inputs/outputs are 3.3V and 2.5V compatible. Separate output power
(VDDQ) pins are used to de-couple output noise from the internal
circuit.
-180 -166 -150 -100
Pipeline
3-1-1-1
tCycle
tKQ
IDD
5.5ns
3.2ns
330mA
6.0ns
3.5ns
310mA
6.6ns
3.8ns
275mA
10ns
4.5ns
190mA
Flow Through
2-1-1-1
tKQ
tCycle
IDD
8ns
10ns
190mA
8.5ns
10ns
190mA
10ns
10ns
190mA
12ns
15ns
140mA
Rev: 2.04 6/2000 2/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS840H18/32/36T/B-180/166/150/100
GS840H18 100 Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
VDD
NC
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
VSS
VDDQ
VDDQ
VSS
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
VSS
VDDQ
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A16
A6
A7
E1
E2
NC
NC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADVA8A9
A15
256K x 18
Top View
DQA9
A17
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 2.04 6/2000 3/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS840H18/32/36T/B-180/166/150/100
GS840H32 100 Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
VSS
VDDQ
VDDQ
VSS
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
VSS
VDDQ
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A16
A6
A7
E1
E2
BD
BC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADVA8A9
A15
128K x 32
Top View
DQB5
NC
DQB7
DQB8
DQB6
DQA6
DQA5
DQA8
DQA7
NC
DQC7
DQC8
DQC6
DQD6
DQD8
DQD7
NC
DQC5
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 2.04 6/2000 4/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS840H18/32/36T/B-180/166/150/100
GS840H36 100 Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
VSS
VDDQ
VDDQ
VSS
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
VSS
VDDQ
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A16
A6
A7
E1
E2
BD
BC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADVA8A9
A15
128K x 36
Top View
DQB5
DQB9
DQB7
DQB8
DQB6
DQA6
DQA5
DQA8
DQA7
DQA9
DQC7
DQC8
DQC6
DQD6
DQD8
DQD7
DQD9
DQC5
DQC9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 2.04 6/2000 5/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS840H18/32/36T/B-180/166/150/100
TQFP Pin Description
Pin Location Symbol Type Description
37, 36 A0, A1 I Address field LSB’s and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46,
47, 48, 49, 50
A2-16 I Address Inputs
80 A17 I Address Inputs (x18 versions)
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8
I/O Data Input and Output pins. (x32, x36 Version)
51, 80, 1, 30
DQA9, DQB9,
DQC9, DQD9
I/O Data Input and Output pins. (x36 Version)
51, 80, 1, 30 NC No Connect (x32 Version)
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQA1-DQA9
DQB1-DQB9
I/O Data Input and Output pins. (x18 Version)
51, 52, 53, 56, 57
75, 78, 79
1, 2, 3, 6, 7
25, 28, 29, 30
NC - No Connect (x18 Version)
87 BW I Byte Write. Writes all enabled bytes. Active Low.
93, 94 BA, BB I Byte Write Enable for DQA, DQB Data I/O’s. Active Low.
95, 96 BC, BD I
Byte Write Enable for DQC, DQD Data I/O’s. Active Low.
(x32, x36 Version)
95, 96 NC - No Connect (x18 Version)
89 CK I Clock Input Signal. Active High.
88 GW I Global Write Enable. Writes all bytes. Active Low.
98, 92 E1, E3 I Chip Enable. Active Low.
97 E2 I Chip Enable. Active High.
86 G I Output Enable. Active Low.
83 ADV I Burst address counter advance enable. Active Low.
84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller). Active Low.
64 ZZ I Sleep Mode control. Active High.
14 FT I Flow Through or Pipeline mode. Active Low.
31 LBO I Linear Burst Order mode. Active Low.
15, 41, 65, 91 VDD I Core power supply.
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS I I/O and Core Ground.
4, 11, 20, 27, 54, 61, 70, 77 VDDQ I Output driver power supply.
16, 38, 39, 42, 43, 66 NC - No Connect.
Rev: 2.04 6/2000 6/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS840H18/32/36T/B-180/166/150/100
GS840H18 Pad Out
119 Bump BGA - Top View
1 2 3 4 5 6 7
A
VDDQ A6 A7 ADSP A8 A9 VDDQ
B
NC E2 A4 ADSC A15 E3 NC
C
NC A5 A3 VDD A14 A16 NC
D
DQB1 NC VSS NC VSS DQA9 NC
E
NC DQB2 VSS E1 VSS NC DQA8
F
VDDQ NC VSS G VSS DQA7 VDDQ
G
NC DQB3 BB ADV NC NC DQA6
H
DQB4 NC VSS GW VSS DQA5 NC
J
VDDQ VDD NC VDD NC VDD VDDQ
K
NC DQB5 VSS CK VSS NC DQA4
L
DQB6 NC NC NC BA DQA3 NC
M
VDDQ DQB7 VSS BW VSS NC VDDQ
N
DQB8 NC VSS A1 VSS DQA2 NC
P
NC DQB9 VSS A0 VSS NC DQA1
R
NC A2 LBO VDD FT A13 NC
T
NC A10 A11 NC A12 A17 ZZ
U
VDDQ NC NC NC NC NC VDDQ
Rev: 2.04 6/2000 7/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS840H18/32/36T/B-180/166/150/100
GS840H32 Pad Out
119 Bump BGA - Top View
1 2 3 4 5 6 7
A
VDDQ A6 A7 ADSP A8 A9 VDDQ
B
NC E2 A4 ADSC A15 E3 NC
C
NC A5 A3 VDD A14 A16 NC
D
DQC4 NC VSS NC VSS NC DQB4
E
DQC3 DQC8 VSS E1 VSS DQB8 DQB3
F
VDDQ DQC7 VSS G VSS DQB7 VDDQ
G
DQC2 DQC6 BC ADV BB DQB6 DQB2
H
DQC1 DQC5 VSS GW VSS DQB5 DQB1
J
VDDQ VDD NC VDD NC VDD VDDQ
K
DQD1 DQD5 VSS CK VSS DQA5 DQA1
L
DQD2 DQD6 BD NC BA DQA6 DQA2
M
VDDQ DQD78 VSS BW VSS DQA7 VDDQ
N
DQD3 DQD8 VSS A1 VSS DQA8 DQA3
P
DQD4 NC VSS A0 VSS NC DQA4
R
NC A2 LBO VDD FT A13 NC
T
NC NC A10 A11 A12 NC ZZ
U
VDDQ NC NC NC NC NC VDDQ
Rev: 2.04 6/2000 8/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS840H18/32/36T/B-180/166/150/100
GS840H36Pad Out
119 Bump BGA - Top View
1 2 3 4 5 6 7
A
VDDQ A6 A7 ADSP A8 A9 VDDQ
B
NC E2 A4 ADSC A15 E3 NC
C
NC A5 A3 VDD A14 A16 NC
D
DQC4 DQC9 VSS NC VSS DQB9 DQB4
E
DQC3 DQC8 VSS E1 VSS DQB8 DQB3
F
VDDQ DQC7 VSS G VSS DQB7 VDDQ
G
DQC2 DQC6 BC ADV BB DQB6 DQB2
H
DQC1 DQC5 VSS GW VSS DQB5 DQB1
J
VDDQ VDD NC VDD NC VDD VDDQ
K
DQD1 DQD5 VSS CK VSS DQA5 DQA1
L
DQD2 DQD6 BD NC BA DQA6 DQA2
M
VDDQ DQD78 VSS BW VSS DQA7 VDDQ
N
DQD3 DQD8 VSS A1 VSS DQA8 DQA3
P
DQD4 DQD9 VSS A0 VSS DQA9 DQA4
R
NC A2 LBO VDD FT A13 NC
T
NC NC A10 A11 A12 NC ZZ
U
VDDQ NC NC NC NC NC VDDQ
Rev: 2.04 6/2000 9/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS840H18/32/36T/B-180/166/150/100
BGA Pin Description
Pin Location Symbol Type Description
N4, P4 A0, A1 I Address field LSB’s and Address Counter Preset Inputs.
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, R2, R6, T3, T5
An I Address Inputs
T4 An Address Input (x32/36 Versions)
T2, T6 NC - No Connect (x32/36 Versions)
T2, T6 An I Address Input (x18 Version)
K7, K6, L7, L6, M6, N7, N6, P7
H7, H6, G7, G6, F6, E7, E6, D7
H1, H2, G1, G2, F2, E1, E2, D1
K1, K2, L1, L2, M2, N1, N2, P1
DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8
I/O Data Input and Output pins. (x32/36 Versions)
P6, D6, D2, P2
DQA9, DQB9,
DQC9, DQD9
I/O Data Input and Output pins. (x36 Version)
P6, D6, D2, P2 NC - No Connect (x32 Version)
L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/O’s. Active Low. ( x36 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
DQA1-DQA9
DQB1-DQB9
I/O Data Input and Output pins. (x18 Version)
L5, G3 BA, BB I Byte Write Enable for DQA, DQB I/O’s. Active Low. ( x18 Version)
B1, C1, R1, T1, U2, J3, U3, D4, L4,
U4, J5, U5, U6, B7, C7, R7
NC - No Connect
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, B1, E1, F2, G1, H2, K1, L2, N2,
P1, G5, L3, T4
NC - No Connect (x18 Version)
K4 CK I Clock Input Signal. Active High.
M4 BW I Byte Write. Writes all enabled bytes. Active Low.
H4 GW I Global Write Enable. Writes all bytes. Active Low.
E4, B6 E1, E3 I Chip Enable. Active Low.
B2 E2 I Chip Enable. Active High.
F4 G I Output Enable. Active Low.
G4 ADV I Burst address counter advance enable. Active Low.
A4, B4 ADSP, ADSC I Address Strobe (Processor, Cache Controller). Active Low.
T7 ZZ I Sleep Mode control. Active High.
R5 FT I Flow Through or Pipeline mode. Active Low.
R3 LBO I Linear Burst Order mode. Active Low.
J2, C4, J4, R4, J6 VDD I Core power supply.
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
VSS I I/O and Core Ground.
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
VDDQ I Output driver power supply.
Rev: 2.04 6/2000 10/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS840H18/32/36T/B-180/166/150/100
GS840H18/32/36 Block Diagram
A1
A0
A0
A1
D0
D1
Q1
Q0
Counter
Load
D Q
D Q
Register
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
DQ
Register
DQ
Register
A0-An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
E1
G
ZZ
Power Down
Control
Memory
Array
36
36
4
A
Q D
E3
E2
DQx0-DQx9
Note: Only x36 version shown for simplicity.
1
FT
Loading...