GS84018/32/36T/B-180/166/150/100
TQFP, BGA
256K x 18, 128K x 32, 128K x 36
Commercial Temp
Industrial Temp
4Mb Sync Burst SRAMs
Features
• FT pin for user configurable flow through or pipelined operation.
• Single Cycle Deselect (SCD) Operation.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or 119 Bump BGA package.
-180 -166 -150 -100
Pipeline
3-1-1-1
Flow Through
2-1-1-1
tCycle
tKQ
IDD
tKQ
tCycle
IDD
5.5ns
3.2ns
330mA
8ns
10ns
190mA
6.0ns
3.5ns
310mA
8.5ns
10ns
190mA
6.6ns
3.8ns
275mA
10ns
10ns
190mA
10ns
4.5ns
190mA
12ns
15ns
140mA
Functional Description
Applications
The GS84018/32/36 is a 4,718,592 bit (4,194,304 bit for x32 version)
high performance synchronous SRAM with a 2 bit burst address
counter. Although of a type originally developed for Level 2 Cache
applications supporting high performance CPU’s, the device now
finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support. The GS84018/32/36
is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA
package.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
180Mhz - 100Mhz
3.3V VDD
3.3V & 2.5V I/O
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through / Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the
BGA, ) . Holding the FT mode pin/bump low places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
SCD Pipelined Reads
The GS84018/32/36 is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available.SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS84018/32/36 operates on a 3.3V power supply and all inputs/
outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ)
pins are used to de-couple output noise from the internal circuit.
Rev: 2.05 6/2000 1/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018 100 Pin TQFP Pinout
GS84018/32/36T/B-180/166/150/100
NC
NC
NC
VDDQ
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
FT
VDD
NC
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
NC
A6
E1
A7
E2
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
E3
BB
VDD
BA
256K x 18
Top View
VSS
CK
G
BW
GW
ADV
ADSP
ADSC
A8
A9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
NC
VSS
VDDQ
NC
NC
NC
A5
A4
A3
A2
A1
A0
NC
LBO
NC
NC
VSS
VDD
A11
NC
A10
A12
A13
A14
A16
A15
Rev: 2.05 6/2000 2/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84032 100 Pin TQFP Pinout
GS84018/32/36T/B-180/166/150/100
NC
DQC8
DQC7
VDDQ
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
NC
A6
E1
A7
E2
BC
BD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
E3
BB
VDD
BA
128K x 32
Top View
VSS
CK
G
BW
GW
ADV
ADSP
ADSC
A8
A9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
A5
A4
A3
A2
A1
A0
NC
LBO
NC
NC
VSS
VDD
A11
NC
A10
A12
A13
A14
A16
A15
Rev: 2.05 6/2000 3/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84036 100 Pin TQFP Pinout
GS84018/32/36T/B-180/166/150/100
DQC9
DQC8
DQC7
VDDQ
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
DQD9
A6
E1
A7
E2
BC
BD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
E3
BB
VDD
BA
128K x 36
Top View
VSS
CK
G
BW
GW
ADV
ADSP
ADSC
A8
A9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
A5
A4
A3
A2
A1
A0
NC
LBO
NC
NC
VSS
VDD
A11
NC
A10
A12
A13
A14
A16
A15
Rev: 2.05 6/2000 4/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018/32/36T/B-180/166/150/100
TQFP Pin Description
Pin Location Symbol Type Description
37, 36 A0, A1 I Address field LSB’s and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46,
47, 48, 49, 50
80 A17 I Address Inputs (x18 versions)
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
51, 80, 1, 30 NC No Connect (x32 Version)
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79
1, 2, 3, 6, 7
25, 28, 29, 30
87 BW I Byte Write. Writes all enabled bytes. Active Low.
93, 94 BA, BB I Byte Write Enable for DQA, DQB Data I/O’s. Active Low.
95, 96 BC, BD I
95, 96 NC - No Connect (x18 Version)
89 CK I Clock Input Signal. Active High.
88 GW I Global Write Enable. Writes all bytes. Active Low.
98, 92 E1, E3 I Chip Enable. Active Low.
97 E2 I Chip Enable. Active High.
86 G I Output Enable. Active Low.
83 ADV I Burst address counter advance enable. Active Low.
84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller). Active Low.
64 ZZ I Sleep Mode control. Active High.
14 FT I Flow Through or Pipeline mode. Active Low.
31 LBO I Linear Burst Order mode. Active Low.
15, 41, 65, 91 VDD I Core power supply.
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS I I/O and Core Ground.
4, 11, 20, 27, 54, 61, 70, 77 VDDQ I Output driver power supply.
16, 38, 39, 42, 43, 66 NC - No Connect.
A2-16 I Address Inputs
DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8
DQA9, DQB9,
DQC9, DQD9
DQA1-DQA9
DQB1-DQB9
NC - No Connect (x18 Version)
I/O Data Input and Output pins. (x32, x36 Version)
I/O Data Input and Output pins. (x36 Version)
I/O Data Input and Output pins. (x18 Version)
Byte Write Enable for DQC, DQD Data I/O’s. Active Low.
(x32, x36 Version)
Rev: 2.05 6/2000 5/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018 Pad Out
GS84018/32/36T/B-180/166/150/100
119 Bump BGA - Top View
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
VDDQ A6 A7 ADSP A8 A9 VDDQ
NC E2 A4 ADSC A15 E3 NC
NC A5 A3 VDD A14 A16 NC
DQB1 NC VSS NC VSS DQA9 NC
NC DQB2 VSS E1 VSS NC DQA8
VDDQ NC VSS G VSS DQA7 VDDQ
NC DQB3 BB ADV NC NC DQA6
DQB4 NC VSS GW VSS DQA5 NC
VDDQ VDD NC VDD NC VDD VDDQ
NC DQB5 VSS CK VSS NC DQA4
DQB6 NC NC NC BA DQA3 NC
M
N
P
R
T
U
VDDQ DQB7 VSS BW VSS NC VDDQ
DQB8 NC VSS A1 VSS DQA2 NC
NC DQB9 VSS A0 VSS NC DQA1
NC A2 LBO VDD FT A13 NC
NC A10 A11 NC A12 A17 ZZ
VDDQ NC NC NC NC NC VDDQ
Rev: 2.05 6/2000 6/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84032 Pad Out
GS84018/32/36T/B-180/166/150/100
119 Bump BGA - Top View
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
VDDQ A6 A7 ADSP A8 A9 VDDQ
NC E2 A4 ADSC A15 E3 NC
NC A5 A3 VDD A14 A16 NC
DQC4 NC VSS NC VSS NC DQB4
DQC3 DQC8 VSS E1 VSS DQB8 DQB3
VDDQ DQC7 VSS G VSS DQB7 VDDQ
DQC2 DQC6 BC ADV BB DQB6 DQB2
DQC1 DQC5 VSS GW VSS DQB5 DQB1
VDDQ VDD NC VDD NC VDD VDDQ
DQD1 DQD5 VSS CK VSS DQA5 DQA1
DQD2 DQD6 BD NC BA DQA6 DQA2
M
N
P
R
T
U
VDDQ DQD78 VSS BW VSS DQA7 VDDQ
DQD3 DQD8 VSS A1 VSS DQA8 DQA3
DQD4 NC VSS A0 VSS NC DQA4
NC A2 LBO VDD FT A13 NC
NC NC A10 A11 A12 NC ZZ
VDDQ NC NC NC NC NC VDDQ
Rev: 2.05 6/2000 7/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84036Pad Out
GS84018/32/36T/B-180/166/150/100
119 Bump BGA - Top View
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
VDDQ A6 A7 ADSP A8 A9 VDDQ
NC E2 A4 ADSC A15 E3 NC
NC A5 A3 VDD A14 A16 NC
DQC4 DQC9 VSS NC VSS DQB9 DQB4
DQC3 DQC8 VSS E1 VSS DQB8 DQB3
VDDQ DQC7 VSS G VSS DQB7 VDDQ
DQC2 DQC6 BC ADV BB DQB6 DQB2
DQC1 DQC5 VSS GW VSS DQB5 DQB1
VDDQ VDD NC VDD NC VDD VDDQ
DQD1 DQD5 VSS CK VSS DQA5 DQA1
DQD2 DQD6 BD NC BA DQA6 DQA2
M
N
P
R
T
U
VDDQ DQD78 VSS BW VSS DQA7 VDDQ
DQD3 DQD8 VSS A1 VSS DQA8 DQA3
DQD4 DQD9 VSS A0 VSS DQA9 DQA4
NC A2 LBO VDD FT A13 NC
NC NC A10 A11 A12 NC ZZ
VDDQ NC NC NC NC NC VDDQ
Rev: 2.05 6/2000 8/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
BGA Pin Description
Pin Location Symbol Type Description
N4, P4 A0, A1 I Address field LSB’s and Address Counter Preset Inputs.
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, R2, R6, T3, T5
T4 An Address Input (x32/36 Versions)
T2, T6 NC - No Connect (x32/36 Versions)
T2, T6 An I Address Input (x18 Version)
K7, K6, L7, L6, M6, N7, N6, P7
H7, H6, G7, G6, F6, E7, E6, D7
H1, H2, G1, G2, F2, E1, E2, D1
K1, K2, L1, L2, M2, N1, N2, P1
P6, D6, D2, P2
P6, D6, D2, P2 NC - No Connect (x32 Version)
L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/O’s. Active Low. ( x36 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
L5, G3 BA, BB I Byte Write Enable for DQA, DQB I/O’s. Active Low. ( x18 Version)
B1, C1, R1, T1, U2, J3, U3, D4, L4,
U4, J5, U5, U6, B7, C7, R7
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, B1, E1, F2, G1, H2, K1, L2, N2,
P1, G5, L3, T4
K4 CK I Clock Input Signal. Active High.
M4 BW I Byte Write. Writes all enabled bytes. Active Low.
H4 GW I Global Write Enable. Writes all bytes. Active Low.
E4, B6 E1, E3 I Chip Enable. Active Low.
B2 E2 I Chip Enable. Active High.
F4 G I Output Enable. Active Low.
G4 ADV I Burst address counter advance enable. Active Low.
A4, B4 ADSP, ADSC I Address Strobe (Processor, Cache Controller). Active Low.
T7 ZZ I Sleep Mode control. Active High.
R5 FT I Flow Through or Pipeline mode. Active Low.
R3 LBO I Linear Burst Order mode. Active Low.
J2, C4, J4, R4, J6 VDD I Core power supply.
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
GS84018/32/36T/B-180/166/150/100
An I Address Inputs
DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8
DQA9, DQB9,
DQC9, DQD9
DQA1-DQA9
DQB1-DQB9
NC - No Connect
NC - No Connect (x18 Version)
VSS I I/O and Core Ground.
VDDQ I Output driver power supply.
I/O Data Input and Output pins. (x32/36 Versions)
I/O Data Input and Output pins. (x36 Version)
I/O Data Input and Output pins. (x18 Version)
Rev: 2.05 6/2000 9/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018/32/36 Block Diagram
A0-An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
Register
D Q
A0
A1
D0
D1
Counter
Load
Register
D Q
Q0
Q1
GS84018/32/36T/B-180/166/150/100
A0
A1
A
Memory
Array
Q D
BB
BC
BD
E1
E3
E2
FT
G
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
36
4
DQ
Register
36
Register
DQ
ZZ
Note: Only x36 version shown for simplicity.
Power Down
Control
1
DQx0-DQx9
Rev: 2.05 6/2000 10/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018/32/36T/B-180/166/150/100
Linear Burst Sequence
I
Mode Pin Functions
Mode Name Pin Name State Function
Burst Order Control LBO
Output Register Control FT
Power Down Control ZZ
Note:
There are pull up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note: The burst counter wraps to initial state on the 5th clock.
L Linear Burst
H or NC Interleaved Burst
L Flow Through
H or NC Pipeline
L or NC Active
H
Standby, IDD = I
nterleaved Burst Sequence
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
SB
A[1:0] A[1:0] A[1:0] A[1:0]
Byte Write Truth Table
Function GW BW BA BB BC BD Notes
Read H H X X X X 1
Read H L H H H H 1
Write byte A H L L H H H 2, 3
Write byte B H L H L H H 2, 3
Write byte C H L H H L H 2, 3, 4
Write byte D H L H H H L 2, 3, 4
Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 2.05 6/2000 11/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018/32/36T/B-180/166/150/100
Synchronous Truth Table
State
Operation Address Used
Deselect Cycle, Power Down None X H X X L X X High-Z
Deselect Cycle, Power Down None X L F L X X X High-Z
Deselect Cycle, Power Down None X L F H L X X High-Z
Read Cycle, Begin Burst External R L T L X X X Q
Read Cycle, Begin Burst External R L T H L X F Q
Write Cycle, Begin Burst External W L T H L X T D
Read Cycle, Continue Burst Next CR X X H H L F Q
Read Cycle, Continue Burst Next CR H X X H L F Q
Write Cycle, Continue Burst Next CW X X H H L T D
Write Cycle, Continue Burst Next CW H X X H L T D
Read Cycle, Suspend Burst Current X X H H H F Q
Read Cycle, Suspend Burst Current H X X H H F Q
Write Cycle, Suspend Burst Current X X H H H T D
Write Cycle, Suspend Burst Current H X X H H T D
Note:
1. X = Don’t Care, H = High, L = Low.
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Diagram
5
Key
E1
E
2
ADSP ADSC ADV
W
3
DQ
4
Rev: 2.05 6/2000 12/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018/32/36T/B-180/166/150/100
Simplified State Diagram
X
Deselect
W R
W
X
Simple Synchronous OperationSimple Burst Synchronous Operation
First Write
W R
Burst Write
CW CR
R
CR
R
CR
R
First Read
Burst Read
X
CRCW
XX
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
Rev: 2.05 6/2000 13/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
Simplified State Diagram with G
GS84018/32/36T/B-180/166/150/100
X
Deselect
W R
W
X
X
First Write
W
Burst Write
CW CR
R
CR
R
CR
W
CW
W
CW
R
First Read
R
Burst Read
X
CRCW
X
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 2.05 6/2000 14/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
Absolute Maximum Ratings
(All voltages reference to V
SS
)
Symbol Description Value Unit
GS84018/32/36T/B-180/166/150/100
V
T
T
V
DDQ
V
V
V
I
I
OUT
P
STG
BIAS
DD
CK
I/O
IN
IN
D
Voltage on VDD Pins -0.5 to 4.6 V
Voltage in V
Pins -0.5 to V
DDQ
DD
V
Voltage on Clock Input Pin -0.5 to 6 V
Voltage on I/O Pins -0.5 to V
Voltage on Other Input Pins -0.5 to V
+0.5 (≤ 4.6 V max.) V
DDQ
+0.5 (≤ 4.6 V max.) V
DD
Input Current on Any Pin +/- 20 mA
Output Current on Any I/O Pin +/- 20 mA
Package Power Dissipation 1.5 W
Storage Temperature -55 to 125
Temperature Under Bias -55 to 125
o
o
C
C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter Symbol Min. Typ. Max. Unit Notes
V
V
DDQ
V
V
T
T
DD
3.135 3.3 3.6 V
2.375 2.5
IH
IL
A
A
1.7 ---
-0.3 --- 0.8 V 2
0 25 70 °C 3
-40 25 85 °C 3
V
DD
VDD+0.3
V 1
V 2
Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V ≤ VDDQ ≤ 2.375V (i.e. 2.5V I/O)
and 3.6V ≤ VDDQ ≤ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be -2V > Vi < VDD+2V with a pulse width not to exceed 20% tKC.
Rev: 2.05 6/2000 15/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018/32/36T/B-180/166/150/100
Undershoot Measurement and Timing Overshoot Measurement and Timing
V
IH
VDD+-2.0V
V
SS
50%
20% tKC
50%
VSS-2.0V
20% tKC
V
DD
V
IL
Capacitance
(TA=25oC, f=1MHZ, VDD=3.3V)
Parameter Symbol Test conditions Typ. Max. Unit
Control Input Capacitance
Input Capacitance
Output Capacitance
Note: This parameter is sample tested.
C
C
C
OUT
I
IN
VDD=3.3V
VIN=0V
V
=0V
OUT
3 4 pF
4 5 pF
6 7 pF
Package Thermal Characteristics
Rating Layer Board Symbol TQFP Max BGA Max Unit Notes
Junction to Ambient (at 200 lfm) single
Junction to Ambient (at 200 lfm) four
Junction to Case (TOP)
Notes:
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
4. For x18 configuration, consult factory.
R
R
R
ΘJA
ΘJA
ΘJC
40 38 °C/W 1,2,4
24 21 °C/W 1,2,4
9 5 °C/W 3,4
Rev: 2.05 6/2000 16/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018/32/36T/B-180/166/150/100
AC Test Conditions
Parameter Conditions
Input high level 2.3V
Input low level 0.2V
Input slew rate 1V/ns
Input reference level 1.25V
Output reference level 1.25V
Output load Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, t
4. Device is deselected as defined by the Truth Table.
DQ
and t
OLZ
Output Load 1
OHZ
.
Output Load 2
2.5V
50Ω
30pF
VT=1.25V
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins)
ZZ Input Current
Mode Pin Input Current
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
I
I
INZZ
I
INM
I
V
V
V
IL
OL
OH
OH
OL
V
V
DD
0V
V
DD
0V
Output Disable,
V
OUT
I
= - 4mA, V
OH
I
= - 4mA, V
OH
= 0 to V
IN
≥
≤ V
≥
≤ V
= 0 to V
I
OL
V
IN
IN
V
IN
IN
DDQ
DDQ
= 4mA
DD
≥
VIH
≤ V
≥
VIL
≤ V
DD
=2.375V
=3.135V
IH
IL
*
-1uA 1uA
-1uA
-1uA
300uA
-300uA
-1uA
-1uA 1uA
1.7V
2.4V
1uA
1uA
1uA
0.4V
DQ
5pF
225Ω
*
225Ω
Rev: 2.05 6/2000 17/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
Operating Currents
Parameter Test Conditions Symbol
IDD
Pipeline
IDD
Flow-Thru
ISB
Pipeline
ISB
Flow-Thru
IDD
Pipeline
IDD
Flow-Thru
Operating
Current
Standby
Current
Deselect
Current
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
ZZ ≥ VDD - 0.2V
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
GS84018/32/36T/B-180/166/150/100
-180 -166 -150 -100
0 to
-40 to
70°C
330mA 340mA 310mA 320mA 275mA 285mA 190mA 200mA
190mA 200mA 190mA 200mA 190mA 200mA 140mA 150mA
30mA 40mA 30mA 40mA 30mA 40mA 30mA 40mA
30mA 40mA 30mA 40mA 30mA 40mA 30mA 40mA
120mA 130mA 110mA 120mA 105mA 115mA 80mA 90mA
80mA 90mA 80mA 90mA 80mA 90mA 65mA 75mA
85°C
0 to
70°C
-40 to
85°C
0 to
70°C
-40 to
85°C
0 to
70°C
-40 to
85°C
Rev: 2.05 6/2000 18/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
AC Electrical Characteristics
GS84018/32/36T/B-180/166/150/100
Pipeline
Flow-
Thru
Parameter Symbol
-180 -166 -150 -100
Min Max Min Max Min Max Min Max
Clock Cycle Time tKC 5.5 --- 6.0 --- 6.7 --- 10 --- ns
Clock to Output Valid tKQ --- 3.2 --- 3.5 --- 3.8 --- 4.5 ns
Clock to Output Invalid tKQX 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns
Clock to Output in Low-Z
Clock Cycle Time tKC 10.0 --- 10.0 --- 10.0 --- 15.0 --- ns
Clock to Output Valid tKQ --- 8.0 --- 8.5 --- 10.0 --- 12.0 ns
Clock to Output Invalid tKQX 3.0 --- 3.0 --- 3.0 --- 3.0 --- ns
Clock to Output in Low-Z
Clock HIGH Time tKH 1.3 --- 1.3 --- 1.5 --- 2 --- ns
Clock LOW Time tKL 1.5 --- 1.5 --- 1.7 --- 2.2 --- ns
Clock to Output in High-Z
G to Output Valid tOE --- 3.2 --- 3.5 --- 3.8 --- 5 ns
G to output in Low-Z
G to output in High-Z
Setup time tS 1.5 --- 1.5 --- 1.5 --- 2.0 --- ns
Hold time tH 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns
ZZ setup time
ZZ hold time
ZZ recovery tZZR 20 --- 20 --- 20 --- 20 --- ns
tLZ
tLZ
tHZ
tOLZ
tOHZ
tZZS
tZZH
1
1
1
1.5 --- 1.5 --- 1.5 --- 1.5 --- ns
3.0 --- 3.0 --- 3.0 --- 3.0 --- ns
1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns
1
1
2
2
0 --- 0 --- 0 --- 0 --- ns
--- 3.2 --- 3.5 --- 3.8 --- 5 ns
5 --- 5 --- 5 --- 5 --- ns
1 --- 1 --- 1 --- 1 --- ns
Unit
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 2.05 6/2000 19/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
Write Cycle Timing
GS84018/32/36T/B-180/166/150/100
CK
ADSP
ADSC
ADV
A0-An
GW
BW
BA - BD
Single Write
tH
tS
tH
tS
WR1
tS
tH
Burst Write
ADSP is blocked by E1 inactive
tKC
tKL
tKH
tH
tS
tH
tS
ADV must be inactive for ADSP Write
WR2 WR3
tS tH
tH
tS
tS
tH
WR1 WR2 WR3
WR1
WR2 WR3
E1 masks ADSP
Write
ADSC initiated write
Deselected
E1
tH
tS
Deselected with E2
E2
tS tH
E2 and E3 only sampled with ADSP or ADSC
E3
G
tS
tH
DQA - DQD
Hi-Z
D1a
Rev: 2.05 6/2000 20/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
Write specified byte for 2a and all bytes for 2b, 2c& 2d
D2a D2b
D2c D2d D3a
GS84018/32/36T/B-180/166/150/100
Flow Through Read Cycle Timing
CK
ADSP
ADSC
ADV
A0-An
GW
BW
BA - BD
Single Read
tS
tH
tS
tS
tH
RD1
tS
tS
tH
tS
tKL
tKH
tS
tH
tH
RD2 RD3
Burst Read
ADSP is blocked by E1 inactive
tKC
Suspend Burst
E1 masks ADSP
ADSC initiated read
Suspend Burst
tH
tH
E1
tH
tS
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
tS
tH
E3
tOE
tOHZ
G
DQA-DQD
tOLZ
Hi-Z
Q1a
tLZ
tKQ
Q2a
tKQX
Q2cQ2b
Q2d
Rev: 2.05 6/2000 21/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
tKQX
Q3a
tHZ
Flow Through Read-Write Cycle Timing
Single Read
CK
tH
tS
ADSP
tKH
tKL
Single Write
tKC
tS
tH
GS84018/32/36T/B-180/166/150/100
Burst Read
ADSP is blocked by E inactive
ADSC initiated read
ADSC
ADV
A0-An
GW
BW
BA - BD
E1
E2
E3
tS
tS
tS
tS
RD1
tH
tH
tH
tH
tOE
tS
tS
tS
tH
WR1
tH
tH
tS
WR1
E2 and E3 only sampled with ADSP and ADSC
tOHZ
RD2
tH
E1 masks ADSP
Deselected with E3
G
tS
tKQ
Q1a D1a
DQA - DQD
Hi-Z
Rev: 2.05 6/2000 22/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
tH
Q2a
Burst wrap around to its initial state
Q2b Q2c
Q2d
Q2a
Pipelined SCD Read Cycle Timing
GS84018/32/36T/B-180/166/150/100
CK
ADSP
ADSC
ADV
A0-A17
GW
BW
BWA - BWD
Single Read
tH
tS
tH
tS
RD1
tS
tS
tS
tH
tS
RD2
tKH
tH
tKL
Burst Read
tKC
ADSP is blocked by E1 inactive
ADSC initiated read
Suspend Burst
RD3
tH
tH
tH
tS
E1 masks ADSP
E1
tH
tS
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
tS
tH
E3
tOE
G
tOHZ
tKQX
Q2a
Q2b
Q2c
DQA - DQD
Hi-Z
tOLZ
Q1a
tLZ
tKQ
Q2d
tKQX
Q3a
tHZ
Rev: 2.05 6/2000 23/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018/32/36T/B-180/166/150/100
Pipelined SCD Read - Write Cycle Timing
CK
ADSP
ADSC
ADV
A0-An
GW
BW
BWA - BWD
tS
tS
tH
RD1
Single Read
tH
tS tH
tS
tS
tH
tKH
tKL
Single Write
tKC
tS
WR1
tH
tS
WR1
ADSP is blocked by E inactive
tH
ADSC initiated read
RD2
tH
Burst Read
E1
E2
E3
G
DQA - DQD
Hi-Z
tS
tS
tS
tH
tH
tH
E2 and E3 only sampled with ADSP and ADSC
tOE tOHZ
tS
tKQ
Q1a
tH
D1a Q2a
E1 masks ADSP
Deselected with E3
Q2b Q2c
Q2d
Rev: 2.05 6/2000 24/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018/32/36T/B-180/166/150/100
Sleep Mode Timing Diagram
~
CK
ADSP
ADSC
ZZ
tS
tH
tKC
tKH
tKL
tZZS
~
~
~
~
~
~
~
~
~
~
~
Snooze
tZZH
tZZR
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in
a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in
transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to
manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised
to avoid excessive bus contention.
Rev: 2.05 6/2000 25/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS 84018/32/36 Output Driver Characteristics
I Out (mA)
VDDQ
60
GS84018/32/36T/B-180/166/150/100
-20
-40
40
Pull Down Drivers
20
I Out
0
VOut
VSS
Pull Up Drivers
-60
-80
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD LD 3.3V PD LD 3.1V PD LD 3.1V PU LD 3.3V PU LD 3.6V PU LD
Rev: 2.05 6/2000 26/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
TQFP Package Drawing
D
GS84018/32/36T/B-180/166/150/100
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
b Lead Width 0.20 0.30 0.40
c Lead Thickness 0.09 0.20
D Terminal Dimension 21.9 22.0 22.1
D1 Package Body 19.9 20.0 20.1
E Terminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
e Lead Pitch 0.65
L Foot Length 0.45 0.60 0.75
L1 Lead Length 1.00
Y Coplanarity 0.10
θ Lead Angle 0° 7°
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion
L1
A1
θ
L
c
Pin 1
e
D1
b
A2
Y
E1
E
Rev: 2.05 6/2000 27/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
Package Dimensions - 119 Pin BGA
GS84018/32/36T/B-180/166/150/100
Pin 1
Corner
A
1234567
A
G
P
B
N
Top View
D
S
R
Bottom View
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Package Dimensions - 119 Pin BGA
Symbol Description Min. Nom. Max
A Width 13.8 14.0 14.2
B Length 21.8 22.0 22.2
C Package Height (including ball) - 2.40
D Ball Size 0.60 0.75 0.90
E Ball Height 0.50 0.60 0.70
F Package Height (excluding balls) 1.46 1.70
G Width between Balls 1.27
K Package Height above board 0.80 0.90 1.00
N Cut-out Package Width 12.00
K
E
F
C T
P Foot Length 19.50
R Width of package between balls 7.62
S Length of package between balls 20.32
T Variance of Ball Height 0.15
Unit: mm
Side View
Rev: 2.05 6/2000 28/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018/32/36T/B-180/166/150/100
Ordering Information for GSI Synchronous Burst RAMS
2
Org
Part Number
1
Type Package
(Mhz/
ns)
256K x 18 GS84018T-180 Pipeline/Flow Through TQFP 180/8 C
256K x 18 GS84018T-166 Pipeline/Flow Through TQFP 166/8.5 C
256K x 18 GS84018T-150 Pipeline/Flow Through TQFP 150/10 C
256K x 18 GS84018T-100 Pipeline/Flow Through TQFP 100/12 C
128K x 32 GS84032T-180 Pipeline/Flow Through TQFP 180/8 C
128K x 32 GS84032T-166 Pipeline/Flow Through TQFP 166/8.5 C
128K x 32 GS84032T-150 Pipeline/Flow Through TQFP 150/10 C
128K x 32 GS84032T-100 Pipeline/Flow Through TQFP 100/12 C
128K x 36 GS84036T-180 Pipeline/Flow Through TQFP 180/8 C
128K x 36 GS84036T-166 Pipeline/Flow Through TQFP 166/8.5 C
128K x 36 GS84036T-150 Pipeline/Flow Through TQFP 150/10 C
128K x 36 GS84036T-100 Pipeline/Flow Through TQFP 100/12 C
256K x 18 GS84018T-180I Pipeline/Flow Through TQFP 180/8 I Not Available
256K x 18 GS84018T-166I Pipeline/Flow Through TQFP 166/8.5 I
256K x 18 GS84018T-150I Pipeline/Flow Through TQFP 150/10 I
256K x 18 GS84018T-100I Pipeline/Flow Through TQFP 100/12 I
128K x 32 GS84032T-180I Pipeline/Flow Through TQFP 180/8 I Not Available
128K x 32 GS84032T-166I Pipeline/Flow Through TQFP 166/8.5 I
128K x 32 GS84032T-150I Pipeline/Flow Through TQFP 150/10 I
128K x 32 GS84032T-100I Pipeline/Flow Through TQFP 100/12 I
128K x 36 GS84036T-180I Pipeline/Flow Through TQFP 180/8 I Not Available
128K x 36 GS84036T-166I Pipeline/Flow Through TQFP 166/8.5 I
128K x 36 GS84036T-150I Pipeline/Flow Through TQFP 150/10 I
128K x 36 GS84036T-100I Pipeline/Flow Through TQFP 100/12 I
256K x 18 GS84018B-180 Pipeline/Flow Through BGA 180/8 C
256K x 18 GS84018B-166 Pipeline/Flow Through BGA 166/8.5 C
256K x 18 GS84018B-150 Pipeline/Flow Through BGA 150/10 C
256K x 18 GS84018B-100 Pipeline/Flow Through BGA 100/12 C
128K x 32 GS84032B-180 Pipeline/Flow Through BGA 180/8 C
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032T-7.5T.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode.
Each device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Speed
3
T
A
Status
Rev: 2.05 6/2000 29/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
GS84018/32/36T/B-180/166/150/100
2
Org
Part Number
1
Type Package
(Mhz/
ns)
128K x 32 GS84032B-166 Pipeline/Flow Through BGA 166/8.5 C
128K x 32 GS84032B-150 Pipeline/Flow Through BGA 150/10 C
128K x 32 GS84032B-100 Pipeline/Flow Through BGA 100/12 C
128K x 36 GS84036B-180 Pipeline/Flow Through BGA 180/8 C
128K x 36 GS84036B-166 Pipeline/Flow Through BGA 166/8.5 C
128K x 36 GS84036B-150 Pipeline/Flow Through BGA 150/10 C
128K x 36 GS84036B-100 Pipeline/Flow Through BGA 100/12 C
256K x 18 GS84018B-180I Pipeline/Flow Through BGA 180/8 I Not Available
256K x 18 GS84018B-166I Pipeline/Flow Through BGA 166/8.5 I
256K x 18 GS84018B-150I Pipeline/Flow Through BGA 150/10 I
256K x 18 GS84018B-100I Pipeline/Flow Through BGA 100/12 I
128K x 32 GS84032B-180I Pipeline/Flow Through BGA 180/8 I Not Available
128K x 32 GS84032B-166I Pipeline/Flow Through BGA 166/8.5 I
128K x 32 GS84032B-150I Pipeline/Flow Through BGA 150/10 I
128K x 32 GS84032B-100I Pipeline/Flow Through BGA 100/12 I
128K x 36 GS84036B-180I Pipeline/Flow Through BGA 180/8 I Not Available
128K x 36 GS84036B-166I Pipeline/Flow Through BGA 166/8.5 I
128K x 36 GS84036B-150I Pipeline/Flow Through BGA 150/10 I
128K x 36 GS84036B-100I Pipeline/Flow Through BGA 100/12 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032T-7.5T.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode.
Each device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Speed
3
T
A
Status
Rev: 2.05 6/2000 30/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
Revision History
GS84018/32/36T/B-180/166/150/100
Rev. Code: Old;
New
GS84018/32/36 Rev 1.02c 5/1999;
GS84018/32/36 2.00 8/1999D
GS84018/32/362.00 8/
1999;GS84018/32/362.01 9/1999E
GS84018/32/362.01 9/
1999E;GS84018/32/362.02
GS84018/32/362.0210-11/
1999;GS84018/32/362.032/2000G
GS84018/32/362.032/2000G;
GS84018_r2_04
Types of Changes
Format or Content
Format/Typos
Content
Format/Typos
Content
Format
Content
Page /Revisions;Reason
• Document/Continued changing to new format.
• Added Fine Pitch BGA Package.
•
• Took “E” out of 840HE...in Core and Interface Voltages.
• Pin outs/New small caps format.
• Timing Diagrams/New format.
• Block Diagrams/New small caps format.
• Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to DQB3.
• Pin Description/Rearranged Address Inputs to match order on TQFP Pinout.
• TQFP Package Diagram/Corrected Dimension D Max from 20.1 to 22.1.
•
• Took out Fine Pitch BGA Package. Package change in progress.
• New GSI Logo
• Took “Pin” out of heading for consistency.
• Updated ADSC in timing diagrams on pages 22 and 24
• Pin description table updated
84018_r2_04; 84018_r2_05 Content
• Updated BGA pin description table to meet JEDEC standard
Rev: 2.05 6/2000 31/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com .
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