GSI GS832272C-250, GS832272C-225, GS832272C-200, GS832272C-166, GS832272C-150 Datasheet

Rev: 1.00 10/2001 1/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

2M x 18, 1M x 36, 512K x 72

36Mb S/DCD Sync Burst SRAMs

250 MHz–133MHz

2.5 V or 3.3 V V

DD

2.5 V or 3.3 V I/O

119- and 209-Pin BGA
Commercial Temp
Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip read parity checking; even or odd selectable

• ZQ mode pin for user-selectable high/low output drive

• On-chip parity encoding and error detection

• 2.5 V or 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 209-bump BGA package

Functional Description

Applications

The GS832218/36/72 is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge­triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.

SCD and DCD Pipelined Reads

The GS832218/36/72 is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.

Core and Interface Voltages

The GS832218/36/72 operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(V

DDQ

) pins are used to decouple output noise from the internal

circuits and are 3.3 V and 2.5 V compatible.

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

t

KQ

tCycle

2.3

4.0

2.5

4.4

3.0

5.0

3.5

6.0

3.8

6.6

4.0

7.5nsns

3.3 V

Curr (x18)
Curr (x36)
Curr (x72)

365
560
660

335
510
600

305
460
540

265
400
460

245
370
430

215
330
380

mA
mA
mA

2.5 V

Curr (x18)
Curr (x36)
Curr (x72)

360
550
640

330
500
590

305
460
530

260
390
450

240
360
420

215
330
370

mA
mA
mA

Flow

Through

2-1-1-1

t

KQ

tCycle

6.0

7.0

6.5

7.5

7.5

8.5

8.51010101115ns
ns

3.3 V

Curr (x18)
Curr (x36)
Curr (x72)

235
300
350

230
300
350

210
270
300

200
270
300

195
270
300

150
200
220

mA
mA
mA

2.5 V

Curr (x18)
Curr (x36)
Curr (x72)

235
300
340

230
300
340

210
270
300

200
270
300

195
270
300

145
190
220

mA
mA
mA

Rev: 1.00 10/2001 2/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832272B Pad Out

209-Bump BGA—Top View

1 2 3 4 5 6 7 8 9 10 11

A DQG5 DQG1 A15 E2 ADSP ADSC ADV E3 A17 DQB1 DQB5 A

B DQG6 DQG2 BC BG NC BW A16 BB BF DQB2 DQB6 B

C DQG7 DQG3 BH BD NC E1 NC BE BA DQB3 DQB7 C

D DQG8 DQG4

V

SS

NC NC G GW NC

V

SS

DQB4 DQB8 D

E DQPG9 DQPC9

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

DQPF9 DQPB9 E

F DQC4 DQC8

V

SS

V

SS

V

SS

ZQ

V

SS

V

SS

V

SS

DQF8 DQF4 F

G DQC3 DQC7

V

DDQ

V

DDQ

V

DD

MCH

V

DD

V

DDQ

V

DDQ

DQF7 DQF3 G

H DQC2 DQC6

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

DQF6 DQF2 H

J DQC1 DQC5

V

DDQ

V

DDQ

V

DD

MCL

V

DD

V

DDQ

V

DDQ

DQF5 DQF1 J

K NC NC CK NC

V

SS

MCL

V

SS

NC NC NC NC K

L DQH1 DQH5

V

DDQ

V

DDQ

V

DD

FT

V

DD

V

DDQ

V

DDQ

DQA5 DQA1 L

M DQH2 DQH6

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

DQA6 DQA2 M

N DQH3 DQH7

V

DDQ

V

DDQ

V

DD

SCD

V

DD

V

DDQ

V

DDQ

DQA7 DQA3 N

P DQH4 DQH8

V

SS

V

SS

V

SS

ZZ

V

SS

V

SS

V

SS

DQA8 DQA4 P

R DQPD9 DQPH9

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

DQPA9 DQPE9 R

T DQD8 DQD4

V

SS

NC NC LBO NC NC

V

SS

DQE4 DQE8 T

U DQD7 DQD3 NC A14 A13 A12 A11 A10 A18 DQE3 DQE7 U

V DQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 DQE2 DQE6 V

W DQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK DQE1 DQE5 W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.00 10/2001 3/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832236C Pad Out

209-Bump BGA—Top View

1 2 3 4 5 6 7 8 9 10 11

A NC NC A15 E2 ADSP ADSC ADV E3 A17 DQB1 DQB5 A

B NC NC BC NC A19 BW A16 BB NC DQB2 DQB6 B

C NC NC NC BD NC E1 NC NC BA DQB3 DQB7 C

D NC NC

V

SS

NC NC G GW NC

V

SS

DQB4 DQB8 D

E NC DQPC9

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

NC DQPB9 E

F DQC4 DQC8

V

SS

V

SS

V

SS

ZQ

V

SS

V

SS

V

SS

NC NC F

G DQC3 DQC7

V

DDQ

V

DDQ

V

DD

MCH

V

DD

V

DDQ

V

DDQ

NC NC G

H DQC2 DQC6

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

NC NC H

J DQC1 DQC5

V

DDQ

V

DDQ

V

DD

MCL

V

DD

V

DDQ

V

DDQ

NC NC J

K NC NC CK NC

V

SS

MCL

V

SS

NC NC NC NC K

L NC NC

V

DDQ

V

DDQ

V

DD

FT

V

DD

V

DDQ

V

DDQ

DQA5 DQA1 L

M NC NC

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

DQA6 DQA2 M

N NC NC

V

DDQ

V

DDQ

V

DD

SCD

V

DD

V

DDQ

V

DDQ

DQA7 DQA3 N

P NC NC

V

SS

V

SS

V

SS

ZZ

V

SS

V

SS

V

SS

DQA8 DQA4 P

R DQPD9 NC

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

DQPA9 NC R

T DQD8 DQD4

V

SS

NC NC LBO NC NC

V

SS

NC NC T

U DQD7 DQD3 NC A14 A13 A12 A11 A10 A18 NC NC U

V DQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 NC NC V

W DQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK NC NC W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.00 10/2001 4/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832218C Pad Out

209-Bump BGA—Top View

1 2 3 4 5 6 7 8 9 10 11

A NC NC A15 E2 ADSP ADSC ADV E3 A17 NC NC A

B NC NC BB NC A19 BW A16 NC NC NC NC B

C NC NC NC NC NC E1 A20 NC BA NC NC C

D NC NC

V

SS

NC NC G GW NC

V

SS

NC NC D

E NC DQPB9

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

NC NC E

F DQB4 DQB8

V

SS

V

SS

V

SS

ZQ

V

SS

V

SS

V

SS

NC NC F

G DQB3 DQB7

V

DDQ

V

DDQ

V

DD

MCH

V

DD

V

DDQ

V

DDQ

NC NC G

H DQB2 DQB6

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

NC NC H

J DQB1 DQB5

V

DDQ

V

DDQ

V

DD

MCL

V

DD

V

DDQ

V

DDQ

NC NC J

K NC NC CK NC

V

SS

MCL

V

SS

NC NC NC NC K

L NC NC

V

DDQ

V

DDQ

V

DD

FT

V

DD

V

DDQ

V

DDQ

DQA5 DQA1 L

M NC NC

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

DQA6 DQA2 M

N NC NC

V

DDQ

V

DDQ

V

DD

SCD

V

DD

V

DDQ

V

DDQ

DQA7 DQA3 N

P NC NC

V

SS

V

SS

V

SS

ZZ

V

SS

V

SS

V

SS

DQA8 DQA4 P

R NC NC

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

DQPA9 NC R

T NC NC

V

SS

NC NC LBO NC NC

V

SS

NC NC T

U NC NC NC A14 A13 A12 A11 A10 A18 NC NC U

V NC NC A9 A8 A7 A1 A6 A5 A4 NC NC V

W NC NC TMS TDI A3 A0 A2 TDO TCK NC NC W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.00 10/2001 5/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832218/36/72 209-Bump BGA Pin Description

Pin Location Symbol Type Description

W6, V6 A0, A1 I Address field LSBs and Address Counter Preset Inputs.

W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6,

U5, U4, A3, B7, A9, U9

An I Address Inputs

B5 A19 I Address Inputs (x36/x18 Versions)
C7 A20 I Address Inputs (x18 Version)

L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, V2, U2, T2, W1, V1, U1, T1, R1

W10, V10, U10, T10, W11, V11, U11, T11, R11

J11, H11, G11, F11, J10, H10, G10, F10, E10

A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2

DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
DQE1–DQE9
DQF1–DQF9
DQG1–DQG9
DQH1–DQH9

I/O Data Input and Output pins (x72 Version)

L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, V2, U2, T2, W1, V1, U1, T1, R1

DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9

I/O Data Input and Output pins (x36 Version)

L11, M11, N11, P11, L10, M10, N10, P10, R10

J1, H1, G1, F1, J2, H2, G2, F2, E2

DQA1–DQA9
DQB1–DQB9

I/O Data Input and Output pins (x18 Version)

C9, B8

BA, BB

I Byte Write Enable for DQA, DQB I/Os; active low

B3, C4

BC,BD

I

Byte Write Enable for DQC, DQD I/Os; active low

(x72/x36 Versions)

C8, B9, B4, C3

BE, BF, BG,BH

I

Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

(x72 Version)
B5 NC — No Connect (x72 Version)
C7 NC — No Connect (x72/x36 Versions)

W10, V10, U10, T10, W11, V11, U11, T11, R11

J11, H11, G11, F11, J10, H10, G10, F10, E10

A2, B2, C2, D2, A1, B1, C1, D1, E1

L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9,

B4, C3

NC — No Connect (x36/x18 Versions)

B3, C4 NC — No Connect (x18 Version)

C5, D4, D5, D8, K1, K2, K4, K8, K9, K10, K11,

T4, T5, T7, T8, U3

NC — No Connect

K3 CK I Clock Input Signal; active high
D7

GW

I Global Write Enable—Writes all bytes; active low

C6

E1

I Chip Enable; active low

A8

E3

I Chip Enable; active low

A4

E2

I Chip Enable; active high

Rev: 1.00 10/2001 6/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

D6

G

I Output Enable; active low

A7

ADV

I Burst address counter advance enable; active low

A5, A6

ADSP, ADSC

I Address Strobe (Processor, Cache Controller); active low

P6

ZZ

I Sleep Mode control; active high

L6

FT

I Flow Through or Pipeline mode; active low

T6

LBO

I Linear Burst Order mode; active low

N6

SCD

I Single Cycle Deselect/Dual Cycle Deselect Mode Control

G6

MCH

I Must Connect High

H6, J6, K6, M6

MCL

Must Connect Low

B6

BW

I Byte Enable; active low

F6

ZQ

I

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

W3

TMS

I Scan Test Mode Select

W4

TDI

I Scan Test Data In

W8

TDO

O Scan Test Data Out

W9

TCK

I Scan Test Clock

E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,

R6, R7

V

DD

I Core power supply

D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,

H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,

P4, P5, P7, P8, P9, T3, T9

V

SS

I I/O and Core Ground

E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9,
L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9

V

DDQ

I Output driver power supply

GS832218/36/72 209-Bump BGA Pin Description

Pin Location Symbol Type Description

Rev: 1.00 10/2001 7/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832236B Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

V

DDQ

A6 A7 ADSP A8 A9

V

DDQ

A

B NC A18 A4 ADSC A15 A17 NC B

C NC A5 A3

V

DD

A14 A16 NC C

D DQC4 DQPC9

V

SS

ZQ

V

SS

DQPB9 DQB4 D

E DQC3 DQC8

V

SS

E1

V

SS

DQB8 DQB3 E

F

V

DDQ

DQC7

V

SS

G

V

SS

DQB7

V

DDQ

F

G DQC2 DQC6 BC ADV BB DQB6 DQB2 G

H DQC1 DQC5

V

SS

GW

V

SS

DQB5 DQB1 H

J

V

DDQ

V

DD

NC

V

DD

NC

V

DD

V

DDQ

J

K DQD1 DQD5

V

SS

CK

V

SS

DQA5 DQA4 K

L DQD2 DQD6 BD SCD BA DQA6 DQA3 L

M

V

DDQ

DQD7

V

SS

BW

V

SS

DQA7

V

DDQ

M

N DQD3 DQD8

V

SS

A1

V

SS

DQA8 DQA2 N

P DQD4 DQPD9

V

SS

A0

V

SS

DQPA9 DQA1 P

R NC A2 LBO

V

DD

FT A13 NC R

T NC NC A10 A11 A12 A19 ZZ T

U

V

DDQ

TMS TDI TCK TDO NC

V

DDQ

U

7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch

Rev: 1.00 10/2001 8/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832218B Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

V

DDQ

A6 A7 ADSP A8 A9

V

DDQ

A

B NC A18 A4 ADSC A15 A17 NC B

C NC A5 A3

V

DD

A14 A16 NC C

D DQB1 NC

V

SS

ZQ

V

SS

DQPA9 NC D

E NC DQB2

V

SS

E1

V

SS

NC DQA8 E

F

V

DDQ

NC

V

SS

G

V

SS

DQA7

V

DDQ

F

G NC DQB3 BB ADV NC NC DQA6 G

H DQB4 NC

V

SS

GW

V

SS

DQA5 NC H

J

V

DDQ

V

DD

NC

V

DD

NC

V

DD

V

DDQ

J

K NC DQB5

V

SS

CK

V

SS

NC DQA4 K

L DQB6 NC NC SCD BA DQA3 NC L

M

V

DDQ

DQB7

V

SS

BW

V

SS

NC

V

DDQ

M

N DQB8 NC

V

SS

A1

V

SS

DQA2 NC N

P NC DQPB9

V

SS

A0

V

SS

NC DQA1 P

R NC A2 LBO

V

DD

FT A13 NC R

T NC A10 A11 A20 A12 A19 ZZ T

U

V

DDQ

TMS TDI TCK TDO NC

V

DDQ

U

7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch

Rev: 1.00 10/2001 9/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832218/36 119-Bump BGA Pin Description

Pin Location Symbol Type Description

P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs

R2, C3, B3, C2, A2, A3, A5, A6, T3,

T5, R6, C5, B5, C6, B6, B2

An I Address Inputs

T4, T6 An Address Input (x36 Version)

T2 NC — No Connect (x36 Version)

T2, T6, T4 An I Address Input (x18 Version)

K7, L7, N7, P7, K6, L6, M6, N6
H7, G7, E7, D7, H6, G6, F6, E6
H1, G1, E1, D1, H2, G2, F2, E2

K1, L1, N1, P1, K2, L2, M2, N2

DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8

I/O Data Input and Output pins. (x36 Version)

P6, D6, D2, P2

DQA9, DQB9,

DQC9, DQD9

I/O Data Input and Output pins. (x36 Version)

L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2

DQA1–DQA9
DQB1–DQB9

I/O Data Input and Output pins (x18 Version)

L5, G3 BA, BB I Byte Write Enable for DQA, DQB I/Os; active low (x18 Version)

B1, C1, R1, T1, U6, B7, C7, J3, J5,

R7

NC — No Connect

P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,

G5, L3

NC — No Connect (x18 Version)

K4 CK I Clock Input Signal; active high
M4 BW I Byte Write—Writes all enabled bytes; active low
H4 GW I Global Write Enable—Writes all bytes; active low

E4 E1 I Chip Enable; active low

F4 G I Output Enable; active low
G4 ADV I Burst address counter advance enable; active low

A4, B4 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low

T7 ZZ I Sleep mode control; active high
R5 FT I Flow Through or Pipeline mode; active low
R3 LBO I Linear Burst Order mode; active low

D4 ZQ I

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive],

High = High Impedance [Low Drive])

L4 SCD I Single Cycle Deselect/Dual Cyle Deselect Mode Control
U2

TMS

I Scan Test Mode Select

Rev: 1.00 10/2001 10/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

U3

TDI

I Scan Test Data In

U5

TDO

O Scan Test Data Out

U4

TCK

I Scan Test Clock

J2, C4, J4, R4, J6

V

DD

I Core power supply

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5

V

SS

I I/O and Core Ground

L4

V

SS

I I/O and Core Ground

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7

V

DDQ

I Output driver power supply

GS832218/36 119-Bump BGA Pin Description

Pin Location Symbol Type Description

Rev: 1.00 10/2001 11/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832218/36 (PE = 0) Block Diagram

A1

A0

A0

A1

D0
D1

Q1

Q0

Counter

Load

D Q

D Q

Register

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

DQ

Register

DQ

Register

A0–An

LBO
ADV

CK
ADSC

ADSP
GW

BW

E1

FT

G

ZZ

Power Down

Control

Memory

Array

36

36

4

A

Q D

DQx0–DQx9

NC

Parity

NC

Parity

Encode

Compare

36

4

36

36

4

32

Note: Only x36 version shown for simplicity.

SCD

36

36

D Q

Register

4

BA

BB

BC

BD

Rev: 1.00 10/2001 12/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS816218/36 (PE = 1) x32 Mode Block Diagram

A1

A0

A0

A1

D0
D1

Q1

Q0

Counter

Load

D Q

D Q

Register

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

DQ

Register

DQ

Register

A0–An

LBO
ADV

CK
ADSC

ADSP
GW

BW
BA

BB

BC

BD

E1

FT

G

ZZ

Power Down

Control

Memory

Array

36

36

4

A

Q D

DQx0–DQx8

NC

Parity

NC

Parity

Encode

Compare

32

4

32

36

4

32

Note: Only x36 version shown for simplicity.

SCD

D Q

Register

D Q

Register

Parity

Encode

32

4

32

36

Rev: 1.00 10/2001 13/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the PE and ZZ pins, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name

Pin

Name

State Function

Burst Order Control LBO

L Linear Burst

H Interleaved Burst

Output Register Control FT

L Flow Through

H or NC Pipeline

Power Down Control ZZ

L or NC Active

H

Standby, IDD = I

SB

Single/Dual Cycle Deselect Control SCD

L Dual Cycle Deselect

H or NC Single Cycle Deselect

Parity Enable PE

L or NC Activate 9th I/O’s (x18/36 Mode)

H Deactivate 9th I/O’s (x16/32 Mode)

FLXDrive Output Impedance Control ZQ

L High Drive (Low Impedance)

H or NC Low Drive (High Impedance)

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

I

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01
4th address 11 00 01 10

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01
4th address 11 10 01 00

Rev: 1.00 10/2001 14/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Byte Write Truth Table

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X