GSI GS832036T-166, GS832036T-150I, GS832036T-150, GS832036T-133I, GS832036T-133 Datasheet

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GS832018/32/36T-250/225/200/166/150/133

100-Pin TQFP

2M x 18, 1M x 32, 1M x 36

Commercial Temp Industrial Temp

36Mb Sync Burst SRAMs

Features

• FT pin for user-configurable flow through or pipeline operation

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

3.3 V

2.5 V Flow

Through

2-1-1-1

3.3 V

2.5 V

t

KQ

tCycle

Curr (x18)

Curr (x32/x36)

Curr (x18)

Curr (x32/x36)

t

KQ

tCycle

Curr (x18)

Curr (x32/x36)

Curr (x18)

Curr (x32/x36)

2.3

4.0

365 430

360 420

6.0

7.0

200 230

200 225

2.5

4.4

335 390

330 380

6.5

7.5

200 230

200 225

3.0

3.5

5.0

6.0

300

265

350

305

295

260

340

295

7.5

8.51010101115ns

8.5

180

195

180

195

3.8

6.6

240 280

235 270

180 195

4.0

7.5nsns

220 245mAmA

215 235mAmA

ns

135 145mAmA

130 145mAmA

250 MHz–133 MHz

2.5 V or 3.3 V V

DD

2.5 V or 3.3 V I/O

cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS832018/32/36T operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

) pins are used to decouple output noise

DDQ

Functional Description

Applications

The GS832018/32/36T is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832018 100-Pin TQFP Pinout

A6

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GS832018/32/36T-250/225/200/166/150/133

DD

E3

E1

A7

E2

BB

BA

NC

SS

V

BW

GW

G

CK

ADSC

A8

ADV

ADSP

A9

NC NC NC

V

DDQ

V

NC

NC DQB1 DQB2

V

DDQ

DQB3 DQB4

V

NC

V DQB5 DQB6

V

DDQ

V DQB7 DQB8

DQB9

NC

V

DDQ

NC NC NC

SS

FT

DD

SS

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

2M x 18

Top View

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

A20 NC NC V

DDQ

V

SS

NC DQA9 DQA8 DQA7 V

SS

V

DDQ

DQA6 DQA5 V

SS

NC V

DD

ZZ DQA4 DQA3 V

DDQ

V

SS

DQA2 DQA1 NC NC V

SS

V

DDQ

NC NC NC

SS

A5

A4

A3

A2

A1

A0

NC

LBO

A19

DD

A17

A18

V

A11

A10

A12

A13

A14

A16

A15

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832032 100-Pin TQFP Pinout

A6

A7

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GS832018/32/36T-250/225/200/166/150/133

DD

E3

E1

E2

BB

BA

BC

BD

SS

V

BW

GW

G

CK

ADSC

A8

ADV

ADSP

A9

NC DQC8 DQC7

V

DDQ

V

SS

DQC6 DQC5 DQC4 DQC3

V

DDQ

DQC2 DQC1

FT

V

DD

NC

V

SS

DQD1 DQD2

V

DDQ

V DQD3 DQD4

DQD5 DQD6

V V

DDQ

DQD7 DQD8

NC

SS

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

1M x 32

Top View

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

NC DQB8 DQB7 V

DDQ

V

SS

DQB6 DQB5 DQB4 DQB3 V

SS

V

DDQ

DQB2 DQB1 V

SS

NC V

DD

ZZ DQA1 DQA2 V

DDQ

V

SS

DQA3 DQA4 DQA5 DQA6 V

SS

V

DDQ

DQA7 DQA8 NC

SS

A5

A4

A3

A2

A1

A0

NC

LBO

A19

DD

A18

V

A11

A17

A10

A12

A13

A14

A16

A15

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832036 100-Pin TQFP Pinout

A6

A7

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GS832018/32/36T-250/225/200/166/150/133

DD

E3

E1

E2

BB

BA

BC

BD

SS

V

BW

GW

G

CK

ADSC

A8

ADV

ADSP

A9

DQC9 DQC8 DQC7

V

DDQ

V

SS

DQC6 DQC5 DQC4 DQC3

V

SS

V

DDQ

DQC2 DQC1

FT

V

DD

NC

V

SS

DQD1 DQD2

V

DDQ

V DQD3 DQD4

DQD5 DQD6

V

DDQ

DQD7 DQD8 DQD9

SS

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

1M x 36

Top View

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

DQB9 DQB8 DQB7 V

DDQ

V

SS

DQB6 DQB5 DQB4 DQB3 V

SS

V

DDQ

DQB2 DQB1 V

SS

NC V

DD

ZZ DQA1 DQA2 V

DDQ

V

SS

DQA3 DQA4 DQA5 DQA6 V

SS

V

DDQ

DQA7 DQA8 DQA9

SS

A5

A4

A3

A2

A1

A0

NC

LBO

A19

DD

V

A18

A11

A10

A12

A13

A14

A16

A17

A15

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TQFP Pin Description

Pin Location Symbol Type Description

37, 36 A0, A1 I Address field LSBs and Address Counter preset Inputs

35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,

47, 48, 49, 50, 43, 42

80 A20 I Address Input (x18 version) 39 A19 I Address Input

63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79

13, 12, 9, 8, 7, 6, 3, 2

18, 19, 22, 23, 24, 25, 28, 29

51, 80, 1, 30

51, 80, 1, 30 NC No Connect (x32 Version)

58, 59, 62, 63, 68, 69, 72, 73, 74

8, 9, 12, 13, 18, 19, 22, 23, 24

51, 52, 53, 56, 57

75, 78, 79, 95, 96,

1, 2, 3, 6, 7,

25, 28, 29, 30

87 BW I Byte Write—Writes all enabled bytes; active low

93, 94 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low

95, 96 BC, BD I

89 CK I Clock Input Signal; active high 88 GW I Global Write Enable—Writes all bytes; active low

98, 92 E1, E3 I Chip Enable; active low

97 E2 I Chip Enable; active high 86 G I Output Enable; active low 83 ADV I Burst address counter advance enable; active low

84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low

64 ZZ I Sleep Mode control; active high 14 FT I Flow Through or Pipeline mode; active low 31 LBO I Linear Burst Order mode; active low

15, 41, 65, 91

5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90

4, 11, 20, 27, 54, 61, 70, 77

16, 38, 39, 66 NC — No Connect

GS832018/32/36T-250/225/200/166/150/133

A2–A18 I Address Inputs

DQA1–DQA8 DQB1–DQB8 DQC1–DQC8 DQD1–DQD8

DQA9, DQB9,

DQC9, DQD9

DQA1–DQA9 DQB1–DQB9

NC — No Connect (x18 Version)

V

DD

V

SS

V

DDQ

I/O Data Input and Output pins (x32, x36 Version)

I/O Data Input and Output pins (x36 Version)

I/O Data Input and Output pins (x18 Version)

Byte Write Enable for DQC, DQD Data I/Os; active low

(x32, x36 Version)

I Core power supply I I/O and Core Ground I Output driver power supply

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832018/32/36 Block Diagram

A0–An

LBO ADV

CK ADSC

ADSP GW

BW

BA

Register

D Q

A0

A1

D0 D1

Counter

Load

Register

D Q

Q0 Q1

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GS832018/32/36T-250/225/200/166/150/133

A0 A1

A

Memory

Array

Q D

FT

E1 E2 E3

G

BB

BC

BD

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

36

4

DQ

Register

36

Register

DQ

ZZ

Note: Only x36 version shown for simplicity.

Power Down

Control

1

DQx0–DQx9

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Linear Burst Sequence

I

Mode Pin Functions

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GS832018/32/36T-250/225/200/166/150/133

Mode Name

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

Note: There is a pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.

Name

State Function

L Linear Burst

H Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

Standby, IDD = I

SB

Burst Counter Sequences

nterleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

A[1:0] A[1:0] A[1:0] A[1:0]

4th address 11 00 01 10

Note: The burst counter wraps to initial state on the 5th clock.

4th address 11 10 01 00

Note: The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832018/32/36T-250/225/200/166/150/133

Byte Write Truth Table

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x32 and x36 versions.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Synchronous Truth Table

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GS832018/32/36T-250/225/200/166/150/133

Operation

Deselect Cycle, Power Down None X H X X L X X High-Z

Deselect Cycle, Power Down None X L F L X X X High-Z

Deselect Cycle, Power Down None X L F H L X X High-Z

Read Cycle, Begin Burst External R L T L X X X Q

Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D

Read Cycle, Continue Burst Next CR X X H H L F Q

Read Cycle, Continue Burst Next CR H X X H L F Q

Write Cycle, Continue Burst Next CW X X H H L T D

Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D

Notes:

1. X = Don’t Care, H = High, L = Low

2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Address

Used

Diagram

5

Key

E1

E

2

ADSP ADSC ADV

W

3

DQ

4

State

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.