GSI GS832036T-166, GS832036T-150I, GS832036T-150, GS832036T-133I, GS832036T-133 Datasheet
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Product Preview
GS832018/32/36T-250/225/200/166/150/133
100-Pin TQFP
2M x 18, 1M x 32, 1M x 36
Commercial Temp
Industrial Temp
36Mb Sync Burst SRAMs
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
3.3 V
2.5 V
Flow
Through
2-1-1-1
3.3 V
2.5 V
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
Curr (x18)
Curr (x32/x36)
2.3
4.0
365
430
360
420
6.0
7.0
200
230
200
225
2.5
4.4
335
390
330
380
6.5
7.5
200
230
200
225
3.0
3.5
5.0
6.0
300
265
350
305
295
260
340
295
7.5
8.51010101115ns
8.5
180
180
195
195
180
180
195
195
3.8
6.6
240
280
235
270
180
195
180
195
4.0
7.5nsns
220
245mAmA
215
235mAmA
ns
135
145mAmA
130
145mAmA
250 MHz–133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS832018/32/36T operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
from the internal circuits and are 3.3 V and 2.5 V compatible.
) pins are used to decouple output noise
DDQ
Functional Description
Applications
The GS832018/32/36T is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
Rev: 1.00 10/2001 1/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832018 100-Pin TQFP Pinout
A6
Product Preview
GS832018/32/36T-250/225/200/166/150/133
DD
E3
E1
A7
E2
BB
BA
NC
NC
SS
V
V
BW
GW
G
CK
ADSC
A8
ADV
ADSP
A9
NC
NC
NC
V
DDQ
V
NC
NC
DQB1
DQB2
V
V
DDQ
DQB3
DQB4
V
NC
V
DQB5
DQB6
V
DDQ
V
DQB7
DQB8
DQB9
NC
V
V
DDQ
NC
NC
NC
SS
SS
FT
DD
SS
SS
SS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2M x 18
Top View
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A20
NC
NC
V
DDQ
V
SS
NC
DQA9
DQA8
DQA7
V
SS
V
DDQ
DQA6
DQA5
V
SS
NC
V
DD
ZZ
DQA4
DQA3
V
DDQ
V
SS
DQA2
DQA1
NC
NC
V
SS
V
DDQ
NC
NC
NC
SS
A5
A4
A3
A2
A1
A0
NC
LBO
A19
DD
A17
A18
V
V
A11
A10
A12
A13
A14
A16
A15
Rev: 1.00 10/2001 2/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832032 100-Pin TQFP Pinout
A6
A7
Product Preview
GS832018/32/36T-250/225/200/166/150/133
DD
E3
E1
E2
BB
BA
BC
BD
SS
V
V
BW
GW
G
CK
ADSC
A8
ADV
ADSP
A9
NC
DQC8
DQC7
V
DDQ
V
SS
DQC6
DQC5
DQC4
DQC3
V
V
DDQ
DQC2
DQC1
FT
V
DD
NC
V
SS
DQD1
DQD2
V
DDQ
V
DQD3
DQD4
DQD5
DQD6
V
V
DDQ
DQD7
DQD8
NC
SS
SS
SS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1M x 32
Top View
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB8
DQB7
V
DDQ
V
SS
DQB6
DQB5
DQB4
DQB3
V
SS
V
DDQ
DQB2
DQB1
V
SS
NC
V
DD
ZZ
DQA1
DQA2
V
DDQ
V
SS
DQA3
DQA4
DQA5
DQA6
V
SS
V
DDQ
DQA7
DQA8
NC
SS
A5
A4
A3
A2
A1
A0
NC
LBO
A19
DD
A18
V
V
A11
A17
A10
A12
A13
A14
A16
A15
Rev: 1.00 10/2001 3/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832036 100-Pin TQFP Pinout
A6
A7
Product Preview
GS832018/32/36T-250/225/200/166/150/133
DD
E3
E1
E2
BB
BA
BC
BD
SS
V
V
BW
GW
G
CK
ADSC
A8
ADV
ADSP
A9
DQC9
DQC8
DQC7
V
DDQ
V
SS
DQC6
DQC5
DQC4
DQC3
V
SS
V
DDQ
DQC2
DQC1
FT
V
DD
NC
V
SS
DQD1
DQD2
V
DDQ
V
DQD3
DQD4
DQD5
DQD6
V
V
DDQ
DQD7
DQD8
DQD9
SS
SS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1M x 36
Top View
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB9
DQB8
DQB7
V
DDQ
V
SS
DQB6
DQB5
DQB4
DQB3
V
SS
V
DDQ
DQB2
DQB1
V
SS
NC
V
DD
ZZ
DQA1
DQA2
V
DDQ
V
SS
DQA3
DQA4
DQA5
DQA6
V
SS
V
DDQ
DQA7
DQA8
DQA9
SS
A5
A4
A3
A2
A1
A0
NC
LBO
A19
DD
V
V
A18
A11
A10
A12
A13
A14
A16
A17
A15
Rev: 1.00 10/2001 4/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
TQFP Pin Description
Pin Location Symbol Type Description
37, 36 A0, A1 I Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43, 42
80 A20 I Address Input (x18 version)
39 A19 I Address Input
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
51, 80, 1, 30 NC No Connect (x32 Version)
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79, 95, 96,
1, 2, 3, 6, 7,
25, 28, 29, 30
87 BW I Byte Write—Writes all enabled bytes; active low
93, 94 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low
95, 96 BC, BD I
89 CK I Clock Input Signal; active high
88 GW I Global Write Enable—Writes all bytes; active low
98, 92 E1, E3 I Chip Enable; active low
97 E2 I Chip Enable; active high
86 G I Output Enable; active low
83 ADV I Burst address counter advance enable; active low
84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low
64 ZZ I Sleep Mode control; active high
14 FT I Flow Through or Pipeline mode; active low
31 LBO I Linear Burst Order mode; active low
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
16, 38, 39, 66 NC — No Connect
GS832018/32/36T-250/225/200/166/150/133
A2–A18 I Address Inputs
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
DQA9, DQB9,
DQC9, DQD9
DQA1–DQA9
DQB1–DQB9
NC — No Connect (x18 Version)
V
DD
V
SS
V
DDQ
I/O Data Input and Output pins (x32, x36 Version)
I/O Data Input and Output pins (x36 Version)
I/O Data Input and Output pins (x18 Version)
Byte Write Enable for DQC, DQD Data I/Os; active low
(x32, x36 Version)
I Core power supply
I I/O and Core Ground
I Output driver power supply
Product Preview
Rev: 1.00 10/2001 5/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832018/32/36 Block Diagram
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
Register
D Q
A0
A1
D0
D1
Counter
Load
Register
D Q
Q0
Q1
Product Preview
GS832018/32/36T-250/225/200/166/150/133
A0
A1
A
Memory
Array
Q D
FT
E1
E2
E3
G
BB
BC
BD
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
Register
D Q
36
4
DQ
Register
36
Register
DQ
ZZ
Note: Only x36 version shown for simplicity.
Power Down
Control
1
DQx0–DQx9
Rev: 1.00 10/2001 6/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Linear Burst Sequence
I
Mode Pin Functions
Product Preview
GS832018/32/36T-250/225/200/166/150/133
Mode Name
Burst Order Control LBO
Output Register Control FT
Power Down Control ZZ
Note:
There is a pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Pin
Name
State Function
L Linear Burst
H Interleaved Burst
L Flow Through
H or NC Pipeline
L or NC Active
H
Standby, IDD = I
SB
Burst Counter Sequences
nterleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
A[1:0] A[1:0] A[1:0] A[1:0]
4th address 11 00 01 10
Note: The burst counter wraps to initial state on the 5th clock.
4th address 11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00 10/2001 7/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
GS832018/32/36T-250/225/200/166/150/133
Byte Write Truth Table
Function GW BW BA BB BC BD Notes
Read H H X X X X 1
Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4
Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.00 10/2001 8/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Synchronous Truth Table
Product Preview
GS832018/32/36T-250/225/200/166/150/133
Operation
Deselect Cycle, Power Down None X H X X L X X High-Z
Deselect Cycle, Power Down None X L F L X X X High-Z
Deselect Cycle, Power Down None X L F H L X X High-Z
Read Cycle, Begin Burst External R L T L X X X Q
Read Cycle, Begin Burst External R L T H L X F Q
Write Cycle, Begin Burst External W L T H L X T D
Read Cycle, Continue Burst Next CR X X H H L F Q
Read Cycle, Continue Burst Next CR H X X H L F Q
Write Cycle, Continue Burst Next CW X X H H L T D
Write Cycle, Continue Burst Next CW H X X H L T D
Read Cycle, Suspend Burst Current X X H H H F Q
Read Cycle, Suspend Burst Current H X X H H F Q
Write Cycle, Suspend Burst Current X X H H H T D
Write Cycle, Suspend Burst Current H X X H H T D
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Address
Used
Diagram
5
Key
E1
E
2
ADSP ADSC ADV
W
3
DQ
4
State
Rev: 1.00 10/2001 9/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
Simplified State Diagram
GS832018/32/36T-250/225/200/166/150/133
X
Deselect
W R
W
X
Simple Synchronous OperationSimple Burst Synchronous Operation
First Write
W R
Burst Write
CW CR
R
CR
R
CR
R
First Read
Burst Read
X
CRCW
XX
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)
control inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.00 10/2001 10/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Simplified State Diagram with G
Product Preview
GS832018/32/36T-250/225/200/166/150/133
X
Deselect
W R
W
X
X
First Write
W
Burst Write
CW CR
R
CR
R
CR
W
CW
W
CW
R
First Read
R
Burst Read
X
CRCW
X
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.00 10/2001 11/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832018/32/36T-250/225/200/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
Product Preview
V
DD
V
DDQ
V
CK
V
I/O
V
IN
I
IN
I
OUT
P
D
T
STG
T
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Voltage on VDD Pins –0.5 to 4.6 V
Voltage in V
Pins –0.5 to 4.6 V
DDQ
Voltage on Clock Input Pin –0.5 to 6 V
Voltage on I/O Pins –0.5 to V
Voltage on Other Input Pins –0.5 to V
+0.5 (≤ 4.6 V max.) V
DDQ
+0.5 (≤ 4.6 V max.) V
DD
Input Current on Any Pin +/–20 mA
Output Current on Any I/O Pin +/–20 mA
Package Power Dissipation 1.5 W
Storage Temperature –55 to 125
Temperature Under Bias –55 to 125
o
o
C
C
Rev: 1.00 10/2001 12/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Power Supply Voltage Ranges
Parameter Symbol Min. Typ. Max. Unit Notes
Product Preview
GS832018/32/36T-250/225/200/166/150/133
3.3 V Supply Voltage
2.5 V Supply Voltage
3.3 V V
2.5 V V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
I/O Supply Voltage V
DDQ
I/O Supply Voltage V
DDQ
V
DD3
V
DD2
DDQ3
DDQ2
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
3.0 3.3 3.6 V
2.3 2.5 2.7 V
3.0 3.3 3.6 V
2.4 2.5 2.7 V
V
Range Logic Levels
DDQ3
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage V
V
Input Low Voltage V
DD
V
I/O Input High Voltage V
DDQ
V
I/O Input Low Voltage V
DDQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
3. V
(max) is voltage on V
IHQ
pins plus 0.3 V.
DDQ
DDn
IH
IL
IHQ
ILQ
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
1.7 —
–0.3 — 0.8 V 1
1.7 —
–0.3 — 0.8 V 1,3
V
Range Logic Levels
DDQ2
VDD + 0.3
V
+ 0.3
DDQ
V 1
V 1,3
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage V
V
Input Low Voltage V
DD
V
I/O Input High Voltage V
DDQ
V
I/O Input Low Voltage V
DDQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
3. V
(max) is voltage on V
IHQ
pins plus 0.3 V.
DDQ
DDn
IH
IL
IHQ
ILQ
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.00 10/2001 13/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
0.6*V
DD
–0.3 —
0.6*V
DD
–0.3 —
—
—
VDD + 0.3
0.3*V
V
+ 0.3
DDQ
0.3*V
DD
DD
V 1
V 1
V 1,3
V 1,3
Recommended Operating Temperatures
Parameter Symbol Min. Typ. Max. Unit Notes
Product Preview
GS832018/32/36T-250/225/200/166/150/133
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
Note:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
T
A
T
A
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
0 25 70 °C 2
–40 25 85 °C 2
Undershoot Measurement and Timing Overshoot Measurement and Timing
V
– 2.0 V
SS
V
50%
IH
V
+ 2.0 V
DD
SS
20% tKC
50%
V
DD
V
IL
20% tKC
Capacitance
(TA = 25oC, f = 1 MHZ, V
DD
= 2.5 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance
Input/Output Capacitance
Note: These parameters are sample tested.
C
IN
C
I/O
V
V
OUT
IN
= 0 V
= 0 V
4 5 pF
6 7 pF
Package Thermal Characteristics
Rating Layer Board Symbol Max Unit Notes
Junction to Ambient (at 200 lfm) single
Junction to Ambient (at 200 lfm) four
Junction to Case (TOP) —
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.00 10/2001 14/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
R
R
R
ΘJA
ΘJA
ΘJC
40 °C/W 1,2
24 °C/W 1,2
9 °C/W 3
AC Test Conditions
Parameter Conditions
Input high level 2.3 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level 1.25 V
Output reference level 1.25 V
Output load Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig.
1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, t
4. Device is deselected as defined by the Truth Table.
DQ
and t
OLZ
Output Load 1
OHZ
Product Preview
GS832018/32/36T-250/225/200/166/150/133
Output Load 2
2.5 V
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins)
ZZ Input Current
FT Input Current
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
50Ω
VT = 1.25 V
I
IL
I
IN1
I
IN2
I
OL
V
OH2
V
OH3
V
OL
*
30pF
* Distributed Test Jig Capacitance
V
IN
V
DD ≥ VIN ≥ VIH
0 V ≤ V
V
DD ≥ VIN ≥ VIL
0 V ≤ V
Output Disable, V
I
= –8 mA, V
OH
I
= –8 mA, V
OH
I
OL
= 0 to V
IN
IN
OUT
DDQ
DDQ
= 8 mA
DQ
DD
≤ V
IH
≤ V
IL
= 0 to V
= 2.375 V
= 3.135 V
5pF
DD
225Ω
*
225Ω
–1 uA 1 uA
–1 uA
–1 uA
–100 uA
–1 uA
1 uA
100 uA
1 uA
1 uA
–1 uA 1 uA
1.7 V —
2.4 V —
— 0.4 V
Rev: 1.00 10/2001 15/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
GS832018/32/36T-250/225/200/166/150/133
Unit
to
–40
0
to
to
–40
0
to
to
–40
0
to
to
–40
0
to
to
–40
mA
230
85°C
220
70°C
260
85°C
250
70°C
280
85°C
270
70°C
320
85°C
310
70°C
355
85°C
mA
25
140
25
130
30
185
30
175
35
185
35
175
40
185
40
175
45
215
mA
15
215
15
205
20
230
20
220
20
255
20
245
20
290
20
280
25
320
mA
15
130
15
120
20
175
20
165
20
175
20
165
20
175
20
165
25
195
mA
15
230
15
220
15
260
15
250
15
280
15
270
15
320
15
310
15
355
mA
15
140
15
130
20
185
20
175
25
185
25
175
30
185
30
175
35
215
mA
15
215
15
205
20
230
20
220
20
255
20
245
20
290
20
280
20
320
mA
mA
mA
mA
mA
10
10
15
15
15
15
15
15
20
10
130
10
120
15
175
15
165
15
175
15
165
15
175
15
165
15
195
0
to
to
–40
-250 -225 -200 -166 -150 -133
0
to
45
345
70°C
50
390
85°C
50
380
70°C
25
205
25
215
25
205
25
310
25
350
25
340
15
185
15
195
15
185
35
345
40
390
40
380
20
205
20
215
20
205
20
310
20
350
20
340
15
185
15
195
15
25 35 25 35 25 35 25 35 25 35 25 35
185
25 35 25 35 25 35 25 35 25 35 25 35
80 85 80 85 70 75 70 75 70 75 65 70
115 120 110 115 105 110 100 105 95 100 90 95
operation.
DDQ2
, and V
SB
DD
I
DD
I
DDQ
I
DD
I
DDQ
I
DD
I
DDQ
I
DD
I
DDQ
I
DD
I
DDQ
I
DD
I
DDQ
I
DD
I
DDQ
I
DDQ
I
SB
DD
I
I
DD
I
I
DDQ3
, V
DD2
, V
Flow
Pipeline
Through
x36)
(x32/
IL
Flow
Pipeline
Through
(x18)
Flow
Pipeline
Through
x36)
(x32/
IL
Flow
Pipeline
Through
(x18)
Flow
Pipeline
Through
—
Flow
Pipeline
Through
—
IL
DD3
– 0.2 V
or ≤ V
IH
≥V
Device Selected;
Output open
All other inputs
or ≤ V
IH
≥V
Device Selected;
Output open
All other inputs
DD
ZZ ≥ V
or ≤ V
IH
≥ V
All other inputs
Device Deselected;
apply to any combination of V
DDQ
and I
Operating Currents
Parameter Test Conditions Mode Symbol
Operating
Operating
3.3 V
Current
2.5 V
Current
Current
Standby
Current
Deselect
DD
Notes:
1. I
2. All parameters listed are worst case scenario.
Rev: 1.00 10/2001 16/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
AC Electrical Characteristics
Product Preview
GS832018/32/36T-250/225/200/166/150/133
Pipeline
Flow
Through
Parameter Symbol
-250 -225 -200 -166 -150 -133
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns
Clock to Output Valid tKQ — 2.3 — 2.5 — 3.0 — 3.4 — 3.8 — 4.0 ns
Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
Clock to Output in Low-Z
tLZ
1
1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
Clock Cycle Time tKC 7.0 — 7.5 — 8.5 — 10.0 — 10.0 — 15.0 — ns
Clock to Output Valid tKQ — 6.0 — 6.0 — 7.5 — 8.5 — 10.0 — 10.0 ns
Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns
Clock to Output in Low-Z
tLZ
1
3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns
Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.5 — 1.7 — ns
Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.7 — 2 — ns
Clock to Output in
High-Z
tHZ
1
1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.5 1.5 3.8 1.5 4.0 ns
G to Output Valid tOE — 2.3 — 2.5 — 3.2 — 3.5 — 3.8 — 4.0 ns
G to output in Low-Z
G to output in High-Z
tOLZ
tOHZ
1
0 — 0 — 0 — 0 — 0 — 0 — ns
1
— 2.3 — 2.5 — 3.0 — 3.5 — 3.8 — 4.0 ns
Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
ZZ setup time
ZZ hold time
tZZS
tZZH
2
5 — 5 — 5 — 5 — 5 — 5 — ns
2
1 — 1 — 1 — 1 — 1 — 1 — ns
ZZ recovery tZZR 100 — 100 — 100 — 100 — 100 — 100 — ns
Unit
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.00 10/2001 17/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Write Cycle Timing
Product Preview
GS832018/32/36T-250/225/200/166/150/133
CK
ADSP
ADSC
ADV
A0–An
GW
BW
BA–BD
Single Write
tH
tS
tH
tS
WR1
tS
tH
Burst Write
ADSP is blocked by E inactive
tKC
tKL
tKH
tH
tS
tH
tS
ADV must be inactive for ADSP Write
WR2 WR3
tS tH
tH
tS
tS
tH
WR1 WR2 WR3
WR1
WR2 WR3
E1 masks ADSP
Write
ADSC initiated write
Deselected
E1
tH
tS
Deselected with E2
E2
tS
tH
E2 and E3 only sampled with ADSP or ADSC
E3
G
tS
tH
DQA–DQD
Hi-Z
D1A
Rev: 1.00 10/2001 18/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Write specified byte for 2A and all bytes for 2B, 2C& 2D
D2A D2B
D2C D2D D3A
Flow Through Read Cycle Timing
Product Preview
GS832018/32/36T-250/225/200/166/150/133
CK
ADSP
ADSC
ADV
A0–An
GW
BW
BA–BB
Single Read
tS
tH
tS
tS
tH
RD1
tS
tS
tH
tS
tKL
tKH
tS
tH
tH
RD2 RD3
Burst Read
ADSP is blocked by E inactive
tKC
Suspend Burst
E1 masks ADSP
ADSC initiated read
Suspend Burst
tH
tH
E1
tH
tS
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
tS
tH
E3
tOE
tOHZ
G
DQA–DQD
tOLZ
Hi-Z
Q1A
tLZ
tKQ
Q2A
tKQX
Q2cQ2B
Q2D
Rev: 1.00 10/2001 19/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
tKQX
Q3A
tHZ
Flow Through Read-Write Cycle Timing
Single Read
CK
tH
tS
ADSP
ADSC
tH
tS
ADV
tS
tH
tKH
tKL
tS
Single Write
tKC
tH
ADSC initiated read
Product Preview
GS832018/32/36T-250/225/200/166/150/133
Burst Read
ADSP is blocked by E inactive
A0–An
GW
BW
BA–BD
E1
E2
E3
G
DQA–DQD
Hi-Z
tS
tS
tS
RD1
tH
tH
tH
tOE
tKQ
tS
tS
tH
tOHZ
Q1A
WR1
tS
tH
tS
E2 and E3 only sampled with ADSP and ADSC
tS
tH
WR1
tH
D1A
RD2
E1 masks ADSP
Q2A
Deselected with E3
Q2B Q2c
Q2D
Q2A
Burst wrap around to it’s initial state
Rev: 1.00 10/2001 20/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Pipelined SCD Read Cycle Timing
Product Preview
GS832018/32/36T-250/225/200/166/150/133
CK
ADSP
ADSC
ADV
A0–An
GW
BW
BWA–BWD
Single Read
tH
tS
tS
tH
tS
RD1
tS
tS
tH
tS
RD2
tKH
tH
tKL
Burst Read
tKC
ADSP is blocked by E inactive
Suspend Burst
ADSC initiated read
RD3
tH
tH
E1
E2
E3
G
DQA–DQD
Hi-Z
tS
tS
tS
tH
tH
tH
tOLZ
tLZ
E1 masks ADSP
E2 and E3 only sampled with ADSP or ADSC
tOE
tOHZ
tKQX
Q1A
tKQ
Q2A
Q2B
Q2c
Deselected with E2
tKQX
Q2D
Q3A
tHZ
Rev: 1.00 10/2001 21/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Pipelined SCD Read-Write Cycle Timing
Product Preview
GS832018/32/36T-250/225/200/166/150/133
CK
ADSP
ADSC
ADV
A0–An
GW
BW
BWA–BWD
tKL
Single Write
tKC
tS tH
WR1
tH
tS
WR1
ADSP is blocked by E inactive
ADSC initiated read
RD2
tH
Single Read Burst Read
tH
tS
tS
RD1
tH
tS
tS
tS
tH
tH
tKH
DQA–DQD
E1
E2
E3
G
Hi-Z
tS
tS
tS
tH
tH
tH
E2 and E3 only sampled with ADSP and ADSC
tOE tOHZ
tS
tKQ
Q1A
tH
D1A Q2A
E1 masks ADSP
Deselected with E3
Q2Bb Q2c
Q2D
Rev: 1.00 10/2001 22/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
GS832018/32/36T-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
~
~
~
~
~
~
CK
ADSP
tS
tH
tKC
tKH
tKL
ADSC
ZZ
tZZS
~
~
~
~
~
~
Snooze
tZZH
tZZR
Rev: 1.00 10/2001 23/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
TQFP Package Drawing
D
Product Preview
GS832018/32/36T-250/225/200/166/150/133
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
b Lead Width 0.20 0.30 0.40
c Lead Thickness 0.09 — 0.20
D Terminal Dimension 21.9 22.0 22.1
D1 Package Body 19.9 20.0 20.1
E Terminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
e Lead Pitch — 0.65 —
L Foot Length 0.45 0.60 0.75
L1 Lead Length — 1.00 —
Y Coplanarity 0.10
θ Lead Angle 0° — 7°
L1
A1
θ
L
c
Pin 1
e
D1
b
A2
Y
E1
E
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.00 10/2001 24/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
GS832018/32/36T-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
2
Org
2M x 18 GS832018T-250 Pipeline/Flow Through TQFP 250/6 C
2M x 18 GS832018T-225 Pipeline/Flow Through TQFP 225/6.5 C
2M x 18 GS832018T-200 Pipeline/Flow Through TQFP 200/7.5 C
2M x 18 GS832018T-166 Pipeline/Flow Through TQFP 166/8.5 C
2M x 18 GS832018T-150 Pipeline/Flow Through TQFP 150/10 C
2M x 18 GS832018T-133 Pipeline/Flow Through TQFP 133/11 C
1M x 32 GS832032T-250 Pipeline/Flow Through TQFP 250/6 C
1M x 32 GS832032T-225 Pipeline/Flow Through TQFP 225/6.5 C
1M x 32 GS832032T-200 Pipeline/Flow Through TQFP 200/7.5 C
1M x 32 GS832032T-166 Pipeline/Flow Through TQFP 166/8.5 C
1M x 32 GS832032T-150 Pipeline/Flow Through TQFP 150/10 C
1M x 32 GS832032T-133 Pipeline/Flow Through TQFP 133/11 C
1M x 36 GS832036T-250 Pipeline/Flow Through TQFP 250/6 C
1M x 36 GS832036T-225 Pipeline/Flow Through TQFP 225/6.5 C
1M x 36 GS832036T-200 Pipeline/Flow Through TQFP 200/7.5 C
1M x 36 GS832036T-166 Pipeline/Flow Through TQFP 166/8.5 C
1M x 36 GS832036T-150 Pipeline/Flow Through TQFP 150/10 C
1M x 36 GS832036T-133 Pipeline/Flow Through TQFP 133/11 C
2M x 18 GS832018T-250I Pipeline/Flow Through TQFP 250/6 I Not Available
2M x 18 GS832018T-225I Pipeline/Flow Through TQFP 225/6.5 I Not Available
2M x 18 GS832018T-200I Pipeline/Flow Through TQFP 200/7.5 I Not Available
2M x 18 GS832018T-166I Pipeline/Flow Through TQFP 166/8.5 I
2M x 18 GS832018T-150I Pipeline/Flow Through TQFP 150/10 I
2M x 18 GS832018T-133I Pipeline/Flow Through TQFP 133/11 I
1M x 32 GS832032T-250I Pipeline/Flow Through TQFP 250/6 I Not Available
1M x 32 GS832032T-225I Pipeline/Flow Through TQFP 225/6.5 I Not Available
1M x 32 GS832032T-200I Pipeline/Flow Through TQFP 200/7.5 I Not Available
1M x 32 GS832032T-166I Pipeline/Flow Through TQFP 166/8.5 I
1M x 32 GS832032T-150I Pipeline/Flow Through TQFP 150/10 I
1M x 32 GS832032T-133I Pipeline/Flow Through TQFP 133/11 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832018T-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Part Number
1
Type Package
Speed
(MHz/ns)
3
T
A
Status
Rev: 1.00 10/2001 25/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
GS832018/32/36T-250/225/200/166/150/133
2
Org
1M x 36 GS832036T-250I Pipeline/Flow Through TQFP 250/6 I Not Available
1M x 36 GS832036T-225I Pipeline/Flow Through TQFP 225/6.5 I Not Available
1M x 36 GS832036T-200I Pipeline/Flow Through TQFP 200/7.5 I Not Available
1M x 36 GS832036T-166I Pipeline/Flow Through TQFP 166/8.5 I
1M x 36 GS832036T-150I Pipeline/Flow Through TQFP 150/10 I
1M x 36 GS832036T-133I Pipeline/Flow Through TQFP 133/11 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832018T-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Part Number
1
Type Package
Speed
(MHz/ns)
3
T
A
Status
Rev: 1.00 10/2001 26/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
36Mb Sync SRAM Datasheet Revision History
Product Preview
GS832018/32/36T-250/225/200/166/150/133
DS/DateRev. Code: Old;
New
832018_r1
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
Rev: 1.00 10/2001 27/27 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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