GS820H32AT/Q-150/138/133/117/100/66
TQFP, QFP
Commercial Temp
Industrial Temp
64K x 32
2M Synchronous Burst SRAM
150Mhz - 66Mhz 9ns - 18ns 3.3V VDD 3.3V & 2.5V I/O
Features
•FT pin for user configurable flow through or pipelined operation.
•Single Cycle Deselect (SCD) Operation.
•High Output Drive current.
•3.3V +10%/-5% Core power supply
•2.5V or 3.3V I/O supply.
•LBO pin for linear or interleaved burst mode.
•Internal input resistors on mode pins allow floating mode pins.
•Default to Interleaved Pipelined Mode.
•Byte write (BW) and/or global write (GW) operation.
•Common data inputs and data outputs.
•Clock Control, registered, address, data, and control.
•Internal Self-Timed Write cycle.
•Automatic power-down for portable applications.
•JEDEC standard 100-lead TQFP or QFP package.
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-150 |
-138 |
-133 |
-117 |
-100 |
-66 |
Pipeline |
tCycle |
6.6ns |
7.25ns |
7.5ns |
8.5ns |
10ns |
12.5ns |
3-1-1-1 |
tKQ |
3.8ns |
4ns |
4ns |
4.5 |
5ns |
6ns |
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IDD |
270mA |
245mA |
240mA |
210mA |
180mA |
150mA |
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Flow |
tCycle |
10.5ns |
15ns |
15ns |
15ns |
15ns |
20ns |
Through |
tKQ |
9ns |
9.7ns |
10ns |
11ns |
12ns |
18ns |
2-1-1-1 |
IDD |
170mA |
120mA |
120mA |
120mA |
120mA |
95mA |
Flow Through / Pipeline Reads
The function of the Data Output register can be controlled by the user via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FPBGA). Holding the FT mode pin/bump low, places the RAM in Flow through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined Mode, activating the rising edge triggered Data Output Register.
Pipelined Reads
The GS820H32A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Functional Description
Applications
The GS820H32A is a 2,097,152 bit high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS820H32A operates on a 3.3V power supply and all inputs/ outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive edge triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Rev: 1.04 3/2000 |
1/23 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
E |
GS820H32AT/Q-150/138/133/117/100/66
GS820H32A 100 Pin TQFP and QFP Pinout
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A6 |
A7 |
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E1 |
E2 |
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BD |
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BC |
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BB |
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BA |
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E3 |
VDD |
VSS |
CK |
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GW |
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BW |
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G |
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ADSC |
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ADSP |
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ADV |
A8 |
A9 |
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NC |
100 |
99 |
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98 |
97 |
96 |
95 |
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94 |
93 |
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92 |
91 |
90 |
89 |
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88 |
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87 |
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86 |
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85 |
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84 |
83 |
82 |
81 |
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1 |
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80 |
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DQC8 |
2 |
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79 |
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DQC7 |
3 |
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78 |
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VDDQ |
4 |
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77 |
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VSS |
5 |
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76 |
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DQC6 |
6 |
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75 |
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DQC5 |
7 |
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74 |
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DQC4 |
8 |
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73 |
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DQC3 |
9 |
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64K x 32 |
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72 |
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VSS |
10 |
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71 |
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Top View |
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VDDQ |
11 |
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70 |
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||||||||||||||||||||
DQC2 |
12 |
|
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|
69 |
|
|
|||||
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||||||||
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|
||||||||
DQC1 |
13 |
|
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68 |
|
|
|||||
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||||||||
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||||||||
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|||||
|
FT |
|
14 |
|
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|
67 |
|
|
|||
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||||||||
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|
||||||||
VDD |
15 |
|
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66 |
|
|
|||||
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||||||||
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|
||||||||
NC |
16 |
|
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65 |
|
|
|||||
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||||||||
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|
||||||||
VSS |
17 |
|
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|
64 |
|
|
|||||
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||||||||
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|
||||||||
DQD1 |
18 |
|
|
|
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|
63 |
|
|
|||||
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||||||||
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|
||||||||
DQD2 |
19 |
|
|
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|
62 |
|
|
|||||
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||||||||
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|
||||||||
VDDQ |
20 |
|
|
|
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|
61 |
|
|
|||||
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|
||||||||
VSS |
21 |
|
|
|
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|
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|
60 |
|
|
|||||
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|
||||||||
DQD3 |
22 |
|
|
|
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|
59 |
|
|
|||||
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||||||||
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|
|
||||||||
DQD4 |
23 |
|
|
|
|
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|
58 |
|
|
|||||
|
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||||||||
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|
||||||||
DQD5 |
24 |
|
|
|
|
|
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|
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|
57 |
|
|
|||||
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||||||||
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|
||||||||
DQD6 |
25 |
|
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|
56 |
|
|
|||||
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||||||||
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|
||||||||
VSS |
26 |
|
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|
55 |
|
|
|||||
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||||||||
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||||||||
VDDQ |
27 |
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54 |
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||||||||
DQD7 |
28 |
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53 |
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||||||||
DQD8 |
29 |
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52 |
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||||||||
NC |
30 |
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51 |
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31 |
32 |
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33 |
34 |
35 |
36 |
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37 |
38 |
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39 |
40 |
41 |
42 |
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43 |
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44 |
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45 |
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46 |
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47 |
48 |
49 |
50 |
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LBO |
A5 |
A4 |
A3 |
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A2 |
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A1 |
A0 |
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NC |
NC |
VSS |
|
VDD |
NC |
NC |
A10 |
A11 |
A12 |
A13 |
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A14 |
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A15 |
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NC |
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NC
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
Rev: 1.04 3/2000 |
2/23 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
E |
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GS820H32AT/Q-150/138/133/117/100/66 |
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TQFP Pin Description |
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Pin Location |
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Symbol |
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Type |
Description |
|
||||||||||||||||||||
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|||||||||||||||||||
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37, |
36 |
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A0, A1 |
|
I |
Address field LSB’s and Address Counter preset Inputs |
|
|||||||||||||||||||
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35, 34, 33, 32, 100, 99, 82, 81, |
44, 45, |
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A2-15 |
|
I |
Address Inputs |
|
|||||||||||||||||||
|
46, 47, 48, 49 |
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|||||||||||||||||||||||
|
52, 53, 56, 57, 58, 59, 62, 63 |
|
DQA1-DQA8 |
|
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|||||||||||||||||||||||
|
68, 69, 72, 73, 74, 75, 78, 79 |
|
DQB1-DQB8 |
|
I/O |
Data Input and Output pins. |
|
|||||||||||||||||||||||
|
2, 3, 6, 7, 8, 9, 12, 13 |
|
|
DQC1-DQC8 |
|
|
||||||||||||||||||||||||
|
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|
||||||||||||||||||||||||
|
18, 19, 22, 23, 24, 25, 28, 29 |
|
DQD1-DQD8 |
|
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|
|||||||||||||||||||||||
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|||||||||||||||
|
16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30 |
|
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|
NC |
|
|
No Connect |
|
|||||||||||||||
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||||
|
87 |
|
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|
I |
Byte Write. Writes all enabled bytes. Active Low. |
|
|||
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|
|
BW |
|
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||||||||||||||
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||||||
|
93, 94 |
|
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|
|
A, |
|
|
|
|
|
B |
|
I |
Byte Write Enable for DQA, DQB Data I/O’s. Active Low. |
|
||||||||
|
|
|
|
|
B |
B |
|
|
||||||||||||||||||||||
|
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|||||||||
|
95, 96 |
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|
C, |
|
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|
|
|
D |
|
I |
Byte Write Enable for DQC, DQD Data I/O’s. Active Low. |
|
|||||||||
|
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|
|
B |
B |
|
|
|||||||||||||||||||||||
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|
||||||||||||||
|
89 |
|
|
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|
|
|
|
|
|
|
CK |
|
I |
Clock Input Signal. Active High. |
|
||||||||||||||
|
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||||||||||
|
88 |
|
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|
|
|
I |
Global Write Enable. Writes all bytes. Active Low. |
|
|||
|
|
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|
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|
|
|
|
GW |
|
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|
|
|
||||||||||||||||
|
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|
|||||||||||
|
98, 92 |
|
|
|
|
|
|
|
|
|
|
|
1, |
|
|
|
|
|
|
3 |
|
I |
Chip Enable. Active Low. |
|
||||||
|
|
|
|
|
|
E |
|
E |
|
|
||||||||||||||||||||
|
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|
|||||||||||||
|
97 |
|
|
|
|
|
|
|
|
|
|
|
E2 |
|
I |
Chip Enable. Active High. |
|
|||||||||||||
|
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||||||||
|
86 |
|
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|
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|
|
I |
Output Enable. Active Low. |
|
|||
|
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|
|
G |
|
|
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|
||||||||||||
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|
||||||||||||
|
83 |
|
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|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
I |
Burst address counter advance enable. Active Low. |
|
|||
|
|
|
|
|
|
|
ADV |
|
|
|
||||||||||||||||||||
|
|
|
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|
||||||||||||||||||
|
84, 85 |
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I |
Address Strobe (Processor, Cache Controller). Active Low. |
|
|||
|
|
|
ADSP, |
|
ADSC |
|
|
|||||||||||||||||||||||
|
|
|
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|
|||||||||||||
|
64 |
|
|
|
|
|
|
|
|
|
|
|
ZZ |
|
I |
Sleep Mode control. Active High. |
|
|||||||||||||
|
|
|
|
|
|
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|
||||||||||||
|
14 |
|
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|
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|
|
|
|
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|
|
|
|
|
|
|
|
I |
Flow Through or Pipeline mode. Active Low. |
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
FT |
|
|
|
|
||||||||||||||
|
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|
||||||||||||||||||
|
31 |
|
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|
|
|
|
|
|
|
|
|
|
|
|
I |
Linear Burst Order mode. Active Low. |
|
|||
|
|
|
|
|
|
|
|
LBO |
|
|
|
|||||||||||||||||||
|
|
|
|
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|
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|
|
|
|
|
||||||||||||||||
|
15, 41, 65, 91 |
|
|
|
|
|
|
|
|
VDD |
|
I |
Core power supply. |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||
|
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 |
|
|
|
|
|
|
|
VSS |
|
I |
I/O and Core Ground. |
|
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||||||||
|
4, 11, 20, 27, 54, 61, 70, 77 |
|
|
|
|
VDDQ |
|
I |
Output driver power supply. |
|
||||||||||||||||||||
|
|
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|
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|
H
Rev: 1.04 3/2000 |
3/23 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
E |
|
|
|
|
|
GS820H32AT/Q-150/138/133/117/100/66 |
|
GS820H32A Block Diagram |
|
|
|
|
||
|
Register |
|
|
|
|
|
A0-An |
D |
Q |
|
|
|
|
|
|
A0 |
|
|
A0 |
|
|
|
|
|
|
|
|
|
|
D0 |
|
Q0 |
A1 |
|
|
|
A1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
D1 |
|
Q1 |
|
|
|
|
Counter |
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A |
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Load |
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LBO |
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Memory |
ADV |
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CK |
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Array |
ADSC |
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ADSP |
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Q |
D |
GW |
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Register |
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BW |
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D |
Q |
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BA |
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Register |
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32 |
32 |
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D |
Q |
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BB |
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4 |
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Register |
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D |
Q |
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BC |
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Register Q D |
Register D Q |
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Register |
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D |
Q |
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BD |
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Register |
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D |
Q |
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1 |
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Register |
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E |
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D |
Q |
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E2 |
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E3 |
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Register |
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D |
Q |
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FT
G
ZZ |
|
Power Down |
DQx1-DQx8 |
|
Control |
||
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||
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|
Rev: 1.04 3/2000 |
4/23 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
E |
|
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GS820H32AT/Q-150/138/133/117/100/66 |
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Mode Pin Functions |
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|||||
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Mode Name |
Pin Name |
State |
Function |
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L |
Linear Burst |
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Burst Order Control |
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LBO |
||||||||
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H or NC |
Interleaved Burst |
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L |
Flow Through |
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Output Register Control |
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FT |
|||||||
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||||||
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H or NC |
Pipeline |
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Power Down Control |
|
ZZ |
L or NC |
Active |
|
|||||
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H |
Standby, IDD = ISB |
|
|||||||
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|
Note:
There are pull up devices on LBO and FT pins and a pull down device on and ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
|
A[1:0] |
A[1:0] |
A[1:0] |
A[1:0] |
|
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1st address |
00 |
01 |
10 |
11 |
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2nd address |
01 |
10 |
11 |
00 |
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3rd address |
10 |
11 |
00 |
01 |
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4th address |
11 |
00 |
01 |
10 |
|
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|
|
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
|
A[1:0] |
A[1:0] |
A[1:0] |
A[1:0] |
|
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1st address |
00 |
01 |
10 |
11 |
|
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2nd address |
01 |
00 |
11 |
10 |
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3rd address |
10 |
11 |
00 |
01 |
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4th address |
11 |
10 |
01 |
00 |
|
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|
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
|
|
|
|
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|
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|
|
Function |
|
GW |
|
BW |
|
BA |
|
BB |
BC |
BD |
Notes |
||||||||
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Read |
|
H |
|
H |
|
X |
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X |
|
X |
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X |
1 |
||||||
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Read |
|
H |
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L |
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H |
|
H |
|
H |
|
H |
1 |
||||||
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Write byte A |
|
H |
|
L |
|
L |
|
H |
|
H |
|
H |
2, 3 |
||||||
|
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Write byte B |
|
H |
|
L |
|
H |
|
L |
|
H |
|
H |
2, 3 |
||||||
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Write byte C |
|
H |
|
L |
|
H |
|
H |
|
L |
|
H |
2, 3, 4 |
||||||
|
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Write byte D |
|
H |
|
L |
|
H |
|
H |
|
H |
|
L |
2, 3, 4 |
||||||
|
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|
Write all bytes |
|
H |
|
L |
|
L |
|
L |
|
L |
|
L |
2, 3, 4 |
||||||
|
|
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|
Write all bytes |
|
L |
|
X |
|
X |
|
X |
|
X |
|
X |
|
||||||
|
|
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|
|
Note:
1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2.Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3.All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.04 3/2000 |
5/23 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
E |
GS820H32AT/Q-150/138/133/117/100/66
Synchronous Truth Table
|
|
State |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Operation |
Address Used |
Diagram |
|
E |
1 |
E2 |
|
ADSP |
|
|
ADSC |
|
|
ADV |
|
W3 |
DQ4 |
|
|
Key5 |
|
|
|
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|
|
|
|
|
|
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|
|
|
|
||
Deselect Cycle, Power Down |
None |
X |
|
H |
X |
|
X |
|
|
L |
|
|
X |
X |
High-Z |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Deselect Cycle, Power Down |
None |
X |
|
L |
F |
|
L |
|
|
X |
|
|
X |
X |
High-Z |
||
Deselect Cycle, Power Down |
None |
X |
|
L |
F |
|
H |
|
|
L |
|
|
X |
X |
High-Z |
||
|
|
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|
||
|
|
|
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|
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|
|
|
|
|
|
|
Read Cycle, Begin Burst |
External |
R |
|
L |
T |
|
L |
|
|
X |
|
|
X |
X |
Q |
||
Read Cycle, Begin Burst |
External |
R |
|
L |
T |
|
H |
|
|
L |
|
|
X |
F |
Q |
||
|
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||
|
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|
|
||
Write Cycle, Begin Burst |
External |
W |
|
L |
T |
|
H |
|
|
L |
|
|
X |
T |
D |
||
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
||
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|
||
Read Cycle, Continue Burst |
Next |
CR |
|
X |
X |
|
H |
|
|
H |
|
|
L |
F |
Q |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Read Cycle, Continue Burst |
Next |
CR |
|
H |
X |
|
X |
|
|
H |
|
|
L |
F |
Q |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Write Cycle, Continue Burst |
Next |
CW |
|
X |
X |
|
H |
|
|
H |
|
|
L |
T |
D |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Write Cycle, Continue Burst |
Next |
CW |
|
H |
X |
|
X |
|
|
H |
|
|
L |
T |
D |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Read Cycle, Suspend Burst |
Current |
|
|
X |
X |
|
H |
|
|
H |
|
|
H |
F |
Q |
||
Read Cycle, Suspend Burst |
Current |
|
|
H |
X |
|
X |
|
|
H |
|
|
H |
F |
Q |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Write Cycle, Suspend Burst |
Current |
|
|
X |
X |
|
H |
|
|
H |
|
|
H |
T |
D |
||
Write Cycle, Suspend Burst |
Current |
|
|
H |
X |
|
X |
|
|
H |
|
|
H |
T |
D |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Note:
1.X = Don’t Care, H = High, L = Low.
2.E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above).
5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.
6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.04 3/2000 |
6/23 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
E |
GS820H32AT/Q-150/138/133/117/100/66
Simplified State Diagram
X |
|
|
|
Deselect |
|
|
|
|
W |
|
|
|
W |
|
|
Operation |
X |
First Write |
R |
|
SynchronousSimple |
||||
CW |
|
CR |
||
|
|
|||
Operation |
|
W |
|
|
Synchronous |
|
|
||
X |
Burst Write |
R |
||
|
|
|
||
Burst |
|
|
CR |
|
Simple |
|
CW |
|
|
|
|
|
R |
|
R |
|
First Read |
X |
|
CR |
R |
|
Burst Read |
X |
CR |
|
Notes:
1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2.The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs and that ADSP is tied high and ADSC is tied low.
3.The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes ADSP is tied high and ADV is tied low.
Rev: 1.04 3/2000 |
7/23 |
© 2000, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
E |