Datasheet GS8170LW72C-250I, GS8170LW72C-250, GS8170LW36C-333I, GS8170LW36C-333, GS8170LW36C-300I Datasheet (GSI)

Rev: 1.01 7/2002 1/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

18Mb Σ1x1

Late Write

SigmaRAM™ SRAM

250 MHz–333 MHz

1.8 V V

DD

1.8 V and 1.5 V I/O

209-Bump BGA
Commercial Temp
Industrial Temp

Features

• Late Write mode

• Pipeline read operation

• JEDEC-standard SigmaRAM

™

pinout and package

• 1.8 V +150/–100 mV core power supply

• 1.5 V or 1.8 V I/O supply

• Dual Cycle Deselect

• Synchronous Burst operation

• Fully coherent read and write pipelines

• Echo Clock outputs track data output drivers

• ZQ mode pin for user-selectable output drive strength

• Byte write operation (9-bit bytes)

• 2 user-programmable chip enable inputs for easy depth
expansion.

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices

SigmaRAM Family Overview

GS8170LW18/36/72 SigmaRAMs (ΣRAM

™)

are built in

compliance with the ΣRAM pinout standard for synchronous

SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are
the first in a family of wide, very low voltage CMOS I/O
SRAMs designed to operate at the speeds needed to implement
economical high performance networking systems.

GSI's ΣRAMs are offered in a number of configurations that

emulate other synchronous SRAMs, such as Burst RAMs,
NBT, Late Write, or Double Data Rate (DDR) SRAMs. The
logical differences between the protocols employed by these
RAMs hinge mainly on various combinations of address

bursting, output data registering and write cueing. The ΣRAM

family standard allows a user to implement the interface
protocol best suited to the task at hand.

Functional Description

Because ΣRAMs are synchronous devices, address, data

inputs, and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.

This ΣRAM reads in Pipeline mode. In Pipeline mode, single
data rate ΣRAMs incorporate a rising-edge-triggered output

register. For read cycles, a pipelined SRAM’s output data is
staged at the input of an edge-triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.

GS8170LW18/36/72C ΣRAMs are implemented with GSI's

high performance CMOS technology and are packaged in a
209-bump BGA.

- 333

Pipeline mode

tKHKH 3.0 ns
tKHQV 1.6 ns

209-Bump, 14 mm x 22 mm BGA

1 mm Bump Pitch, 11 x 19 Bump Array

Bottom View

Rev: 1.01 7/2002 2/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

8170LW72C 256K x 72 Pinout

256K x 72 Common I/O—Top View

1234567891011

A DQg DQg A E2 A

ADV A

E3 A DQb DQb

B DQg DQg Bc

Bg NC W A Bb Bf DQb DQb

C DQg DQg Bh

Bd NC

(144M)

E1 NC Be Ba DQb DQb

D DQg DQg V

SS

NC NC MCL NC NC V

SS

DQb DQb

E DQg DQc V

DDQ

V

DDI

V

DD

V

DD

V

DD

V

DDI

V

DDQ

DQf DQb

FDQcDQcV

SS

V

SS

V

SS

ZQ V

SS

V

SS

V

SS

DQf DQf

G DQc DQc V

DDQ

V

DDQ

V

DD

EP2 V

DD

V

DDQ

V

DDQ

DQf DQf

H DQc DQc V

SS

V

SS

V

SS

EP3 V

SS

V

SS

V

SS

DQf DQf

J DQc DQc V

DDQ

V

DDQ

V

DD

MCH V

DD

V

DDQ

V

DDQ

DQf DQf

K CQ2 CQ2

CK NC V

SS

MCL V

SS

NC NC CQ1 CQ1

L DQh DQh V

DDQ

V

DDQ

V

DD

MCL V

DD

V

DDQ

V

DDQ

DQa DQa

M DQh DQh V

SS

V

SS

V

SS

MCL V

SS

V

SS

V

SS

DQa DQa

N DQh DQh V

DDQ

V

DDQ

V

DD

MCH V

DD

V

DDQ

V

DDQ

DQa DQa

P DQh DQh V

SS

V

SS

V

SS

MCL V

SS

V

SS

V

SS

DQa DQa

R DQd DQh V

DDQ

V

DDI

V

DD

V

DD

V

DD

V

DDI

V

DDQ

DQa DQe

T DQd DQd V

SS

NC NC MCL NC NC V

SS

DQe DQe

U DQd DQd NC A NC

(72M)

A NC

(36M)

A NC DQe DQe

VDQdDQdAAAA1AAADQe DQe

WDQdDQdTMS TDI AA0ATDO TCK DQe DQe

• 2001.03

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.01 7/2002 3/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

8170LW36C 512K x 36 Pinout

512K x 36 Common I/O—Top View

1234567891011

A NC NC A E2 A

ADV A E3 A DQb DQb

B NC NC Bc

NC A W A Bb NC DQb DQb

C NC NC NC Bd

NC

(144M)

E1 NC NC Ba DQb DQb

D NC NC V

SS

NC NC MCL NC NC V

SS

DQb DQb

E NC DQc V

DDQ

V

DDI

V

DD

V

DD

V

DD

V

DDI

V

DDQ

NC DQb

F DQc DQc V

SS

V

SS

V

SS

ZQ V

SS

V

SS

V

SS

NC NC

G DQc DQc V

DDQ

V

DDQ

V

DD

EP2 V

DD

V

DDQ

V

DDQ

NC NC

H DQc DQc V

SS

V

SS

V

SS

EP3 V

SS

V

SS

V

SS

NC NC

J DQc DQc V

DDQ

V

DDQ

V

DD

MCH V

DD

V

DDQ

V

DDQ

NC NC

K CQ2 CQ2

CK NC V

SS

MCL V

SS

NC NC CQ1 CQ1

L NC NC V

DDQ

V

DDQ

V

DD

MCL V

DD

V

DDQ

V

DDQ

DQa DQa

M NC NC V

SS

V

SS

V

SS

MCL V

SS

V

SS

V

SS

DQa DQa

N NC NC V

DDQ

V

DDQ

V

DD

MCH V

DD

V

DDQ

V

DDQ

DQa DQa

P NC NC V

SS

V

SS

V

SS

MCL V

SS

V

SS

V

SS

DQa DQa

R DQd NC V

DDQ

V

DDI

V

DD

V

DD

V

DD

V

DDI

V

DDQ

DQa NC

T DQd DQd V

SS

NC NC MCL NC NC V

SS

NC NC

U DQd DQd NC A NC (72M) A NC (36M) A NC NC NC

VDQdDQdAAAA1AAANC NC

WDQdDQdTMSTDI AA0ATDO TCK NC NC

• 2001.03

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.01 7/2002 4/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

8170LW18 1M x 18 Pinout

1M x 18 Common I/O—Top View

1234567891011

A NC NC A E2 A ADV A E3 A NC NC

B NC NC Bb

NC A W A NC NC NC NC

C NC NC NC NC NC

(144M)

E1

A NC Ba NC NC

D NC NC V

SS

NC NC MCL NC NC V

SS

NC NC

E NC DQb V

DDQ

V

DDI

V

DD

V

DD

V

DD

V

DDI

V

DDQ

NC NC

F DQb DQb V

SS

V

SS

V

SS

ZQ V

SS

V

SS

V

SS

NC NC

G DQb DQb V

DDQ

V

DDQ

V

DD

EP2 V

DD

V

DDQ

V

DDQ

NC NC

H DQb DQb V

SS

V

SS

V

SS

EP3 V

SS

V

SS

V

SS

NC NC

J DQb DQb V

DDQ

V

DDQ

V

DD

MCH V

DD

V

DDQ

V

DDQ

NC NC

K CQ2 CQ2

CK NC V

SS

MCL V

SS

NC NC CQ1 CQ1

L NC NC V

DDQ

V

DDQ

V

DD

MCL V

DD

V

DDQ

V

DDQ

DQa DQa

M NC NC V

SS

V

SS

V

SS

MCL V

SS

V

SS

V

SS

DQa DQa

N NC NC V

DDQ

V

DDQ

V

DD

MCH V

DD

V

DDQ

V

DDQ

DQa DQa

P NC NC V

SS

V

SS

V

SS

MCL V

SS

V

SS

V

SS

DQa DQa

R NC NC V

DDQ

V

DDI

V

DD

V

DD

V

DD

V

DDI

V

DDQ

DQa NC

T NC NC V

SS

NC NC MCL NC NC V

SS

NC NC

U NC NC NC A NC

(72M)

A NC

(36M)

A NC NC NC

VNCNCAAAA1AAANC NC

WNCNCTMSTDIAA0ATDO TCK NC NC

• 2001.03

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.01 7/2002 5/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Pin Description Table

Symbol Description Type Comments

A Address Input —

ADV Advance Input Active High

Bx

Byte Write Enable Input Active Low

CK Clock Input Active High

CQ Echo Clock Output Active High

CQ

Echo Clock Output Active Low

DQ Data I/O Input/Output —

E1

Chip Enable Input Active Low

E2 & E3 Chip Enable Input Programmable Active High or Low

EP2 & EP3 Chip Enable Program Pin Input —

TCK Test Clock Input Active High

TDI Test Data In Input —

TDO Test Data Out Output —

TMS Test Mode Select Input —

MCH Must Connect High Input Active High

MCL Must Connect Low Input Active Low

NC No Connect — Not connected to die

W

Write Input Active Low

V

DD

Core Power Supply Input 1.8 V Nominal

V

DDQ

Output Driver Power Supply Input 1.8 V or 1.5 V Nominal

V

DDI

Input Buffer Power Supply Input 1.8 V or 1.5 V Nominal

V

SS

Ground Input —

ZQ Output Impedance Control Input

Low = Low Impedance [High Drive]
High = High Impedance [Low Drive]

Rev: 1.01 7/2002 6/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Background

The central characteristics of ΣRAMs are that they are extremely fast and consume very little power. Because both operating and
interface power is low, ΣRAMs can be implemented in a wide (x72) configuration, providing very high single package bandwidth

(in excess of 20Gb/s in ordinary pipelined configuration) and very low random access latency (5 ns). The use of very low voltage

circuits in the core and 1.8 V or 1.5 V interface voltages allow the speed, power and density performance of ΣRAMs.
The ΣRAM family of pinouts has been designed to support a number of different common read and write protocols. The following

timing diagrams provide a quick comparison between single data rate read and write protocols options available in the context of

the ΣRAM standard. This particular datasheet covers the single data rate (non-DDR), Late Write (LW) ΣRAM.

Common I/O SigmaRAM Family Mode Comparison—EW vs. LW vs. DLW

Note: R = Read, W = Write, Z = Deselect

The character of the applications for fast synchronous SRAMs in networking systems are extremely diverse. ΣRAMs have been

developed to address the broad variety of applications in the networking market in a manner that can be supported with a unified

development and manufacturing infrastructure. ΣRAMs address each of the bus protocol options commonly found in networking
systems. This allows the ΣRAM to find application in radical shrinks and speed-ups of existing networking chip sets that were

designed for use with older SRAMs, like the NBT, Late Write, or Double Data Rate SRAMs, as well as with new chip sets and

ASICs that employ the Echo Clocks and realize the full potential of the ΣRAMs.

Σ

1x1Ep (Early Write - Pipelined Read)

Σ

1x1Lp (Late Write - Pipelined Read)

Σ

1x1Dp (Double Late Write - Pipelined Read)

QE

DQ

QE

ABCDE F

F

Control

RXXWRR

BC E

CK

Address

CQ

D

DD

R

CK

QD

Address

A

QA DC

QA

R

DF

CK

CQ

W

Control

XZW

Address

ABC

Control

RWR

QC DD

DEF

WRW

CQ

QA DB























Rev: 1.01 7/2002 7/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

All address, data and control inputs (with the exception of PE2, PE3, ZQ, and the mode pins, L6, M6, J6) are synchronized to
rising clock edges. Read and write operations must be initiated with the Advance/Load

pin (ADV) held low, in order to load the

new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1

, E2, and E3). Deassertion of
any one of the Enable inputs will deactivate the device. It should be noted that ONLY deactivation of the RAM via E2 and/or
E3 deactivates the Echo Clocks, CQ1–CQ2.

Mode Selection Truth Table Standard

L6 M6 J6 Name Function Analogous to... In This Data Sheet?

000

Σ

1x1Ef

Early Write, Flow through Read Flow through Burst RAM No

001

Σ

1x1Lf

Late Write, Flow through Read Flow through NBT SRAM No

010 RFU n/a

011

Σ

1x2Lp

DDR Double Data Rate SRAM No

100

Σ

1x1Ep

Early Write, Pipeline Read Pipelined Burst RAM No

101

Σ

1x1Dp

Double Late Write, Pipeline Read Pipelined NBT SRAM No

110

Σ

1x1Lp

Late Write, Pipeline Read Pipelined Late Write SRAM Yes

111 RFU — n/a

Rev: 1.01 7/2002 8/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Read Operations

Pipelined Read

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W

) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins.

Single Data Rate Pipelined Read

FDAddress

Read

CK

E

QC QD

CQ

Read Deselect Read Read

AXXC

Key

Hi-Z Access

ADV

QA

/E

1

/W

DQ

Rev: 1.01 7/2002 9/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Write Operations

Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W

) is asserted low, and ADV is asserted low.

Late Write

In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late
Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications.

SigmaRAM Late Write with Pipelined Read

Key

QDQA D

C

CQ

Read Read

CDE

ADV

Read Deselect Write

Hi-Z

F

Access

CK

Address A XX

/E

1

/W

DQ

Rev: 1.01 7/2002 10/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Byte Write Control

The Byte Write Enable inputs (BX) determine which bytes will be written. All or none may be activated. A Write Cycle with no
Byte Write inputs active is a write abort cycle.

Byte Write Control Example with x18 SigmaRAM Late Write RAM

Example of x36 Byte Write Truth Table

Function W

B

A

B

B

B

C

B

D

Read HXXXX

Write Byte A L L H H H

Write Byte B L H L H H

Write Byte C L H H L H

Write Byte D L H H H L

Write all Bytes L L L L L

Write Abort L H H H H

DA DB DE

DA DC

F

/E

1

Write

BCD

ADV

ADV

Non-WriteWrite Write

CK

Address A E

Write

CQ

/BA

/BB

DQA0-DQA8

DQB0-DQB8

Rev: 1.01 7/2002 11/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Special Functions

Burst Cycles

ΣRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write

implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use
the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded
into the SRAM by driving the ADV pin low, into Load mode.

SigmaRAM Pipelined Burst Reads with Counter Wrap-around

Internal
Address

A2 A3 A0 A1 A2

CQ

DQ QA2 QA3 QA1

Counter Wraps

/E

1

A2 XX XX

QA0

/W

ADV

Continue

CK

XX XX

Read Continue Continue Continue

Extern al
Address

Rev: 1.01 7/2002 12/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

SigmaRAM Late Write SRAM Burst Writes with Counter Wrap-around

Burst Order

The burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) have
been accessed. SigmaRAMs always count in linear burst order.

Linear Burst Order

Note: The burst counter wraps to initial state on the 5th rising edge of clock.

Echo Clock

In Pipeline read mode, ΣRAMs feature Echo Clocks, CQ1,CQ2, CQ1, and CQ2 that track the performance of the output drivers.

The Echo Clocks are delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver
delays due to variance in die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output
drivers. SigmaRAMs provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1
and CQ2

).

A[1:0]

A[1:0]

A[1:0]

A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

D1 D2

XX XX

A2

Counter Wraps

CQ

Continue

/E

1

ADV

DQ D2

ADV

Continue

CK

Address A2 XX XX XX

Continue ContinueWrite

D0

/W

A1A2 A3 A0

D3

Internal

Addres

Rev: 1.01 7/2002 13/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1

does not deactivate the

Echo Clocks.

Programmable Enables

ΣRAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active

low or active high inputs, is determined by the state of the programming inputs, PE2 and PE3. For example, if PE2 is held at V

DD

,

E2 functions as an active high enable. If PE2 is held to V

SS

, E2 functions as an active low chip enable input.

Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming

the enable inputs of four ΣRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four
ΣRAMs can be made to look like one larger RAM to the system.

Example Four Bank Depth Expansion Schematic

A

CK

E1

E2

E3

W

A0–A

n

CK

W

DQ0–DQ

n

Bank 0

Bank 1 Bank 2

Bank 3

Bank Enable Truth Table

EP2 EP3 E2 E3

Bank 0

V

SS

V

SS

Active Low Active Low

Bank 1 V

SS

V

DD

Active Low Active High

Bank 2 V

DD

V

SS

Active High Active Low

Bank 3

V

DD

V

DD

Active High Active High

E1

A

n – 1

A

n

A0–A

n – 2

A

n – 1

A

n

A0–A

n – 2

A

n – 1

A

n

A0–A

n – 2

A

n – 1

A

n

A0–A

n – 2

DQ

A

CK

E2

E3

W

DQ

A

CK

E2

E3

W

DQ

A

CK

E2

E3

W

DQ

E1

E1

E1

CQ CQ CQ

CQ

CQ

EP2

EP3

0

0

EP2

EP3

1

0 EP2

EP3

0

1

EP2

EP3

1

1

Rev: 1.01 7/2002 14/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1

does not deactivate the

Echo Clocks.

In some applications it may be appropriate to pause between banks (i.e., to deselect both RAMs with E1

before resuming read

operations). An E1

deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle

in the bank. Although the following drawing illustrates a E1

read pause upon switching from Bank 1 to Bank 2, a write to Bank 2

would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.

Echo Clock Control in Two Banks of SigmaRAM Pipelined SRAMs

Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.

QD

CQ

Bank 1

CQ

Bank 2

DQ

Bank 2

QB

CQ1 + CQ2

QC

Address A B

/E

1

/E2 Bank 1

E2 Bank 2

DQ

Bank 1

QA

ADV

FDEC

Read Read Read

CK

Read Read

Rev: 1.01 7/2002 15/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

.

FLXDrive™ Output Driver Impedance Control

The ZQ pin allows selection between ΣRAM nominal drive strength (ZQ floating or low) for multi-drop bus applications and low

drive strength (ZQ high) point-to-point applications.

Pipelined Read Bank Switch with E1 Deselect

Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.

QDQC

CQ

Bank 1

CQ1 + CQ2

CQ

Bank 2

DQ

Bank 2

QA

Address A XX

ADV

/E

1

/E2 Bank 1

E2 Bank 2

DQ

Bank 1

FDEC

Read Read Read

CK

Read No Op

Rev: 1.01 7/2002 16/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Late Write, Pipelined Read Truth Table

CK

E1

(tn)E(tn)

ADV

(tn)W(tn)B(tn)

Previous

Operation

Current Operation

DQ/CQ

(tn)

DQ/CQ

(t

n+1

)

0→1 X F 0 X X X Bank Deselect ***/*** Hi-Z/Hi-Z

0

→

1 X X 1 X X Bank Deselect Bank Deselect (Continue) Hi-Z/Hi-Z Hi-Z/Hi-Z

0

→

1 1 T 0 X X X Deselect ***/*** Hi-Z/CQ

0

→

1 X X 1 X X Deselect Deselect (Continue) Hi-Z/CQ Hi-Z/CQ

0

→

10 T 0 0 T X

Write

Loads new address

Stores DQx if B

x = 0

***/*** D1/CQ

0

→

10 T 0 0 F X

Write (Abort)

Loads new address

No data stored

***/*** Hi-Z/CQ

0

→

1X X 1 X T Write

Write Continue

Increments address by 1

Stores DQx if B

x = 0

Dn-1/CQ Dn/CQ

0

→

1X X 1 X F Write

Write Continue (Abort)

Increments address by 1

No data stored

Dn-1/CQ Hi-Z/CQ

0

→

10 T 0 1 X X

Read

Loads new address

***/*** Qn/CQ

0

→

1 X X 1 X X Read

Read Continue

Increments address by 1

Qn-1/CQ Qn/CQ

Notes:

1. If E2 = EP2 and E3 = EP3, then E = “T” else E = “F”.

2. If one or more B

x = 0, then B = “T” else B = “F”.

3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

4. “***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.

5. DQs are tristated in response to Bank Deselect, Chip Deselect, and Write commands, one full cycle after the command is sampled.

6. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.

7. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces
of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter­nal (base) address.

Rev: 1.01 7/2002 17/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Common I/O State Diagram

Notes:

1. The notation “X,X,X,X” controlling the state transitions above indicate the states of inputs E1

, E, ADV, and W, respectively.

2. If (E2 = EP2 and E3 = EP3), then E = “T” else E = “F”.

3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

Deselect

Bank

Deselect

Read

Read

Write

Write

Continue

X,F,0,X or X,X,1,X

Continue

X,F,0,X

1,T,0,X

X,F,0,X

1,T,0,X

1,T,0,X

X,F,0,X

1,T,0,X

1,T,0,X or X,X,1,X

0,T,0,00,T,0,1

0,T,0,00,T,0,1

X,F,0,X

X,F,0,X

0,T,0,0

0,T,0,1 X,X,1,X X,X,1,X

0,T,0,0

0,T,0,1

1,T,0,X

0,T,0,0

0,T,0,1

X,X,1,X X,X,1,X

0,T,0,1 0,T,0,0

Clock (CK)

Command

Current State Next State

ƒƒƒƒ

Current State & Next State Definition for Read/Write Control State Diagram

Current State (n)

Next State (n + 1)

Transition

ƒ

Input Command Code

Key

n n+1 n+2 n+3

Rev: 1.01 7/2002 18/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to
Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended
period of time, may affect reliability of this component.

Recommended Operating Conditions

Absolute Maximum Ratings

(All voltages reference to V

SS

)

Symbol Description Value Unit

V

DD

Voltage on VDD Pins

–0.5 to 2.5 V

V

DDI

Voltage in V

DDI

Pins

–0.5 to 2.5 V

V

DDQ

Voltage in V

DDQ

Pins –0.5 to V

DD

V

V

I/O

Voltage on I/O Pins

–0.5 to V

DDQ

+0.5 (≤ 2.5 V max.)

V

V

IN

Voltage on Other Input Pins

–0.5 to V

DDI

+0.5 (≤ 2.5 V max.)

V

I

IN

Input Current on Any Pin +/–100 mA dc

I

OUT

Output Current on Any I/O Pin +/–100 mA dc

T

J

Maximum Junction Temperature 125

o

C

T

STG

Storage Temperature –55 to 125

º

C

Power Supplies

Parameter Symbol Min. Typ. Max. Unit Notes

Supply Voltage

V

DD

1.7 1.8 1.95 V

1.8 V Input Supply Voltage

V

DDI

1.7 1.8

V

DD

V1

1.8 V I/O Supply Voltage

V

DDQ

1.7 1.8

V

DD

V1

1.5 V Input Supply Voltage

V

DDI

1.4 1.5 1.6 V V 1

1.5 V I/O Supply Voltage

V

DDQ

1.4 1.5 1.6 V V 1

Ambient Temperature

(Commercial Range Versions)

T

A

02570°C2

Ambient Temperature

(Industrial Range Versions)

T

A

–40 25 85 °C2

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ V

DDQ

≤ 1.6V (i.e., 1.5 V I/O)

and 1.7 V ≤ V

DDQ

≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.

2. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number
of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evalu­ated for worst case in the temperature range marked on the device.

Rev: 1.01 7/2002 19/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Note: This parameter is sample tested.

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

CMOS I/O DC Input Characteristics

Parameter Symbol Min. Typ. Max. Unit Notes

CMOS Input High Voltage

V

IH

0.65 * V

DDI

—

V

DDI

+ 0.3

V1

CMOS I/O Input High Voltage

V

IH

0.65 * V

DDI

—

V

DDI

+ 0.3

V1

CMOS Input Low Voltage

V

IL

–0.3 —

0.35 * V

DDI

V1

Note: For devices supplied with CMOS input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.

Capacitance

(TA = 25oC, f = 1 MHZ, V

DD

= 1.8 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

C

IN

V

IN

= 0 V

45pF

Output Capacitance

C

OUT

V

OUT

= 0 V

67pF

Package Thermal Characteristics

Rating Layer Board Symbol Max Unit Notes

Junction to Ambient (at 200 lfm) single

R

ΘJA

TBD °C/W 1,2

Junction to Ambient (at 200 lfm) four

R

ΘJA

TBD °C/W 1,2

Junction to Case (TOP) n/a

R

ΘJC

TBD °C/W 3

20% tKC

SS

– 1.0 V

50%

V

SS

V

IH

Undershoot Measurement and Timing Overshoot Measurement and Timing

20% tKC

V

DD

+ 1.0 V

50%

V

DD

V

IL

Rev: 1.01 7/2002 20/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

AC Test Load Diagram

AC Test Conditions

Parameter Conditions

Input high level

V

DDQ

Input low level 0 V

Max. input slew rate 2 V/ns

Input reference level

V

DDI

/2

Output reference level

V

DDQ

/2

Input and Output Leakage Characteristics

Parameter Symbol Test Conditions Min. Max Notes

Input Leakage Current

(except mode pins)

I

IL

V

IN

= 0 to V

DD

–2 uA 2 uA —

Mode and ZQ, MCH, MCL, EP1, EP2

Pin Input Current

I

INM

V

DD ≥

V

IN

≥

VIL

0 V

≤ V

IN

≤ V

IL

–2 uA

–50 uA

50 uA

2 uA

—

Output Leakage Current

I

OL

Output Disable,

V

OUT

= 0 to V

DDQ

–2 uA 2 uA —

Selectable Impedance Output Driver DC Electrical Characteristics

Parameter Symbol Test Conditions Min. Max Notes

Low Drive Output High Voltage

V

OHL

I

OHL

= –4 mA V

DDQ

– 0.4 V

—1

Low Drive Output Low Voltage

V

OLL

I

OLL

= 4 mA

— 0.4 V 1

High Drive Output High Voltage

V

OHH

I

OHH

= –8 mA V

DDQ

– 0.4 V

—2

High Drive Output Low Voltage

V

OLH

I

OLH

= 8 mA

— 0.4 V 2

Notes:

1. ZQ = 1; High Impedance output driver setting (low drive)

2. ZQ = 0; Low Impedance output driver setting (high drive)

DQ

VT = V

DDQ

/2

50Ω

ZQ = High (CMOS I/O)

Rev: 1.01 7/2002 21/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Operating Currents

Parameter Symbol

-333 -300 -250
Test Conditions

0°C to

70°C

–40°C to

+85°C

0°C to

70°C

–40°C to

+85°C

0°C to

70°C

–40°C to

+85°C

Operating

Current

x72

I

DDP

(PL)

345 mA 355 mA 320 mA 330 mA 275 mA 285 mA

E1 ≤ V

IL

Max.

tKHKH ≥ tKHKH Min.

All other inputs

V

IL

≥ V

IN

≥ V

IH

x36

I

DDP

(PL)

245 mA 255 mA 225 mA 235 mA 200 mA 210 mA

x18

I

DDP

(PL)

195 mA 205 mA 180 mA 190 mA 160 mA 170 mA

Chip Disable

Current

x72

I

SB1

(PL)

75 mA 85 mA 70 mA 80 mA 65 mA 75 mA

E1 ≥ V

IH

Min. or

tKHKH ≥ tKHKH Min.

All other inputs

V

IL

≥ V

IN

≥ V

IH

x36

I

SB1

(PL)

70 mA 80 mA 65 mA 75 mA 60 mA 70 mA

x18

I

SB1

(PL)

70 mA 80 mA 65 mA 75 mA 60 mA 70 mA

Bank Deselect

Current

x72

I

SB2

(PL)

75 mA 85 mA 70 mA 80 mA 65 mA 75 mA

E2 or E3 False

tKHKH ≥ tKHKH Min.

All other inputs

V

IL

≥ V

IN

≥ V

IH

x36

I

SB2

(PL)

70 mA 80 mA 65 mA 75 mA 60 mA 70 mA

x18

I

SB2

(PL)

70 mA 80 mA 65 mA 75 mA 60 mA 70 mA

CMOS

Deselect

Current

I

DD3

45 mA 55 mA 45 mA 55 mA 45 mA 55 mA

Device Deselected

All inputs

V

SS

+ 0.10 V

≥ VIN ≥

V

DD

– 0.10 V

Rev: 1.01 7/2002 22/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

AC Electrical Characteristics

Parameter Symbol

-333 -300 -250
Unit Notes

Min Max Min Max Min Max

Clock Cycle Time tKHKH 3.0 — 3.3 — 4.0 — ns —

Clock High Time tKHKL 1.2 — 1.3 — 1.5 — ns —

Clock Low Time tKLKH 1.2 — 1.3 — 1.5 — ns —

Clock High to Echo Clock Low-Z tKHCX1 0.5 — 0.5 — 0.5 — ns 2

Clock High to Echo Clock High tKHCH 0.5 1.5 0.5 1.7 0.5 2.0 ns —

Echo Clock High Time tCHCL tKHKL +/- 200 ps tKHKL +/- 250 ps ns 2

Clock Low to Echo Clock Low tKLCL 0.5 1.5 0.5 1.7 0.5 2.0 ns

Echo Clock Low Time tCLCH tKHKL +/- 200 ps tKHKL +/- 250 ps ns 2

Clock High to Echo Clock High-Z tKHCZ 0.5 1.5 0.5 1.7 0.5 2.0 ns 1, 2

Clock High to Output in Low-Z tKHQX1 0.5 — 0.5 — 0.5 — ns 1

Clock High to Output Valid tKHQV 1.6 1.8 2.1 ns —

Clock High to Output Invalid tKHQX 0.5 — 0.5 — 0.5 — ns —

Clock High to Output in High-Z tKHQZ 0.5 1.6 0.5 1.8 0.5 2.1 ns 1

Echo Clock High to Output Valid tCHQV — 0.4 — 0.4 — 0.5 ns 2

Echo Clock High to Output Invalid tCHQX -0.4 — -0.4 — -0.5 — ns 2

Address Valid to Clock High tAVKH 0.6 — 0.7 — 0.8 — ns —

Clock High to Address Don’t Care tKHAX 0.4 — 0.4 — 0.5 — ns —

Enable Valid to Clock High tEVKH 0.6 — 0.7 — 0.8 — ns —

Clock High to Enable Don’t Care tKHEX 0.4 — 0.4 — 0.5 — ns —

Write Valid to Clock High tWVKH 0.6 — 0.7 — 0.8 — ns —

Clock High to Write Don’t Care tKHWX 0.4 — 0.4 — 0.5 — ns —

Byte Write Valid to Clock High tBVKH 0.6 — 0.7 — 0.8 — ns —

Clock High to Byte Write Don’t Care tKHBX 0.4 — 0.4 — 0.5 — ns —

Data In Valid to Clock High tDVKH 0.6 — 0.7 — 0.8 — ns —

Clock High to Data In Don’t Care tKHDX 0.4 — 0.4 — 0.5 — ns —

ADV Valid to Clock High tadvVKH 0.6 — 0.7 — 0.8 — ns —

Clock High to ADV Don’t Care tKHadvX 0.4 — 0.4 — 0.5 — ns —

Notes:

1. Measured at 100 mV from steady state. Not 100% tested.

2. Guaranteed by design. Not 100% tested.

3. For any specific temperature and voltage tKHCZ < tKHCX1.

Rev: 1.01 7/2002 23/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Timing Parameter Key—Pipelined Read Cycle Timing

tKHQX

tKHQZ

tKHQX1

tKHQV

tAVKH

tKHAX

CK

A

DQ

tKHKH

tKLKH

tKHKL

CD

E

QB

CQ

tCHQV

tKHCH

tKHCX1

tKHCZ

= CQ High Z

tCLCHtCHCL

tCHQX

Rev: 1.01 7/2002 24/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Timing Parameter Key—Late Write Mode Control and Data In Timing

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V

DDI

. The JTAG output

drivers are powered by V

DDQ

.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to
V

DDI

. TDO should be left unconnected.

tKHnX

tnVKH

tAVKH

tKHAX

CK

A

AB

C

E1, E2, E3,

W, Bn, ADV

tKHDX

tDVKH

DA

DQ (Data In)

Note: tnVKH = tEVKH, tWVKH, tBVKH, etc. and tKHnX = tKHEX, tKHWX, tKHBX, etc.

DB

Rev: 1.01 7/2002 25/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP registers are serial shift registers that capture serial input data on the
rising edge of TCK and push serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.

TMS Test Mode Select In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.

TDI Test Data In In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the state
of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction
Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same
result as a logic one input level.

TDO Test Data Out Out

Output that is active depending on the state of the TAP state machine. Output changes in response
to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.

Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held
high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Rev: 1.01 7/2002 26/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads. This device will not
perform INTEST but can perform the preload portion of the SAMPLE/PRELOAD command.

ID Register Contents

Die

Revision

Code

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Bit # 31302928272625242322212019181716151413121110987654321 0

x72

0000000000000001100100011011001 1

x36

0000000000000001100000011011001 1

x18

0000000000000001101000011011001 1

Instruction Register

ID Code Register

Boundary Scan Register

012

012

····

31 30 29

012

···

······

n

0

Bypass Register

TDI

TDO

TMS

TCK

Test Access Port (TAP) Controller

Rev: 1.01 7/2002 27/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state, the Instruction Register is placed between TDI and TDO. In this state the
desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all
instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP
instruction set for this device is listed in the following table.

JTAG Tap Controller State Diagram

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc­tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Some Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified
in the BSDL file. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O
ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAP’s input
data capture set-up plus hold time (tTS plus tTH ). The RAM’s clock inputs need not be paused for any other TAP operation except capturing

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle

0

0

1

0

1

1

0

0

1

1

1

0

0

1

1

0

0

0

0

1

1

0 0

1

1

0

0

0

1

111

Rev: 1.01 7/2002 28/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the Boundary Scan Register
between the TDI and TDO pins. The Update-DR controller state transfers the contents of boundary scan cells into the holding register of
each cell associated with an output pin on the RAM.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM’s input pins (except CK); therefore, the RAM’s internal state is still determined by its
input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the state of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are sampled
and transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state. Boundary Scan Register con­tents may then be shifted serially through the register using the Shift-DR command or the controller can be skipped to the Update-DR com­mand. When the controller is placed in the Update-DR state, a RAM that has a fully compliant EXTEST function drives out the value of the
Boundary Scan Register location associated with which each output pin.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z/PRELOAD

The SAMPLE-Z instruction operates exactly like SAMPLE/PRELOAD except that loading the SAMPLE-Z instruction forces all the RAM’s
output drivers, except TDO, to an inactive drive state (high-Z).

RFU

These instructions are reserved for future use.

Rev: 1.01 7/2002 29/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

SAMPLE-Z/

PRELOAD

010

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all Data and Clock output drivers to High-Z.

1

Private 011 Private instruction. 1

SAMPLE/

PRELOAD

100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1

Private 101 Private instruction. 1

Private 110 Private instruction. 1

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in Test-Logic-Reset state.

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

Test Port Input High Voltage

V

IHT

0.65 * V

DDI

V

DDI

+0.3

V1

Test Port Input Low Voltage

V

ILT

–0.3

0.35 * V

DDI

V1

TMS, TCK and TDI Input Leakage Current

I

INTH

–2 2 uA 2

TMS, TCK and TDI Input Leakage Current

I

INTL

–50 2 uA 3

TDO Output Leakage Current

I

OLT

–2 2 uA 4

Test Port Output High Voltage

V

OHT

VDD – 100 mV

—V5, 6

Test Port Output Low Voltage

V

OLT

— 100 mV V 7

Notes:

1. Input Under/overshoot voltage must be –1 V < Vi < V

DD

+ 1 V with a pulse width not to exceed 20% tTKC.

2. V

DDI ≥

V

IN

≥

VIL

3. 0 V

≤ V

IN

≤ V

IL

4. Output Disable, V

OUT

= 0 to V

DDI

5. The TDO output driver is served by the V

DDQ

supply.

6. I

OH

= –100 uA

7. I

OL

= +100 uA

Rev: 1.01 7/2002 30/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

JTAG Port Timing Diagram

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 50 — ns

TCK Low to TDO Valid tTKQ — 10 ns

TCK High Pulse Width tTKH 20 — ns

TCK Low Pulse Width tTKL 20 — ns

TDI & TMS Set Up Time tTS 5 — ns

TDI & TMS Hold Time tTH 5 — ns

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

JTAG Port AC Test Conditions

Parameter Conditions

Input high level

V

DDI

– 200 mV

Input low level 200 mV

Input slew rate 1 V/ns

Input reference level

V

DDI

/2

Output reference level

V

DDQ

/2

DQ

V

T

= V

DDQ

/2

50Ω

JTAG Port AC Test Load

tTKQ

tTS tTH

tTKH

tTKL

TCK

TMS

TDI

TDO

tTKC

Rev: 1.01 7/2002 31/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

209 BGA Package Drawing

14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array

Symbol Min Typ Max Units

A 1.70 mm

A1

0.40 0.50 0.60 mm

∅b 0.50 0.60 0.70 mm

c 0.31 0.36 0.38 mm

D

21.9 22.0 22.1 mm

D1 18.0 (BSC) mm

E 13.9 14.0 14.1 mm

E1

10.0 (BSC) mm

e

1.00 (BSC) mm

aaa

0.15 mm

Rev 1.0

A

A1

C

∅b

e

e

E

E1

D1

D

aaa

Bottom View

Side View

Rev: 1.01 7/2002 32/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Ordering Information—GSI SigmaRAM

Org

Part Number

1

Type Package

Speed

2

(MHz)

T

A

3

256K x 72 GS8170LW72C-333

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 333 C

256K x 72 GS8170LW72C-300

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 300 C

256K x 72 GS8170LW72C-250

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 250 C

256K x 72 GS8170LW72C-333I

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209 Pin BGA 333 I

256K x 72 GS8170LW72C-300I

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 300 I

256K x 72 GS8170LW72C-250I

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 250 I

512K x 36 GS8170LW36C-333

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 333 C

512K x 36 GS8170LW36C-300

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 300 C

512K x 36 GS8170LW36C-250

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 250 C

512K x 36 GS8170LW36C-333I

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 333 I

512K x 36 GS8170LW36C-300I

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 300 I

512K x 36 GS8170LW36C-250I

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 250 I

1Mx 18 GS8170LW18C-333

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 333 C

1Mx 18 GS8170LW18C-300

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 300 C

1Mx 18 GS8170LW18C-250

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 250 C

1Mx 18 GS8170LW18C-333I

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 333 I

1Mx 18 GS8170LW18C-300I

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 300 I

1Mx 18 GS8170LW18C-250I

Σ

1x1Lp Late Write ΣRAM

1 mm Pitch, 209-Pin BGA 250 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS817x72C-300T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode.

3. T

A

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

Rev: 1.01 7/2002 33/33 © 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

18Mb Sync ΣRAM Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes
Format or Content

Page;Revisions;Reason

8170LW18_r1

• Creation of new datasheet

8170LW18_r1;

8170LW18_r1_01

Content

• Removed all references to FT mode