GSI GS74116AX-8I, GS74116AX-8, GS74116AX-7I, GS74116AX-7, GS74116AJ-8I Datasheet

GS74116ATP/J/X

SOJ, TSOP, FP-BGA

256K x 16

Commercial Temp
Industrial Temp

4Mb Asynchronous SRAM

Features

• Fast access time: 7, 8, 10, 12 ns

• CMOS low power operation: 150/130/105/95 mA at
minimum cycle time

• Single 3.3 V power supply

• All inputs and outputs are TTL-compatible

• Byte control

• Fully static operation

• Industrial Temperature Option: –40° to 85°C

• Package line up

J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
X: 6 mm x 10 mm Fine Pitch Ball Grid Array
package

Description

The GS74116A is a high speed CMOS Static RAM organized
as 262,144 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL­compatible. The GS74116A is available in a 6 x 10 mm Fine
Pitch BGA package, 400 mil SOJ and 400 mil TSOP Type-II
packages.

7, 8, 10, 12 ns

3.3 V V

Center VDD and V

SOJ 256K x 16-Pin Configuration (Package J)

A
A
A
A
A

CE
DQ
DQ
DQ
DQ

V

DD

V

SS

DQ
DQ6
DQ7
DQ

WE
A
A
A

A

12

A

4

3

2

1

0

1

2

3

4

5

8

15

14

13

16

1
2
3
4
5
6
7
8
9
10
11
12

13
14
15

16
17
18

19
20
21
22

Top view

44-pin

SOJ

44
43
42
41
40
39
38
37
36
35
34
33
32
31

30

29
28

27

26
25

24
23

A
A
A
OE
UB
LB
DQ
DQ
DQ

DQ
V
V
DQ
DQ
DQ
DQ
NC
A
A
A
A
A

DD

SS

5

6

7

16

15

14

13

SS

DD

12

11

10

9

8

9

10

11

17

Pin Descriptions

Symbol Description

FP-BGA 256K x 16 Bump Configuration (Package X)

123456

A0–A17 Address input

–DQ

CE

LB

UB

WE

OE

V

V

DD

SS

16

Data input/output

ALBOE A

0

1

A

A2NC

Chip enable input

Lower byte enable input

(DQ1 to DQ8)

Upper byte enable input

(DQ9 to DQ16)

Write enable input

Output enable input

+3.3 V power supply

Ground

16

BDQ

UB A

CDQ14DQ15A

DVSSDQ13A

EVDDDQ12NC A16DQ5V

FDQ11DQ10A

GDQ9NC A

HNCA12A

3

A4CE DQ

5

A6DQ2DQ

17

A7DQ4V

8

A9DQ7DQ

10A11

13A14A15

WE DQ

1

3

DD

SS

6

8

NC

DQ1

NC No connect

6 x 10 mm Bump Pitch

Rev: 1.03 10/2002 1/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TSOP-II 256K x 16 Pin Configuration (Package TP)

GS74116ATP/J/X

Top View

DQ
DQ
DQ
DQ

V

V

DQ
DQ
DQ
DQ

WE
A

A14

A

A

A

CE

A

4

A

3

A

2

A

1

A

0

1

2

3

4

DD

SS

5

6

7

8

15

13

12

16

1
2
3
4
5
6
7
8
9
10
11
12

13
14
15

16
17
18

19
20
21
22

Top view

44 pin

TSOP II

44
43
42
41
40
39
38
37
36
35
34
33
32
31

30

29
28

A

5

A

6

A

7

OE
UB
LB
DQ

16

DQ

15

DQ

14

DQ

13

V

SS

V

DD

DQ

12

DQ

11

DQ

10

DQ

9

NC

27

A

26

25

24

23

8

A

9

A

10

A

11

A

17

Block Diagram

A

A

CE

WE

OE

UB
LB

0

17

_____

_____

Address

Input

Buffer

Control

Row

Decoder

Memory Array

Column
Decoder

I/O Buffer

DQ

1

DQ

16

Rev: 1.03 10/2002 2/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Truth Table

GS74116ATP/J/X

CE OE WE LB UB DQ1 to DQ

8

DQ9 to DQ

16

H X X X X Not Selected Not Selected ISB1, ISB

L L Read Read

LLH

L H Read High Z

H L High Z Read

LL Write Write

LXL

L H Write Not Write, High Z

H L Not Write, High Z Write

L H H X X High Z High Z

L X X H H High Z High Z

Note: X: “H” or “L”

Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage V

DD

–0.5 to +4.6 V

VDD Current

2

DD

I

Input Voltage V

Output Voltage V

IN

OUT

–0.5 to V

(≤ 4.6 V max.)

–0.5 to V

(≤ 4.6 V max.)

DD

DD

+0.5

+0.5

V

V

Allowable power dissipation PD 0.7 W

Storage temperature T

STG –55 to 150

o

C

Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec­ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.

Rev: 1.03 10/2002 3/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

GS74116ATP/J/X

Supply Voltage for -7/-8/-10/-12

Input High Voltage V

Input Low Voltage V

Ambient Temperature,

Commercial Range

Ambient Temperature,

Industrial Range

V

DD

IH

IL

T

Ac

I

T

A

3.0 3.3 3.6 V

2.0 —

–0.3 — 0.8 V

0—70

–40 — 85

Note:

1. Input overshoot voltage should be less than V

+2 V and not exceed 20 ns.

DD

2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.

Capacitance

Parameter Symbol Test Condition Max Unit

Input Capacitance CIN VIN = 0 V 5 pF

Output Capacitance C

Notes:

1. Tested at T

A = 25°C, f = 1 MHz

2. These parameters are sampled and are not 100% tested.

OUT

OUT

V

= 0 V 7 pF

V

DD

+0.3

V

o

C

o

C

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage

Current

Output Leakage

Current

Output High Voltage V

Output Low Voltage V

IIL

I

LO

OH IOH = –4 mA 2.4 —

OL ILO = +4 mA — 0.4 V

Rev: 1.03 10/2002 4/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

VIN = 0 to V

Output High Z

V

OUT = 0 to V

DD

DD

– 1 uA 1 uA

–1 uA 1 uA

Power Supply Currents

Parameter Symbol Test Conditions

CE ≤ VIL

Operating

Supply

Current

Standby

Current

Standby

Current

I

I

I

SB1

SB2

DD

All other inputs

≥ V

IH or ≤ VIL

Min. cycle time

I

OUT = 0 mA

CE ≥ V

All other inputs

≥ V

IH

Min. cycle time

CE ≥ V

All other inputs

≥ V

DD

– 0.2 V or ≤ 0.2 V

or ≤ V

DD

– 0.2V

GS74116ATP/J/X

0 to 70°C –40 to 85°C

7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns

150 130 105 90 160 140 115 100 mA

IH

IL

40 30 25 25 50 40 35 35 mA

10 20 mA

Unit

AC Test Conditions

Parameter Conditions

Input high level VIH = 2.4 V

Input low level V

Input rise time tr = 1 V/ns

Input fall time tf = 1 V/ns

Input reference level 1.4 V

Output reference level 1.4 V

Output load Fig. 1& 2

Note:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output load 2 for t

LZ

, tHZ, t

OLZ

and t

OHZ

IL = 0.4 V

DQ

Output Load 1

VT = 1.4 V

Output Load 2

DQ

5pF

1

50Ω

3.3 V

589Ω

434Ω

30pF

1

Rev: 1.03 10/2002 5/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.