GSI GS74108TP-15, GS74108TP-12I, GS74108TP-12, GS74108TP-10I, GS74108TP-10 Datasheet

GS74108TP/J

SOJ, TSOP

512K x 8

Commercial Temp
Industrial Temp

4Mb Asynchronous SRAM

Features

• Fast access time: 8, 10, 12, 15ns

• CMOS low power operation: 150/125/110/90 mA at min. cycle time.

• Single 3.3V ± 0.3V power supply

• All inputs and outputs are TTL compatible

• Fully static operation

• Industrial Temperature Option: -40° to 85°C

• Package line up
J: 400mil, 36 pin SOJ package
TP: 400mil, 44 pin TSOP Type II package

Description

The GS74108 is a high speed CMOS static RAM organized as
524,288-words by 8-bits. Static design eliminates the need for exter­nal clocks or timing strobes. Operating on a single 3.3V power supply
and all inputs and outputs are TTL compatible. The GS74108 is avail­able in 400 mil SOJ and 400 mil TSOP Type-II packages.

Pin Descriptions

Symbol Description

A0 to A18

DQ1 to DQ8 Data input/output

CE Chip enable input

WE Write enable input

OE Output enable input

VDD +3.3V power supply

VSS Ground

NC No connect

Address input

SOJ 512K x 8 Pin Configuration

A4

A3

A2

A1

A0

CE

DQ1

DQ2

VDD

VSS

DQ3

DQ4

WE

A17

A16

A15

A14

A13

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

36 pin

400mil SOJ

8, 10, 12, 15ns

3.3V VDD

Center VDD & VSS

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19 NC

NC

A5

A6

A7

A8

OE

DQ8

DQ7

VSS

VDD

DQ6

DQ5

A9

A10

A11

A12

A18

Rev: 1.06 7/2000 1/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TSOP-II 512K x 8 Pin Configuration

GS74108TP/J

NC
NC

A4
A3
A2

A1
A0
CE
DQ1
DQ2

VDD

VSS
DQ3
DQ4

WE

A17
A16

A15
A14

A13

NC
NC

1
2
3
4

5
6

7

8
9

10
11

12

13
14

15

16
17

18

19
20

21

22

44 pin

400mil TSOP II

44
43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

NC
NC

NC
A5

A6
A7

A8
OE
DQ8

DQ7

VSS
VDD
DQ6
DQ5

A9
A10
A11

A12
A18

NC

NC
NC

Block Diagram

A0

A18

CE

WE

OE

Address

Input

Buffer

Control

Row

Decoder

Memory Array

Column
Decoder

I/O Buffer

DQ1

DQ8

Rev: 1.06 7/2000 2/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Truth Table

CE OE WE DQ1 to DQ8 VDD Current

H X X Not Selected ISB1, ISB2

L L H Read

L H H High Z

Note: X: “H” or “L”

Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage VDD -0.5 to +4.6 V

GS74108TP/J

IDDL X L Write

Input Voltage VIN

Output Voltage VOUT

Allowable power dissipation PD 0.7 W

Storage temperature TSTG -55 to 150

Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

-0.5 to VDD+0.5

(≤ 4.6V max.)

-0.5 to VDD+0.5

(≤ 4.6V max.)

V

V

o

C

Rev: 1.06 7/2000 3/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply Voltage for -10/12/15 VDD 3.0 3.3 3.6 V

Supply Voltage for -8 VDD 3.135 3.3 3.6 V

Input High Voltage VIH 2.0 - VDD+0.3 V

Input Low Voltage VIL -0.3 - 0.8 V

GS74108TP/J

Ambient Temperature,

Commercial Range

Ambient Temperature,

Industrial Range

Note:

1. Input overshoot voltage should be less than VDD+2V and not exceed 20ns.

2. Input undershoot voltage should be greater than -2V and not exceed 20ns.

TAc 0 - 70

TAI -40 - 85

Capacitance

Parameter Symbol Test Condition Max Unit

Input Capacitance CIN VIN=0V 5 pF

Output Capacitance COUT VOUT=0V 7 pF

Notes:

1. Tested at TA=25°C, f=1MHz

2. These parameters are sampled and are not 100% tested

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Min Max

o

C

o

C

Input Leakage

Current

Output Leakage

Current

Output High Voltage VOH IOH = - 4mA 2.4

Output Low Voltage VOL ILO = + 4mA 0.4V

Rev: 1.06 7/2000 4/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

IIL VIN = 0 to VDD -1uA 1uA

ILO

Output High Z

VOUT = 0 to VDD

-1uA 1uA

Power Supply Currents

Parameter Symbol Test Conditions

CE ≤ VIL

Operating

Supply

Current

Standby

Current

IDD

ISB1

All other inputs

≥ VIH or ≤ VIL

Min. cycle time

IOUT = 0 mA

CE ≥ VIH

All other inputs

≥ VIH or ≤VIL

Min. cycle time

GS74108TP/J

0 to 70°C -40 to 85°C

8ns 10ns 12ns 15ns 10ns 12ns 15ns

150mA 125mA 110mA 90mA 135mA 120mA 100mA

70mA 65mA 60mA 55mA 75mA 70mA 65mA

Standby

Current

ISB2

CE ≥ VDD - 0.2V

All other inputs

≥ VDD - 0.2V or ≤ 0.2V

AC Test Conditions

Parameter Conditions

Input high level VIH=2.4V

Input low level VIL=0.4V

Input rise time tr=1V/ns

Input fall time tf=1V/ns

Input reference level 1.4V

Output reference level 1.4V

Output load Fig. 1& 2

Note:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted

3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ.

30mA 40mA

Output Load 1

DQ

Output Load 2

DQ

VT=1.4V

1

5pF

50Ω

3.3V

589Ω

434Ω

30pF

1

Rev: 1.06 7/2000 5/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Characteristics

Read Cycle

Parameter Symbol

Read cycle time tRC 8 --- 10 --- 12 --- 15 --- ns

Address access time tAA --- 8 --- 10 --- 12 --- 15 ns

Chip enable access time (CE) tAC --- 8 --- 10 --- 12 --- 15 ns

Output enable to output valid (OE) tOE --- 3.5 --- 4 --- 5 --- 6 ns

Output hold from address change tOH 3 --- 3 --- 3 --- 3 --- ns

GS74108TP/J

-8 -10 -12 -15
Unit

Min Max Min Max Min Max Min Max

Chip enable to output in low Z (CE)

Output enable to output in low Z (OE)

Chip disable to output in High Z (CE)

Output disable to output in High Z (OE)

* These parameters are sampled and are not 100% tested

Read Cycle 1: CE = OE = VIL, WE = V

Address

Data Out Previous Data Data valid

IH

tLZ

tOLZ

tHZ

tOHZ

tOH

*

*

*

*

3 --- 3 --- 3 --- 3 --- ns

0 --- 0 --- 0 --- 0 --- ns

--- 4 --- 5 --- 6 --- 7 ns

--- 3.5 --- 4 --- 5 --- 6 ns

tRC

tAA

Rev: 1.06 7/2000 6/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS74108TP/J

Read Cycle 2: WE = V

Write Cycle

Parameter Symbol

IH

Address

CE

OE

Data Out

High impedance

tRC

tAA

tAC

tLZ

tOLZ

tOE

DATA VALID

tHZ

tOHZ

-8 -10 -12 -15

Min Max Min Max Min Max Min Max

Unit

Write cycle time tWC 8 --- 10 --- 12 --- 15 --- ns

Address valid to end of write tAW 5.5 --- 7 --- 8 --- 10 --- ns

Chip enable to end of write tCW 5.5 --- 7 --- 8 --- 10 --- ns

Data set up time tDW 4 --- 5 --- 6 --- 7 --- ns

Data hold time tDH 0 --- 0 --- 0 --- 0 --- ns

Write pulse width tWP 5.5 --- 7 --- 8 --- 10 --- ns

Address set up time tAS 0 --- 0 --- 0 --- 0 --- ns

Write recovery time (WE) tWR 0 --- 0 --- 0 --- 0 --- ns

Write recovery time (CE) tWR1 0 --- 0 --- 0 --- 0 --- ns

Output Low Z from end of write

Write to output in High Z

* These parameters are sampled and are not 100% tested

tWLZ

tWHZ

*

3 --- 3 --- 3 --- 3 --- ns

*

--- 3.5 --- 4 --- 5 --- 6 ns

Rev: 1.06 7/2000 7/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Write Cycle 1: WE control

Address

GS74108TP/J

tWC

CE

WE

Data In

Data Out

Write Cycle 2: CE control

Address

OE

CE

OE

tAW

tCW

tAS tWP

tWC

tAW

tAS tCW

tWR

tDW tDH

DATA VALID

tWLZtWHZ

HIGH IMPED ANCE

tWR1

tWP

WE

tDW tDH

Data In

Data Out

DATA VALID

HIGH IMPED ANCE

Rev: 1.06 7/2000 8/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

36 Pin SOJ, 400 mil

A

1

A2

A1

GS74108TP/J

Dimension in inch Dimension in mm

Symbol

L

D

E

e

y

B

B1

HE

c

A

Detail A

GE

Q

Note:

1. Dimension D& E do not include interlead flash

2. Dimension B1 does not include dambar protrusion / intrusion

3. Controlling dimension: inches

min nom max min nom max

A - - 0.146 - - 3.70

A1 0.026 - - 0.66 - -

A2 0.105 0.110 0.115 2.67 2.80 2.92

B 0.013 0.017 0.021 0.33 0.43 0.53

B1 0.024 0.028 0.032 0.61 0.71 0.81

c 0.006 0.008 0.012 0.15 0.20 0.30

D 0.920 0.924 0.929 23.37 23.47 23.60

E 0.395 0.400 0.405 10.04 10.16 10.28

e - 0.05 - - 1.27 -

HE 0.430 0.435 0.440 10.93 11.05 11.17

GE 0.354 0.366 0.378 9.00 9.30 9.60

L 0.082 - - 2.08 - -

y - - 0.004 - - 0.10

Q

o

0

-

10

o

o

0

-

10

o

Rev: 1.06 7/2000 9/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

44 Pin, 400 mil TSOP-II

3.

Controlling dimension: mm

1 22

A

A1 A2

e

y

GS74108TP/J

Dimension in inch Dimension in mm

D

2344

E

HE

B

L1

c

Q

Detail A

Symbol

A1 0.002 - - 0.05 - -

A

L

A2 0.037 0.039 0.041 0.95 1.00 1.05

HE 0.455 0.463 0.471 11.56 11.76 11.96

L1 - 0.031 - - 0.80 -

Note:

1. Dimension D& E do not include interlead flash

2. Dimension B does not include dambar protrusion / intrusion

min nom max min nom max

A - - 0.047 - - 1.20

B 0.01 0.014 0.018 0.25 0.35 0.45

c - 0.006 - - 0.15 -

D 0.721 0.725 0.729 18.31 18.41 18.51

E 0.396 0.400 0.404 10.06 10.16 10.26

e - 0.031 - - 0.80 -

L 0.016 0.020 0.024 0.40 0.50 0.60

y - - 0.004 - - 0.10

Q

o

0

-

o

o

5

0

-

o

5

Rev: 1.06 7/2000 10/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Ordering Information

GS74108TP/J

Part Number

GS74108TP-8 400 mil TSOP-II 8 ns Commercial

GS74108TP-10 400 mil TSOP-II 10 ns Commercial

GS74108TP-12 400 mil TSOP-II 12 ns Commercial

GS74108TP-15 400 mil TSOP-II 15 ns Commercial

GS74108TP-8I 400 mil TSOP-II 8 ns Industrial

GS74108TP-10I 400 mil TSOP-II 10 ns Industrial

GS74108TP-12I 400 mil TSOP-II 12 ns Industrial

GS74108TP-15I 400 mil TSOP-II 15 ns Industrial

GS74108J-8 400 mil SOJ 8 ns Commercial

GS74108J-10 400 mil SOJ 10 ns Commercial

GS74108J-12 400 mil SOJ 12 ns Commercial

GS74108J-15 400 mil SOJ 15 ns Commercial

GS74108J-8I 400 mil SOJ 8 ns Industrial

GS74108J-10I 400 mil SOJ 10 ns Industrial

*

Package Access Time Temp. Range Status

GS74108J-12I 400 mil SOJ 12 ns Industrial

GS74108J-15I 400 mil SOJ 15 ns Industrial

*

Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS74108TP-8T

Rev: 1.06 7/2000 11/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Revision History

GS74108TP/J

Rev. Code: Old;

New

741081.04d 5/1999/741081.05 1/
2000 Content

GS74108Rev1.05 10/19991/
2000K;Rev 5 2/2000L

Types of Changes

Format or Content

Format/Content

Page #/Revisions/Reason

1. Page 2/Pins 16 - 20 and 26 - 30 on 44 pin TSOP II Pin Configuration/
Correction.

1. GSI Logo

2.

Rev: 1.06 7/2000 12/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.