GSI GS74104TP-8I, GS74104TP-8, GS74104TP-15I, GS74104TP-15, GS74104TP-12I Datasheet

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GS74104TP/J
SOJ, TSOP
1M x 4
Commercial Temp Industrial Temp
4Mb Asynchronous SRAM
Features
• Fast access time: 8, 10, 12, 15 ns
• CMOS low power operation: 150/125/110/90 mA at minimum cycle time.
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 32-pin SOJ package TP: 400 mil, 44-pin TSOP Type II package
Description
The GS74104 is a high speed CMOS Static RAM organized as 1,048,576 words by 4 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single
3.3 V power supply and all inputs and outputs are TTL-com-
patible. The GS74104 is available in 400 mil SOJ and 400 mil TSOP Type-II packages.
Center VDD and V
SOJ 1M x 4-Pin Configuraton
A4 A3 A2 A1 A0 CE DQ1 V
DD
V
SS
DQ2 WE A19 A18 A17 A16 A15
TSOP-II 1M x 4-Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-pin
400 mil SOJ
8, 10, 12, 15 ns
3.3 V V
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A5 A6 A7 A8 A9 OE DQ4 V V DQ3 A10 A11 A12 A13 A14 NC
DD
SS
SS DD
Pin Descriptions
Symbol Description
A0–A19 Address input
DQ1–DQ4 Data input/output
CE Chip enable input WE Write enable input OE Output enable input
V
DD
V
SS
NC No connect
+3.3 V power supply
Ground
NC NC NC A4 A3 A2 A1 A0 CE DQ1 V
DD
V
SS
DQ2 WE A19 A18 A17 A16
A15 NC
NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
19 20 21 22
44-pin
400 mil TSOP II
44 43
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
24 23
NC NC NC A5 A6 A7 A8 A9 OE DQ4 V
SS
V
DD
DQ3 A10 A11 A12 A13 A14 NC NC
NC NC
Rev: 1.07 1/2001 1/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Block Diagram
GS74104TP/J
A0
A19
CE
WE
OE
Address
Input
Buffer
Control
Row
Decoder
Memory Array
Column Decoder
I/O Buffer
DQ1
DQ4
Truth Table
CE OE WE DQ1 to DQ8
H X X Not Selected ISB1, ISB2
L L H Read
VDD Current
IDDL X L Write
L H H High Z
Note: X: “H” or “L”
Rev: 1.07 1/2001 2/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply Voltage VDD –0.5 to +4.6 V
GS74104TP/J
Input Voltage VIN
Output Voltage VOUT
–0.5 to V
(4.6 V max.)
–0.5 to V
(4.6 V max.)
DD
DD
+0.5
+0.5
V
V
Allowable power dissipation PD 0.7 W
Storage temperature TSTG –55 to 150
o
C
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec­ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply Voltage for -10/12/15
Supply Voltage for -8
Input High Voltage VIH 2.0
Input Low Voltage VIL –0.3 0.8 V
V
DD
V
DD
3.0 3.3 3.6 V
3.135 3.3 3.6 V VDD +0.3
V
Ambient Temperature,
Commercial Range
Ambient Temperature,
Industrial Range
TAc 0 70
TAI –40 85
o
C
o
C
Note:
1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Rev: 1.07 1/2001 3/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Capacitance
Parameter Symbol Test Condition Max Unit
Input Capacitance CIN VIN = 0 V 5 pF
Output Capacitance COUT VOUT = 0 V 7 pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter Symbol Test Conditions Min Max
GS74104TP/J
Input Leakage
Current
Output Leakage
Current
Output High Voltage VOH IOH = –4mA 2.4
Output Low Voltage VOL ILO = +4mA 0.4 V
IIL
ILO
VIN = 0 to V
Output High Z
VOUT = 0 to V
DD
DD
– 1 uA 1 uA
–1 uA 1 uA
Rev: 1.07 1/2001 4/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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