GSI GS72116AU-8I, GS72116AU-8, GS72116AU-7, GS72116AU-15I, GS72116AU-15 Datasheet
...
Rev: 1.04a 10/2002 1/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
128K x 16
2Mb Asynchronous SRAM
7, 8, 10, 12 ns
3.3 V V
DD
Center VDD and V
SS
SOJ, TSOP, FP-BGA, TQFP
Commercial Temp
Industrial Temp
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
T: 10 mm x 10 mm, 44-pin TQFP
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
Description
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS72116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as
well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
Pin Descriptions
SOJ 128K x 16-Pin Configuration
Package J
Symbol Description
A0–A16 Address input
DQ1
–DQ
16
Data input/output
CE
Chip enable input
LB
Lower byte enable input
(DQ1 to DQ8)
UB
Upper byte enable input
(DQ9 to DQ16)
WE
Write enable input
OE
Output enable input
V
DD
+3.3 V power supply
V
SS
Ground
NC No connect
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ6
DQ7
DQ
8
WE
A
15
A
14
A
13
A
5
A
6
A
7
OE
UB
LB
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
8
A
9
A
10
Top view
21
22
24
23
A
12
A
11
44-pin
SOJ
NCA
16
Rev: 1.04a 10/2002 2/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin TQFP 128K x 16-Pin Configuration
Package T
Fine Pitch BGA 128K x 16-Bump Configuration
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Package U
123456
ALB
OE A
0
A
1
A2NC
BDQ16UB A
3
A4CE DQ
1
CDQ14DQ15A
5
A6DQ2DQ
3
D
V
SS
DQ13NC A7DQ
4
V
DD
E
V
DD
DQ12NC A16DQ
5
V
SS
FDQ11DQ10A
8
A9DQ7DQ
6
GDQ9NC A
10A11
WE DQ
8
HNCA12A
13A14A15
NC
A16A15A14A13A12A11A10A9OE UB LB
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ
6
DQ
7
DQ
8
DQ
16
WE A0A1A2A3A4NC A5A6A7A
8
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
Rev: 1.04a 10/2002 3/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
TSOP-II 128K x 16-Pin Configuration
Package TP
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ
6
DQ
7
DQ
8
WE
A
15
A14
A
13
A
5
A
6
A
7
OE
UB
LB
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
8
A
9
A
10
Top view
21
22
24
23
A
12
A
11
44-pin
TSOP II
NCA
16
Memory Array
Row
Decoder
Column
Decoder
Address
Input
Buffer
Control
I/O Buffer
A
0
CE
WE
OE
DQ
1
A
16
Block Diagram
DQ
16
UB
_____
LB
_____
Rev: 1.04a 10/2002 4/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Note: X: “H” or “L”
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Truth Table
CE OE WE LB UB DQ1 to DQ
8
DQ9 to DQ
16
VDD Current
H X X X X Not Selected Not Selected ISB1, ISB
2
LLH
L L Read Read
I
DD
L H Read High Z
H L High Z Read
LXL
LL Write Write
L H Write Not Write, High Z
H L Not Write, High Z Write
L H H X X High Z High Z
L X X H H High Z High Z
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply Voltage V
DD
–0.5 to +4.6 V
Input Voltage V
IN
–0.5 to V
DD
+0.5
(≤ 4.6 V max.)
V
Output Voltage V
OUT
–0.5 to V
DD
+0.5
(≤ 4.6 V max.)
V
Allowable power dissipation PD 0.7 W
Storage temperature T
STG –55 to 150
o
C
Rev: 1.04a 10/2002 5/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Note:
1. Input overshoot voltage should be less than V
DD
+2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Notes:
1. Tested at T
A = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply Voltage for -7/-8/-10/12
V
DD
3.0 3.3 3.6 V
Input High Voltage V
IH
2.0 —
V
DD
+0.3
V
Input Low Voltage V
IL
–0.3 — 0.8 V
Ambient Temperature,
Commercial Range
T
Ac
0 — 70
o
C
Ambient Temperature,
Industrial Range
T
A
I
–40 — 85
o
C
Capacitance
Parameter Symbol Test Condition Max Unit
Input Capacitance CIN VIN = 0 V 5 pF
Output Capacitance C
OUT
V
OUT
= 0 V 7 pF
DC I/O Pin Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage
Current
IIL
VIN = 0 to V
DD
– 1 uA 1 uA
Output Leakage
Current
I
LO
Output High Z
V
OUT = 0 to V
DD
–1 uA 1 uA
Output High Voltage V
OH IOH = –4mA 2.4 —
Output Low Voltage V
OL ILO = +4mA — 0.4 V
Rev: 1.04a 10/2002 6/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
AC Test Conditions
Power Supply Currents
Parameter Symbol Test Conditions
0 to 70°C –40 to 85°C
7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns
Operating
Supply
Current
IDD (max)
CE ≤ VIL
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
145 mA 125 mA 100 mA 85 mA 150 mA 130 mA 105 mA 90 mA
Standby
Current
ISB1
(max)
CE
≥ VIH
All other inputs
≥ VIH or ≤VIL
Min. cycle time
25 mA 20 mA 20 mA 15 mA 30 mA 25 mA 25 mA 20 mA
Standby
Current
ISB2
(max)
CE ≥ V
DD
– 0.2 V
All other inputs
≥ V
DD
– 0.2 V or
≤ 0.2 V
5 mA 10 mA
DQ
VT = 1.4 V
50Ω
30pF
1
DQ
3.3 V
Output Load 1
Output Load 2
589Ω
434Ω
5pF
1
Note:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in
Fig. 1
unless otherwise noted.
3. Output load 2 for t
LZ, tHZ, tOLZ and tOHZ
Parameter Conditions
Input high level V
IH
= 2.4 V
Input low level V
IL
= 0.4 V
Input rise time tr = 1 V/ns
Input fall time tf = 1 V/ns
Input reference level 1.4 V
Output reference level 1.4 V
Output load Fig. 1& 2
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