Rev: 1.04a 10/2002 1/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
128K x 16
2Mb Asynchronous SRAM
7, 8, 10, 12 ns
3.3 V V
DD
Center VDD and V
SS
SOJ, TSOP, FP-BGA, TQFP
Commercial Temp
Industrial Temp
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
T: 10 mm x 10 mm, 44-pin TQFP
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
Description
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS72116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as
well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
Pin Descriptions
SOJ 128K x 16-Pin Configuration
Package J
Symbol Description
A0–A16 Address input
DQ1
–DQ
16
Data input/output
CE
Chip enable input
LB
Lower byte enable input
(DQ1 to DQ8)
UB
Upper byte enable input
(DQ9 to DQ16)
WE
Write enable input
OE
Output enable input
V
DD
+3.3 V power supply
V
SS
Ground
NC No connect
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ6
DQ7
DQ
8
WE
A
15
A
14
A
13
A
5
A
6
A
7
OE
UB
LB
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
8
A
9
A
10
Top view
21
22
24
23
A
12
A
11
44-pin
SOJ
NCA
16
Rev: 1.04a 10/2002 2/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin TQFP 128K x 16-Pin Configuration
Package T
Fine Pitch BGA 128K x 16-Bump Configuration
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Package U
123456
ALB
OE A
0
A
1
A2NC
BDQ16UB A
3
A4CE DQ
1
CDQ14DQ15A
5
A6DQ2DQ
3
D
V
SS
DQ13NC A7DQ
4
V
DD
E
V
DD
DQ12NC A16DQ
5
V
SS
FDQ11DQ10A
8
A9DQ7DQ
6
GDQ9NC A
10A11
WE DQ
8
HNCA12A
13A14A15
NC
A16A15A14A13A12A11A10A9OE UB LB
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ
6
DQ
7
DQ
8
DQ
16
WE A0A1A2A3A4NC A5A6A7A
8
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
Rev: 1.04a 10/2002 3/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
TSOP-II 128K x 16-Pin Configuration
Package TP
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ
6
DQ
7
DQ
8
WE
A
15
A14
A
13
A
5
A
6
A
7
OE
UB
LB
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
8
A
9
A
10
Top view
21
22
24
23
A
12
A
11
44-pin
TSOP II
NCA
16
Memory Array
Row
Decoder
Column
Decoder
Address
Input
Buffer
Control
I/O Buffer
A
0
CE
WE
OE
DQ
1
A
16
Block Diagram
DQ
16
UB
_____
LB
_____
Rev: 1.04a 10/2002 4/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Note: X: “H” or “L”
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Truth Table
CE OE WE LB UB DQ1 to DQ
8
DQ9 to DQ
16
VDD Current
H X X X X Not Selected Not Selected ISB1, ISB
2
LLH
L L Read Read
I
DD
L H Read High Z
H L High Z Read
LXL
LL Write Write
L H Write Not Write, High Z
H L Not Write, High Z Write
L H H X X High Z High Z
L X X H H High Z High Z
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply Voltage V
DD
–0.5 to +4.6 V
Input Voltage V
IN
–0.5 to V
DD
+0.5
(≤ 4.6 V max.)
V
Output Voltage V
OUT
–0.5 to V
DD
+0.5
(≤ 4.6 V max.)
V
Allowable power dissipation PD 0.7 W
Storage temperature T
STG –55 to 150
o
C
Rev: 1.04a 10/2002 5/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Note:
1. Input overshoot voltage should be less than V
DD
+2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Notes:
1. Tested at T
A = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply Voltage for -7/-8/-10/12
V
DD
3.0 3.3 3.6 V
Input High Voltage V
IH
2.0 —
V
DD
+0.3
V
Input Low Voltage V
IL
–0.3 — 0.8 V
Ambient Temperature,
Commercial Range
T
Ac
0 — 70
o
C
Ambient Temperature,
Industrial Range
T
A
I
–40 — 85
o
C
Capacitance
Parameter Symbol Test Condition Max Unit
Input Capacitance CIN VIN = 0 V 5 pF
Output Capacitance C
OUT
V
OUT
= 0 V 7 pF
DC I/O Pin Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage
Current
IIL
VIN = 0 to V
DD
– 1 uA 1 uA
Output Leakage
Current
I
LO
Output High Z
V
OUT = 0 to V
DD
–1 uA 1 uA
Output High Voltage V
OH IOH = –4mA 2.4 —
Output Low Voltage V
OL ILO = +4mA — 0.4 V
Rev: 1.04a 10/2002 6/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
AC Test Conditions
Power Supply Currents
Parameter Symbol Test Conditions
0 to 70°C –40 to 85°C
7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns
Operating
Supply
Current
IDD (max)
CE ≤ VIL
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
145 mA 125 mA 100 mA 85 mA 150 mA 130 mA 105 mA 90 mA
Standby
Current
ISB1
(max)
CE
≥ VIH
All other inputs
≥ VIH or ≤VIL
Min. cycle time
25 mA 20 mA 20 mA 15 mA 30 mA 25 mA 25 mA 20 mA
Standby
Current
ISB2
(max)
CE ≥ V
DD
– 0.2 V
All other inputs
≥ V
DD
– 0.2 V or
≤ 0.2 V
5 mA 10 mA
DQ
VT = 1.4 V
50Ω
30pF
1
DQ
3.3 V
Output Load 1
Output Load 2
589Ω
434Ω
5pF
1
Note:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in
Fig. 1
unless otherwise noted.
3. Output load 2 for t
LZ, tHZ, tOLZ and tOHZ
Parameter Conditions
Input high level V
IH
= 2.4 V
Input low level V
IL
= 0.4 V
Input rise time tr = 1 V/ns
Input fall time tf = 1 V/ns
Input reference level 1.4 V
Output reference level 1.4 V
Output load Fig. 1& 2
Rev: 1.04a 10/2002 7/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
AC Characteristics
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = V
IL
Read Cycle
Parameter Symbol
-7 -8 -10 -12
Unit
Min Max Min Max Min Max Min Max
Read cycle time t
RC
7—8— 10 — 12 — ns
Address access time t
AA —7— 8 — 10 — 12 ns
Chip enable access time (CE
)tAC—7— 8 — 10 — 12 ns
Byte enable access time (UB
, LB)tAB—3— 3.5 — 4 — 5ns
Output enable to output valid (OE
)tOE —3— 3.5 — 4 — 5ns
Output hold from address change t
OH
3—3— 3 — 3 — ns
Chip enable to output in low Z (CE
)
t
LZ
*
3—3— 3 — 3 — ns
Output enable to output in low Z (OE
)
t
OLZ
*
0—0— 0 — 0 — ns
Byte enable to output in low Z (UB
, LB)
t
BLZ
*
0—0— 0 — 0 — ns
Chip disable to output in High Z (CE
)
t
HZ
*
—3.5— 4 — 5 — 6ns
Output disable to output in High Z (OE
)
t
OHZ
*
—3— 3.5 — 4 — 5ns
Byte disable to output in High Z (UB
, LB)
t
BHZ
*
—3— 3.5 — 4 — 5ns
tAA
t
OH
t
RC
Address
Data Out Previous Data Data valid
Rev: 1.04a 10/2002 8/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Read Cycle 2: WE = V
IH
* These parameters are sampled and are not 100% tested.
Write Cycle
Parameter Symbol
-7 -8 -10 -12
Unit
Min Max Min Max Min Max Min Max
Write cycle time tWC 7 — 8 — 10 — 12 — ns
Address valid to end of write tAW 5 — 5.5 — 7 — 8 — ns
Chip enable to end of write tCW 5 — 5.5 — 7 — 8 — ns
Byte enable to end of write tBW 5 — 5.5 — 7 — 8 — ns
Data set up time tDW 3.5 — 4 — 5 — 6 — ns
Data hold time tDH 0 — 0 — 0 — 0 — ns
Write pulse width tWP 5 — 5.5 — 7 — 8 — ns
Address set up time tAS 0 — 0 — 0 — 0 — ns
Write recovery time (WE
)tWR0—0— 0 — 0 — ns
Write recovery time (CE
)tWR10—0— 0 — 0 — ns
Output Low Z from end of write
tWLZ
*
3— 3— 3 — 3 — ns
Write to output in High Z
tWHZ
*
—3— 3.5 — 4 — 5ns
tAA
tRC
Address
tAC
tLZ
tAB
tBLZ
tOE
tOLZ
CE
UB, LB
OE
Data Out
tHZ
tBHZ
tOHZ
Data valid
High impedance
Rev: 1.04a 10/2002 9/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Write Cycle 1: WE control
Write Cycle 2: CE control
tWC
Address
CE
UB, LB
WE
Data In
OE
Data Out
tAW
tCW
tBW
tAS tWP
tWR
tDW tDH
tWLZtWHZ
Data valid
High impedance
tWC
Address
CE
UB, LB
WE
Data In
OE
Data Out
tAW
tWP
tAS tCW
tWR1
tDW tDH
Data valid
High impedance
tBW
Rev: 1.04a 10/2002 10/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Write Cycle 3: UB, LB control
tWC
Address
CE
UB, LB
WE
Data In
OE
Data Out
tAW
tWP
tAS tCW
tWR1
tDW tDH
Data valid
High impedance
tBW
Rev: 1.04a 10/2002 11/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin, 400 mil SOJ
122
2344
e
B1
D
A1
A2
y
E
H
E
Q
c
L
G
E
Detail A
A
B
A
Note:
1. Dimension D& E do not include interlead flash.
2. Dimension B1 does not include dambar protrusion/intrusion.
3. Controlling dimension: inches
Symbol
Dimension in inch Dimension in mm
min nom max min nom max
A ——0.148 ——3.759
A1 0.025 ——0.635 ——
A2 0.105 0.110 0.115 2.667 2.794 2.921
B — 0.018 ——0.457 —
B1 0.026 0.028 0.032 0.660 0.711 0.813
c — 0.008 ——0.203 —
D 1.120 1.125 1.130 28.44 28.58 28.70
E 0.395 0.400 0.405 10.033 10.160 10.287
e — 0.05 ——1.27 —
H
E
0.435 0.440 0.445 11.049 11.176 11.303
G
E 0.360 0.370 0.380 9.144 9.398 9.652
L 0.082 0.087 0.106 2.083 2.210 2.70
y ——0.004 ——0.102
Q
0
o
—
7
o
0
o
—
7
o
Rev: 1.04a 10/2002 12/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin, 400 mil TSOP-II
D
122
2344
e
B
Q
A
A1
A2
y
c
Detail A
E
H
E
L
L1
A
Note:
1. Dimension D& E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Controlling dimension: mm
Symbol
Dimension in inch Dimension in mm
min nom max min nom max
A ——0.047 ——1.20
A1 0.002 ——0.05 ——
A2 0.037 0.039 0.041 0.95 1.00 1.05
B 0.01 0.014 0.018 0.25 0.35 0.45
c — 0.006 ——0.15 —
D 0.721 0.725 0.729 18.31 18.41 18.51
E 0.396 0.400 0.404 10.06 10.16 10.26
e — 0.031 ——0.80 —
H
E
0.455 0.463 0.471 11.56 11.76 11.96
L 0.016 0.020 0.024 0.40 0.50 0.60
L1 — 0.031 ——0.80 —
y ——0.004 ——0.10
Q
0
o
—
5
o
0
o
—
5
o
Rev: 1.04a 10/2002 13/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin TQFP (LQFP) Package
Units: mm
Body Size
Lead Count
Standoff Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch
E1 D1 A1 A2 L1 b c e
10 10 44 0.1 1.4 1.0 0.3 0.127 0.8
e
L1
C
b
D1
A2
A1
E1
Rev: 1.04a 10/2002 14/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44 Pin TQFP (LQFP) Package
Units: mm
Body Size
Lead Count
Standoff Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch
E1 D1 A1 A2 L1 b c e
10 10 44 0.1 1.4 1.0 0.3 0.127 0.8
e
L1
C
b
D1
A2
A1
E1
Rev: 1.04a 10/2002 15/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
6 mm x 10 mm Fine Pitch BGA
C
5.25
0.75(typ).
3.75
pin A1 index
654321
A
B
D
E
F
G
H
0.22 ± 0.05
1.20(max)
0.36(typ)
Ball Dia. 0.35
Pitch 0.75
D
0.10
pin A1 index
Bottom View Top View
6.00 ± 0.10
8.00 ± 0.10
units: mm
Rev: 1.04a 10/2002 16/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Ordering Information
Part Number
*
Package Access Time Temp. Range Status
GS72116ATP-7 400 mil TSOP-II 7 ns Commercial
GS72116ATP-8 400 mil TSOP-II 8 ns Commercial
GS72116ATP-10 400 mil TSOP-II 10 ns Commercial
GS72116ATP-12 400 mil TSOP-II 12 ns Commercial
GS72116ATP-7I 400 mil TSOP-II 7 ns Industrial
GS72116ATP-8I 400 mil TSOP-II 8 ns Industrial
GS72116ATP-10I 400 mil TSOP-II 10 ns Industrial
GS72116ATP-12I 400 mil TSOP-II 12 ns Industrial
GS72116AJ-7 400 mil SOJ 7 ns Commercial
GS72116AJ-8 400 mil SOJ 8 ns Commercial
GS72116AJ-10 400 mil SOJ 10 ns Commercial
GS72116AJ-12 400 mil SOJ 12 ns Commercial
GS72116AJ-7I 400 mil SOJ 7 ns Industrial
GS72116AJ-8I 400 mil SOJ 8 ns Industrial
GS72116AJ-10I 400 mil SOJ 10 ns Industrial
GS72116AJ-12I 400 mil SOJ 12 ns Industrial
GS72116AT-7 44-pin TQFP 7 ns Commercial
GS72116AT-8 44-pin TQFP 8 ns Commercial
GS72116AT-10 44-pin TQFP 10 ns Commercial
GS72116AT-12 44-pin TQFP 12 ns Commercial
GS72116AT-7I 44-pin TQFP 7 ns Industrial
GS72116AT-8I 44-pin TQFP 8 ns Industrial
GS72116AT-10I 44-pin TQFP 10 ns Industrial
GS72116AT-12I 44-pin TQFP 12 ns Industrial
Rev: 1.04a 10/2002 17/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
*
Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:
GS72116ATP-8T
GS72116AU-7 6 mm x 8 mm Fine Pitch BGA 7 ns Commercial
GS72116AU-8 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial
GS72116AU-10 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial
GS72116AU-12 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial
GS72116AU-7I 6 mm x 8 mm Fine Pitch BGA 7 ns Industrial
GS72116AU-8I 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial
GS72116AU-10I 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial
GS72116AU-12I 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial
Ordering Information
Part Number
*
Package Access Time Temp. Range Status
Rev: 1.04a 10/2002 18/18 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
2Mb Asynchronous Datasheet Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
Page #/Revisions/Reason
72116A_r1
• Creation of new datasheet
72116A_r1; 72116A_r1_01 Content
• Added 6 ns speed bin to entire document
72116A_r1_01; 72116A_r1_02 Content
• Updated all power numbers
• Changed 6 mm x 10 mm FP_BGA package designator from U to X
72116A_r1_02; 72116A_r1_03 Content
• Updated Recommended Operating Conditions table on page 5
• Removed 15 ns bin
• Changed FPBGA package from 6 x 10 to 6 x 8 (package U)
72116A_r1_03; 72116A_r1_04 Content
• Removed 6 ns speed bin from entire document
• Added 7 ns speed bin to entire document
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