GSI GS72108AJ-7, GS72108AJ-15I, GS72108AJ-15, GS72108AJ-12I, GS72108AJ-12 Datasheet
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Rev: 1.04a 10/2002 1/12 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72108ATP/J
256K x 8
2Mb Asynchronous SRAM
7, 8, 10, 12 ns
3.3 V V
DD
Center VDD and V
SS
SOJ, TSOP
Commercial Temp
Industrial Temp
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 135/115/95/80 mA at minimum
cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 36-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
Description
The GS72108A is a high speed CMOS Static RAM organized
as 262,144 words by 8 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS72108A is available in 400 mil SOJ and
400 mil TSOP Type-II packages.
Pin Descriptions
SOJ 256K x 8-Pin Configuration
Package J
Symbol Description
A0–A
17
Address input
DQ
1–DQ8 Data input/output
CE
Chip enable input
WE
Write enable input
OE
Output enable input
V
DD
+3.3 V power supply
V
SS
Ground
NC No connect
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
V
DD
V
SS
DQ
3
DQ
4
WE
A
17
A
16
A
15
NC
A
5
A
6
A
7
A
8
OE
DQ
8
DQ
7
V
SS
V
DD
DQ
6
DQ
5
A
9
A
10
A
11
A
12
36-pin
400 mil SOJ
17
18
A
14
A
13
20
19
NC
NC
Rev: 1.04a 10/2002 2/12 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72108ATP/J
TSOP-II 256K x 8-Pin Configuration
Package TP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
V
DD
V
SS
DQ
3
DQ
4
WE
NC
A
5
A
6
A
7
A
8
OE
DQ
8
DQ
7
V
SS
V
DD
DQ
6
DQ
5
A
10
A
11
A
12
NC
44-pin
400 mil TSOP II
19
20
26
25
NC
21
22
NC
NC
24
23
NC
NC
1
2
NC
NC
44
43
NC
NC
A
9
A
13
A
17
A
16
A
15
A
14
Memory Array
Row
Decoder
Column
Decoder
Address
Input
Buffer
Control
I/O Buffer
A
0
CE
WE
OE
DQ
1
A
17
Block Diagram
DQ
8
Rev: 1.04a 10/2002 3/12 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72108ATP/J
Note: X: “H” or “L”
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Truth Table
CE OE WE DQ1 to DQ
8
VDD Current
H X X Not Selected ISB1, ISB
2
L L H Read
I
DD
LX L Write
LH H High Z
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply Voltage VDD –0.5 to +4.6 V
Input Voltage V
IN
–0.5 to V
DD
+0.5
(≤ 4.6 V max.)
V
Output Voltage V
OUT
–0.5 to V
DD
+0.5
(≤ 4.6 V max.)
V
Allowable power dissipation PD 0.7 W
Storage temperature T
STG
–55 to 150
o
C
Rev: 1.04a 10/2002 4/12 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72108ATP/J
Notes:
1. Input overshoot voltage should be less than V
DD
+2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Notes:
1. Tested at T
A = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply Voltage for -7/-8/-10/-12
V
DD
3.0 3.3 3.6 V
Input High Voltage V
IH
2.0 —
V
DD
+0.3
V
Input Low Voltage V
IL
–0.3 — 0.8 V
Ambient Temperature,
Commercial Range
T
Ac
0 — 70
o
C
Ambient Temperature,
Industrial Range
T
A
I
–40 — 85
o
C
Capacitance
Parameter Symbol Test Condition Max Unit
Input Capacitance CIN VIN = 0 V 5 pF
Output Capacitance C
OUT
V
OUT
= 0 V 7 pF
DC I/O Pin Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage
Current
IIL
VIN = 0 to V
DD
– 1 uA 1 uA
Output Leakage
Current
I
LO
Output High Z
V
OUT = 0 to V
DD
–1 uA 1 uA
Output High Voltage V
OH IOH = –4mA 2.4 —
Output Low Voltage V
OL ILO = +4mA — 0.4 V
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